The R8C core clock is generally referred to as BCLK. The CPU executes the shortest instructions in one BCLK cycle. In Divide-by-1 mode, a BCLK cycle is equal to the main clock frequency. Therefore, a device operating from a 20MHz oscillator circuit will complete a one-cycle instruction in 50ns. In the M16C core, which has a 16-bit data bus, memory accesses to internal RAM and ROM or Flash take only one clock cycle. In the R8C core, the 8-bit internal data bus doesn’t affect the speed of accessing 8-bit data. However, when accessing Word (16-bit) data, the CPU has to access the memory area twice to get two 8-bit units. Therefore, for R8C MCUs, a single-cycle Ram access becomes a two-cycle access. Special Function Register (SFR) accesses always take four cycles for R8C MCUs. By contrast, accesses to the SFR area take two cycles for M16C devices.