The RX Bus Error Monitoring system checks each memory access against a list of valid memory areas in the RX memory map. When errors are detected, an interrupt can be generated.

Status registers can then be used to determine which bus master created the fault, and the memory address that was accessed. There are two types of errors that can be detected; illegal address errors and timeout errors. Illegal address errors can be detected for both internal and external address areas. Attempting to read or write any of the internal reserved areas in the memory map will create a bus error. Similarly, a bus error will be flagged for any illegal accesses in the external chip select and SDRAM areas. Globally, the bus monitor is enabled with the Bus Error Monitoring Enable Register, BEREN. When this is done, monitoring of illegal accesses to the memory area for a particular chip select is turned on for disabled chip selects. This applies to the SDRAM controller also; if it is disabled and bus monitoring is turned on, then accesses to the SDRAM’s area in memory will generate a bus error. The RX Bus State Controller also protects against external devices hanging up the bus through the Bus Timeout Error. It was seen previously that the external chip selects support an external wait signal from connected devices. Bus Timeout monitoring applies only to those areas of the memory map covered by the external chip selects. A timeout occurs when the wait signal is asserted for too long by an external device. This feature is enabled in the Bus Error Monitoring Enable Register by setting the TOEN bit.