The register set for configuring each chip select is relatively simple, although a lot of options are packed into each register, it is recommended to check the hardware manual for full details.

Each chip select has a mode register that sets the access mode, whether or not to use the hardware wait signal, which can enable faster page access modes if the external devices support them. A control register turns the chip select on and off sets the bus width. The endian for each chip select can be set to match the processor’s endian setting, or to use the endian setting that is opposite to the processor’s. Three timing registers govern the insertion of wait states at all stages of reads from, and writes to, the external device. These provide a great amount of flexibility and allow the RX to be easily connected to a wide range of memory and peripheral devices without the need for glue logic. Even if the designer is not using the external BCLK signal, BCLK must be set up properly in the clock generation circuit since all of the wait timings in these registers are multiples of BLCK. Detailed timing diagrams in the hardware manual show the insertion points of each of the configurable wait periods.