There are eight external chip selects, CS0 through CS7. Each has a dedicated hardware pin and a dedicated area in the RX memory map. Shown on this slide is the memory map for chip selects 1 through 7. CS0 is special in that it overlaps the very top of memory and the on-board program flash in the chip. Since only very unique applications would use CS0 it is not covered in this presentation. A 16Mb window is reserved for each chip select and a number of features that can be set independently for each chip select including whether to use big or little endian mode when reading and writing the device, the access width of the memory or device attached and very flexible timing settings that allow the RX to be connected to a wide range of external memory devices and peripherals. This flexibility is expanded by selecting one of the two available bus interface modes for each chip select, either a single write strobe mode with four byte strobe lines in addition to the main write signal, or a byte strobe mode which uses four independent write signals for multiple byte width devices. The “Buses” chapter in the product hardware manual provides detailed diagrams that show the differences.