Some pointers for use with the programmable external chip selects are shown on this slide. First, when designing a PC board, remember that CS0 is special in that it overlaps the top of internal memory, including the reset vector and on-chip program flash. Unless there are very specific needs for this type of setup, and the user intends to disable the internal ROM, Renesas recommends that chip selects one through seven be used instead. Next, though the BCLK signal might not be used on the board, there may still be an advantage to setting the BCLK to a higher multiplier. All of the wait states for the chip selects are in multiples of BLCK, so a higher rate will result in more resolution on the timing settings at the expense of a shorter overall period. Another tip is that the Endian setting for a chip select is relative to the processor’s operating mode, so if a design allows the processor’s operating mode to be changed then the code must read the mode before setting up the chip select appropriately. Also a programming note, when possible, try to align data on natural boundaries. That is, 32-bit values should be aligned on long-word boundaries, and 16-bit values on word boundaries. This can make the difference between taking three cycles to access a variable versus a single cycle. The Renesas compiler for the RX has linker commands that group 8-, 16-, and 32-bit together to reduce any wasted space and to help keep data at natural boundaries. And finally, the RX does not support crossing chip select regions in a single access. Modularize the code or data to ensure that this does not happen at run time.