This slide shows the SDRAM controller hardware pins on the RX. The first to review is the external data bus. The data bus can be up to 32-bits wide, or the width can be limited to 8- or 16-bits and reclaim some I/O pins by setting the port function control registers appropriately. The RX external address bus has twenty four address lines, though only A0 through A18 are used by the SDRAM controller. It is possible to limit the number of address lines used with the port function control registers. Note that the number of bits on the data and address buses available to the application might be limited based on the package used in the design. The DQM signals indicate which bits of the data bus, in blocks of eight, are valid during a given transaction. QM0 is for D0 through D7, DQM1 for D8 through D15, and so on. Standard SDRAM control signals, including chip select, RAS, CAS, write enable, and clock enable are all provided. Finally, the SDRAM clock signal synchronizes and paces all of the other SDRAM control signals.