Looking at the RX memory map again, it can be seen that the SDRAM controller, like the external chip selects, has a dedicated area in memory. The SDRAM controller occupies a 128Mb window in the RX memory map and implements the industry-standard interface adopted by SDRAM manufacturers. This includes multiplexed row and column addresses, with a configurable row shift of 8-, 9-, 10- or 11-bits. The external data bus can be set to 8-, 16-, or 32-bits wide, allowing easy connection to a wide range of SDRAMs. Intervals for auto-refresh are configurable up to 4096 cycles to match the SDRAM's timing requirements, and support for self refresh mode allows the user to reduce system power. The selectable CAS latency can be set from one to three SDCLK cycles. The SDRAM controller also includes a configurable sequencer to issue SDRAM initialization commands to the external memory.  It is possible to configure the number of cycles for pre-charge and auto-refresh cycles, and the total number of times to repeat the sequence, up to fifteen times. Setting the mode register in the SDRAM is accomplished with a single register in the RX controller. Prior to setting up the SDRAM controller, it will be necessary to set the proper values in one or more port function control registers to enable signals such as the SDCLK signal, and to turn on external bus signals like the data and address lines.