In full-rate CMOS mode, the data output bits normally change at the same time as the falling edge of CLKOUT+, so the rising edge of CLKOUT+ can be used to latch the output data. In double data rate CMOS and LVDS modes, the data output bits normally change at the same time on both the falling and rising edges of CLKOUT+. To allow adequate setup-and-hold time when latching the data, the CLKOUT+ signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature and this is generally the best place to adjust the timing. The LTC2262 family can also delay the CLKOUT+ and CLKOUT– signals relative to the digital outputs using the serial programming mode. The output clock can be shifted by 0°, 45°, 90°, or 135°. To use the phase shifting feature, the clock duty cycle stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and CLKOUT–, independently of the phase shift. The combination of these two features enables phase shifts of 45° to 315° to match setup and hold times of the receiving device.