In addition to the alternate bit polarity mode, an optional data output randomizer is available for reducing interference from the digital outputs. The randomizer decorrelates the digital output to reduce the likelihood of repetitive code patterns that couple back into the ADC input, causing unwanted tones in the output spectrum. By randomizing the digital output before it is transmitted off-chip, these unwanted tones can be randomized, which reduces the unwanted tone amplitude. The digital output is randomized by applying an exclusive-OR logic operation between the least significant bit and all other data output bits. To decode, the reverse operation is applied in the FPGA. The digital output randomizer is independent of the alternate bit polarity mode; either, both, or neither function can be on at the same time. The output randomizer is enabled via serial programming. Both digital feedback techniques (alternate bit polarity mode and the data output randomizer) have been shown to improve SFDR performance 10 to 15dB, as demonstrated on the next slide.