The signal quality of the encode inputs strongly affects the ADC noise performance. The encode inputs should be treated as analog signals and should not be routed next to digital traces on the circuit board. There are two modes of operation for the encode inputs: differential encode mode and single-ended encode mode. The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs. The single-ended encode mode should be used with CMOS encode inputs. Fast clock edges are desirable to achieve the highest SNR performance; therefore, square waves should be used where possible. Driving single-ended can achieve slightly better jitter performance, thereby improving SNR. For good performance, the encode signal should have a 50% (±5%) duty cycle. If the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the encode signal changes frequency or is turned off, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock.