The two DA Data registers shown here (one for each channel) indirectly represent the desired analog output in that they actually just control the duty cycle of the output pin. Later in this presentation, an example will be given of the program/driver code. Users will see that in the PWM14 driver, a simple algorithm can be used to relate a value to a desired analog output. One feature of the architecture of the PWM D/A is that customers can use it at resolutions less than 14-bits and thus reduce its conversion time. As the user starts masking the DAn bits (from the bottom), the conversion will essentially complete faster. For example in 12-bit mode, bits DA0 and DA1 are masked (i.e., always write to 0, mask=0x3ffc). The driver that will be presented later supports 14-, 12- and 10-bit resolution. As is shown on the illustration in this slide, both of the DA Data registers have a Carrier Frequency Select (CFS) bit. This bit determines the fundamental clock rate that the D/A generates on the PWM output pin. When CFS = 0, the base cycle = T (processor clock frequency) x 64. Please remember that when CFS=0, the Data Register is limited to the range of 0x0401 to 0xfffd (count value 0x100 through 0x3fff). When CFS = 1, the base cycle = T x 256. In this condition, the Data register is limited to the range of 0x103 to 0xfffd (count value 0x40 to 0x3fff). These points will be summarized in an upcoming illustration. A good question to ask is:  What happens when values are written outside of the range defined by the CFS bit? Well, depending on the setting of the Output Select (OS) bit in the control register, the output will either be a solid low or solid high.