This page shows how all of these settings control the PWM output. For a full conversion to occur with 14-bit resolution, the counter must cycle through all 14-bits. This fact is a basis for the conversion time. There are two settings for CKS and two settings for CFS, so the user will have a total of four base cycles from which to choose. This slide gives a look at the conversion time and the CFS setting together. Consider an example using an H8 MCU running from a 10MHz clock. It might seem that the conversion time appears fixed, based on the settings of CFS and CKS, but that is not the case. Remember that the user can mask the upper bits of the PWM Data register and reduce the conversion time accordingly. If the resolution is reduced to 12-bits, that is, divide the resolution by 4, the conversion time is also reduced by a factor of 4, to 1638.4µs/4 = 409.6µs. Customers can achieve a further factor-of-4 savings in conversion time by reducing the resolution to 10-bits (T = 102.4µs). Obviously, the conversion time varies with the processor clock and the processor performance will “track” conversion time. Therefore, to a lesser extent, the processor performance has a minor impact on the maximum frequency users can recreate with the PWM D/A converter.