The LPC32x0 has a multi-layer AHB matrix for inter-block communication. AHB is an ARM defined high-speed bus, which is part of the ARM bus architecture. For systems that have only one (CPU), or two (for instance a CPU and a DMA), a simple AHB works well. However, if a system requires multiple bus masters and the CPU needs access to external memory, a single AHB bus can cause a bottleneck. There are seven masters in this device, each with a dedicated bus – a CPU instruction bus, a CPU data bus, two DMA bus masters each with eight channels, an Ethernet controller, a USB controller, and an LCD controller. They interconnect with the various slaves over the AHB matrix. There will not be any arbitration delays unless two masters attempt to access the same slave at the same time.