Digital to Analog Converters (DAC)

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18µs (Typ)
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2.7V ~ 5.5V
2.7V ~ 5.5V
±1.2, ±0.25
String DAC
-40°C ~ 105°C
8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
8-uMAX/uSOP
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2,500 : $12.24715
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16
1
18µs (Typ)
Voltage - Buffered
No
SPI, DSP
External
2.7V ~ 5.5V
2.7V ~ 5.5V
±1.2, ±0.25
String DAC
-40°C ~ 105°C
8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
8-uMAX/uSOP
Surface Mount
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About ADC Converters


An analog-to-digital converter (ADC) converts real-world signals, sensors, audio, current shunts, into digital data, but the bits on the label aren't the bits you get. A "16-bit ADC" may deliver closer to 13–14 effective bits in many real-world conditions (especially at higher input frequencies) because real performance is governed by noise and distortion, not resolution alone. The metric that captures this is Effective Number of Bits (ENOB): it reflects how many bits are truly usable after noise and nonlinearity are accounted for, and it's calculated from SINAD (signal-to-noise-and-distortion ratio). When evaluating datasheets look for plots like SINAD- or ENOB-vs-input-frequency, along with INL/DNL graphs, these tell you how the ADC actually behaves across your signal range and under real operating conditions. Beyond the converter itself, your signal chain determines your ceiling: a poorly matched driver amplifier is one of the most common reasons a high-resolution ADC underperforms, and reference voltage instability will corrupt accuracy regardless of how well everything else is designed. Anti-alias filtering also deserves attention. Without a proper filter before the input, out-of-band noise folds back into the baseband and appears as valid in-band data.

For architecture selection, match your signal characteristics to the converter type using this as a guide: Sigma-delta ADCs are ideal for slow, high-resolution measurements. A medical ECG application, for example, demands both high ENOB and strong common-mode rejection to extract microvolt-level cardiac signals from a noisy body environment, and sigma-delta's oversampling and digital filtering make it the natural fit. SAR ADCs are the workhorse choice for industrial applications such as 4–20mA process control loops, where deterministic timing, moderate resolution, and low power consumption matter more than raw speed, and where their balance of resolution, throughput, and predictable latency is difficult to match. Pipelined ADCs dominate communications and RF sampling applications where throughput is the governing requirement; in these contexts, metrics like SFDR and SINAD (or THD+N, depending on the application) become more critical than SNR alone. Flash ADCs are reserved for ultra-high-speed niche applications due to their power and complexity cost. To make your selection, work through these steps in order: define your signal bandwidth, set your sampling rate (at least 2× your signal bandwidth, with margin for filtering), determine the ENOB your application actually requires, select an architecture, then validate your front-end driver and voltage reference. Matching architecture to requirements, rather than chasing the highest-resolution part available, is what separates a working design from one that disappoints on the bench.

Even a well-chosen ADC will underperform if the system around it isn't right, so knowing where to look when measured results fall short of expectations is as important as the selection process itself. If your ENOB is lower than the datasheet suggests it should be, the driver amplifier and voltage reference are the first suspects, as noise or instability in either will directly compress effective resolution. An unexpectedly high noise floor that doesn't improve with signal averaging usually points to PCB layout: ground plane splits, inadequate supply decoupling near the analog inputs, or digital switching noise coupling into the analog domain are the most common culprits. If you're seeing missing codes or pronounced nonlinearity, check reference stability and decoupling first, then verify the input signal isn't overdriving the front end or violating timing constraints. Aliasing artifacts (frequency components that shouldn't be present in your sampled data) almost always indicate insufficient anti-alias filter rolloff before the input stage. In each case the diagnostic path is the same: isolate the signal chain one stage at a time, starting at the input and working toward the digital output, and compare measured SNR and THD against the datasheet conditions (input frequency, amplitude, sampling rate, and test setup) under which those specs were tested.