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Clock and Data Distribution Products Part 2 Slide 34

The P3P8163A has a single LVCMOS input and three LVCMOS outputs. Two of these outputs are copies of the inputs and make no use of the internal PLL. The third output is a 12 MHz clock which is modulated by the internal PLL at + or – 0.4%. This device is suitable for consumer electronics applications.

PTM Published on: 2014-08-04