MAXREFDES34#: Secure Authentication, SHA-256

The Alcatraz (MAXREFDES34#) subsystem provides a reference design for securing Xilinx FPGAs to protect IP and prevent attached peripheral counterfeiting. The system implements a SHA-256 challenge-response between the FPGA and a DS28E15 secure authenticator. Boards for purchase, hardware, and firmware design files provide complete system information for rapid prototyping and development.

Smart factories, industrial and medical applications employ the flexibility and high performance of modern FPGAs. As these systems become increasingly connected, security emerges as a paramount feature to protect IP, enable system features using software and prevent counterfeiting. The Alcatraz (MAXREFDES34#) subsystem reference design uses the DS28E15 to immediately implement SHA-256 authentication on Xilinx® FPGAs. The DS28E15 communicates over the single contact 1-Wire® bus, reducing the number of pins necessary to carry out the solution. The reference code defines a combined SHA-256 processor and 1-Wire Master on the host FPGA.