PIC18Fxx20 Datasheet by Microchip Technology

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 2003-2013 Microchip Technology Inc. DS39609C-page 1

PIC18F6520/8520/6620/

8620/6720/8720

High-Performance RISC CPU:

• C compiler optimized architecture/instruction set:

- Source code compatible with the PIC16 and

PIC17 instruction sets

• Linear program memory addressing to 128 Kbytes

• Linear data memory addressing to 3840 bytes

• 1 Kbyte of data EEPROM

• Up to 10 MIPs operation:

- DC – 40 MHz osc./clock input

- 4 MHz – 10 MHz osc./clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path

• Priority levels for interrupts

• 31-level, software accessible hardware stack

• 8 x 8 Single Cycle Hardware Multiplier

External Memory Interface

(PIC18F8X20 Devices Only):

• Address capability of up to 2 Mbytes

• 16-bit interface

Peripheral Features:

• High current sink/source 25 mA/25 mA

• Four external interrupt pins

• Timer0 module: 8-bit/16-bit timer/counter

• Timer1 module: 16-bit timer/counter

• Timer2 module: 8-bit timer/counter

• Timer3 module: 16-bit timer/counter

• Timer4 module: 8-bit timer/counter

• Secondary oscillator clock option – Timer1/Timer3

• Five Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resolution 6.25 ns (TCY/16)

- Compare is 16-bit, max. resolution 100 ns (TCY)

- PWM output: PWM resolution is 1 to 10-bit

• Master Synchronous Serial Port (MSSP) module

with two modes of operation:

- 3-wire SPI (supports all 4 SPI modes)

-I

2C™ Master and Slave mode

• Two Addressable USART modules:

- Supports RS-485 and RS-232

• Parallel Slave Port (PSP) module

Analog Features:

• 10-bit, up to 16-channel Analog-to-Digital

Converter (A/D):

- Conversion available during Sleep

• Programmable 16-level Low-Voltage Detection

(LVD) module:

- Supports interrupt on Low-Voltage Detection

• Programmable Brown-out Reset (PBOR)

• Dual analog comparators:

- Programmable input/output configuration

Special Microcontroller Features:

• 100,000 erase/write cycle Enhanced Flash

program memory typical

• 1,000,000 erase/write cycle Data EEPROM

memory typical

• 1 second programming time

• Flash/Data EEPROM Retention: > 40 years

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own On-Chip

RC Oscillator for reliable operation

• Programmable code protection

• Power saving Sleep mode

• Selectable oscillator options including:

- 4X Phase Lock Loop (of primary oscillator)

- Secondary Oscillator (32 kHz) clock input

• In-Circuit Serial Programming™ (ICSP™) via

two pins

• MPLAB® In-Circuit Debug (ICD) via two pins

CMOS Technology:

• Low-power, high-speed Flash technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Industrial and Extended temperature ranges

Device

Program Memory Data Memory

I/O 10-bit

A/D

(ch)

CCP

(PWM)

MSSP

USART Timers

8-bit/16-bit Ext

Bus

Max

FOSC

(MHz)

Bytes # Single-Word

Instructions SRAM

(bytes) EEPROM

(bytes) SPI Master

I2C

PIC18F6520 32K 16384 2048 1024 52 12 5 Y Y 2 2/3 N 40

PIC18F6620 64K 32768 3840 1024 52 12 5 Y Y 2 2/3 N 25

PIC18F6720 128K 65536 3840 1024 52 12 5 Y Y 2 2/3 N 25

PIC18F8520 32K 16384 2048 1024 68 16 5 Y Y 2 2/3 Y 40

PIC18F8620 64K 32768 3840 1024 68 16 5 Y Y 2 2/3 Y 25

PIC18F8720 128K 65536 3840 1024 68 16 5 Y Y 2 2/3 Y 25

64/80-Pin High-Performance, 256 Kbit to 1 Mbit

Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 2  2003-2013 Microchip Technology Inc.

Pin Diagrams

PIC18F6620

RE2/CS

RE3

RE4

RE5

RE6

RE7/CCP2(1)

RD0/PSP0

VDD

VSS

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

RE1/WR

RE0/RD

RG0/CCP3

RG1/TX2/CK2

RG2/RX2/DT2

RG3/CCP4

MCLR/VPP

RG4/CCP5

VSS

VDD

RF7/SS

RF6/AN11

RF4/AN9

RF3/AN8

RF2/AN7/C1OUT

RB0/INT0

RB1/INT1

RB2/INT2

RB3/INT3

RB4/KBI0

RB5/KBI1/PGM

RB6/KBI2/PGC

VSS

OSC2/CLKO/RA6

OSC1/CLKI

VDD

RB7/KBI3/PGD

RC4/SDI/SDA

RC3/SCK/SCL

RC2/CCP1

RF0/AN5

RF1/AN6/C2OUT

AVDD

AVSS

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

VSS

VDD

RA4/T0CKI

RA5/AN4/LVDIN

RC1/T1OSI/CCP2(1)

RC0/T1OSO/T13CKI

RC7/RX1/DT1

RC6/TX1/CK1

RC5/SDO

PIC18F6720

RF5/AN10/CVREF

64-Pin TQFP

PIC18F6520

Note 1: CCP2 is multiplexed with RC1 when CCP2MX is set.

 2003-2013 Microchip Technology Inc. DS39609C-page 3

PIC18F6520/8520/6620/8620/6720/8720

Pin Diagrams (Continued)

PIC18F8620

RE2/CS/AD10(3)

RE3/AD11

RE4/AD12

RE5/AD13

RE6/AD14

RE7/CCP2/AD15(2)

RD0/PSP0/AD0(3)

VDD

VSS

RD1/PSP1/AD1(3)

RD2/PSP2/AD2(3)

RD3/PSP3/AD3(3)

RD4/PSP4/AD4(3)

RD5/PSP5/AD5(3)

RD6/PSP6/AD6(3)

RD7/PSP7/AD7(3)

RE1/WR/AD9(3)

RE0/RD/AD8(3)

RG0/CCP3

RG1/TX2/CK2

RG2/RX2/DT2

RG3/CCP4

MCLR/VPP

RG4/CCP5

VSS

VDD

RF7/SS

RF6/AN11

RF5/AN10/CVREF

RF4/AN9

RF3/AN8

RF2/AN7/C1OUT

RB0/INT0

RB1/INT1

RB2/INT2

RB3/INT3/CCP2(1)

RB4/KBI0

RB5/KBI1/PGM

RB6/KBI2/PGC

VSS

OSC2/CLKO/RA6

OSC1/CLKI

VDD

RB7/KBI3/PGD

RC4/SDI/SDA

RC3/SCK/SCL

RC2/CCP1

RF0/AN5

RF1/AN6/C2OUT

AVDD

AVSS

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

VSS

VDD

RA4/T0CKI

RA5/AN4/LVDIN

RC1/T1OSI/CCP2(1)

RC7/RX1/DT1

RC6/TX1/CK1

RC5/SDO

RJ0/ALE

RJ1/OE

RH1/A17

RH0/A16

RH2/A18

RH3/A19

RH7/AN15

RH6/AN14

RH5/AN13

RH4/AN12

RJ5/CE

RJ4/BA0

RJ7/UB

RJ6/LB

RJ2/WRL

RJ3/WRH

80-Pin TQFP

PIC18F8720

RC0/T1OSO/T13CKI

PIC18F8520

Note 1: CCP2 is multiplexed with RC1 when CCP2MX is set.

2: CCP2 is multiplexed by default with RE7 when the device is configured in Microcontroller mode.

3: PSP is available only in Microcontroller mode.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 4  2003-2013 Microchip Technology Inc.

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Oscillator Configurations ............................................................................................................................................................ 21

3.0 Reset.......................................................................................................................................................................................... 29

4.0 Memory Organization ................................................................................................................................................................. 39

5.0 Flash Program Memory.............................................................................................................................................................. 61

6.0 External Memory Interface ......................................................................................................................................................... 71

7.0 Data EEPROM Memory ............................................................................................................................................................. 79

8.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 85

9.0 Interrupts .................................................................................................................................................................................... 87

10.0 I/O Ports ................................................................................................................................................................................... 103

11.0 Timer0 Module ......................................................................................................................................................................... 131

12.0 Timer1 Module ......................................................................................................................................................................... 135

13.0 Timer2 Module ......................................................................................................................................................................... 141

14.0 Timer3 Module ......................................................................................................................................................................... 143

15.0 Timer4 Module ......................................................................................................................................................................... 147

16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 149

17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 157

18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 197

19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 213

20.0 Comparator Module.................................................................................................................................................................. 223

21.0 Comparator Voltage Reference Module................................................................................................................................... 229

22.0 Low-Voltage Detect .................................................................................................................................................................. 233

23.0 Special Features of the CPU.................................................................................................................................................... 239

24.0 Instruction Set Summary .......................................................................................................................................................... 259

25.0 Development Support............................................................................................................................................................... 301

26.0 Electrical Characteristics .......................................................................................................................................................... 305

27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 341

28.0 Packaging Information.............................................................................................................................................................. 355

Appendix A: Revision History............................................................................................................................................................. 361

Appendix B: Device Differences......................................................................................................................................................... 361

Appendix C: Conversion Considerations ........................................................................................................................................... 362

Appendix D: Migration from Mid-range to Enhanced Devices ........................................................................................................... 362

Appendix E: Migration from High-end to Enhanced Devices ............................................................................................................. 363

The Microchip Web Site..................................................................................................................................................................... 375

Customer Change Notification Service .............................................................................................................................................. 375

Customer Support .............................................................................................................................................................................. 375

Reader Response .............................................................................................................................................................................. 376

PIC18F6520/8520/6620/8620/6720/8720 Product Identification System .......................................................................................... 377

 2003-2013 Microchip Technology Inc. DS39609C-page 5

PIC18F6520/8520/6620/8620/6720/8720

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PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 6  2003-2013 Microchip Technology Inc.

NOTES:

 2003-2013 Microchip Technology Inc. DS39609C-page 7

PIC18F6520/8520/6620/8620/6720/8720

1.0 DEVICE OVERVIEW

This document contains device specific information for

the following devices:

This family offers the same advantages of all PIC18

microcontrollers – namely, high computational

performance at an economical price – with the addition of

high endurance Enhanced Flash program memory. The

PIC18FXX20 family also provides an enhanced range of

program memory options and versatile analog features

that make it ideal for complex, high-performance

applications.

1.1 Key Features

1.1.1 EXPANDED MEMORY

The PIC18FXX20 family introduces the widest range of

on-chip, Enhanced Flash program memory available

on PIC® microcontrollers – up to 128 Kbyte (or 65,536

words), the largest ever offered by Microchip. For users

with more modest code requirements, the family also

includes members with 32 Kbyte or 64 Kbyte.

Other memory features are:

•Data RAM and Data EEPROM: The

PIC18FXX20 family also provides plenty of room

for application data. Depending on the device,

either 2048 or 3840 bytes of data RAM are

available. All devices have 1024 bytes of data

EEPROM for long-term retention of nonvolatile

data.

•Memory Endurance: The Enhanced Flash cells

for both program memory and data EEPROM are

rated to last for many thousands of erase/write

cycles – up to 100,000 for program memory and

1,000,000 for EEPROM. Data retention without

refresh is conservatively estimated to be greater

than 40 years.

1.1.2 EXTERNAL MEMORY INTERFACE

In the event that 128 Kbytes of program memory is

inadequate for an application, the PIC18F8X20

members of the family also implement an External

Memory Interface. This allows the controller’s internal

program counter to address a memory space of up to

2 Mbytes, permitting a level of data access that few

8-bit devices can claim.

With the addition of new operating modes, the External

Memory Interface offers many new options, including:

• Operating the microcontroller entirely from external

memory

• Using combinations of on-chip and external

memory, up to the 2-Mbyte limit

• Using external Flash memory for reprogrammable

application code, or large data tables

• Using external RAM devices for storing large

amounts of variable data

1.1.3 EASY MIGRATION

Regardless of the memory size, all devices share the

same rich set of peripherals, allowing for a smooth

migration path as applications grow and evolve.

The consistent pinout scheme used throughout the

entire family also aids in migrating to the next larger

device. This is true when moving between the 64-pin

members, between the 80-pin members, or even

jumping from 64-pin to 80-pin devices.

1.1.4 OTHER SPECIAL FEATURES

•Communications: The PIC18FXX20 family

incorporates a range of serial communications

peripherals, including 2 independent USARTs and

a Master SSP module, capable of both SPI and

I2C (Master and Slave) modes of operation. For

PIC18F8X20 devices, one of the general purpose

I/O ports can be reconfigured as an 8-bit Parallel

Slave Port for direct processor-to-processor

communications.

•CCP Modules: All devices in the family

incorporate five Capture/Compare/PWM modules

to maximize flexibility in control applications. Up

to four different time bases may be used to

perform several different operations at once.

•Analog Features: All devices in the family

feature 10-bit A/D converters, with up to 16 input

channels, as well as the ability to perform

conversions during Sleep mode. Also included

are dual analog comparators with programmable

input and output configuration, a programmable

Low-Voltage Detect module and a programmable

Brown-out Reset module.

•Self-programmability: These devices can write

to their own program memory spaces under inter-

nal software control. By using a bootloader routine

located in the protected Boot Block at the top of

program memory, it becomes possible to create

an application that can update itself in the field.

• PIC18F6520 • PIC18F8520

• PIC18F6620 • PIC18F8620

• PIC18F6720 • PIC18F8720

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 8  2003-2013 Microchip Technology Inc.

1.2 Details on Individual Family

Members

The PIC18FXX20 devices are available in 64-pin and

80-pin packages. They are differentiated from each

other in five ways:

1. Flash program memory (32 Kbytes for

PIC18FX520 devices, 64 Kbytes for

PIC18FX620 devices and 128 Kbytes for

PIC18FX720 devices)

2. Data RAM (2048 bytes for PIC18FX520

devices, 3840 bytes for PIC18FX620 and

PIC18FX720 devices)

3. A/D channels (12 for PIC18F6X20 devices,

16 for PIC18F8X20)

4. I/O pins (52 on PIC18F6X20 devices, 68 on

PIC18F8X20)

5. External program memory interface (present

only on PIC18F8X20 devices)

All other features for devices in the PIC18FXX20 family

are identical. These are summarized in Table 1-1.

Block diagrams of the PIC18F6X20 and PIC18F8X20

devices are provided in Figure 1-1 and Figure 1-2,

respectively. The pinouts for these device families are

listed in Table 1-2.

TABLE 1-1: PIC18FXX20 DEVICE FEATURES

Features PIC18F6520 PIC18F6620 PIC18F6720 PIC18F8520 PIC18F8620 PIC18F8720

Operating Frequency DC – 40 MHz DC – 25 MHz DC – 25 MHz DC – 40 MHz DC – 25 MHz DC – 25 MHz

Program Memory

(Bytes)

32K 64K 128K 32K 64K 128K

Program Memory

(Instructions)

16384 32768 65536 16384 32768 65536

Data Memory

(Bytes)

2048 3840 3840 2048 3840 3840

Data EEPROM

Memory (Bytes)

1024 1024 1024 1024 1024 1024

External Memory

Interface

No No No Yes Yes Yes

Interrupt Sources 17 17 17 18 18 18

I/O Ports Ports A, B, C,

D, E, F, G

Ports A, B, C, D,

E, F, G

Ports A, B, C, D,

E, F, G

Ports A, B, C,

D, E, F, G, H, J

Ports A, B, C,

D, E, F, G, H, J

Ports A, B, C,

D, E, F, G, H, J

Timers 5 5 5 5 5 5

Capture/Compare/

PWM Modules

55 5555

Serial Communications MSSP,

Addressable

USART (2)

MSSP,

Addressable

USART (2)

MSSP,

Addressable

USART (2)

MSSP,

Addressable

USART (2)

MSSP,

Addressable

USART (2)

MSSP,

Addressable

USART (2)

Parallel Communications PSP PSP PSP PSP PSP PSP

10-bit Analog-to-Digital

Module

12 input

channels

12 input

channels

12 input

channels

16 input

channels

16 input

channels

16 input

channels

Resets (and Delays) POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

Programmable

Low-Voltage Detect

Yes Yes Yes Yes Yes Yes

Programmable

Brown-out Reset

Yes Yes Yes Yes Yes Yes

Instruction Set 77 Instructions 77 Instructions 77 Instructions 77 Instructions 77 Instructions 77 Instructions

Package 64-pin TQFP 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP

 2003-2013 Microchip Technology Inc. DS39609C-page 9

PIC18F6520/8520/6620/8620/6720/8720

FIGURE 1-1: PIC18F6X20 BLOCK DIAGRAM

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

OSC2/CLKO

MCLR/VPP VDD, VSS

PORTA

PORTB

PORTC

RA4/T0CKI

RA5/AN4/LVDIN

RB0/INT0

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX1/CK1

RC7/RX1/DT1

Brown-out

Reset

USART1

Comparator

Synchronous

BOR

Serial Port

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

Timing

Generation

RB1/INT1

Data Latch

Data RAM

Address Latch

Address<12>

Bank0, F

BSR FSR0

FSR1

FSR2

inc/dec

logic

Decode

412 4

PCH PCL

PCLATH

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

WREG

BITOP 8

ALU<8>

Address Latch

Program Memory

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

PORTD

RD7/PSP7:RD0/PSP0

RB2/INT2

RB3/INT3

PCLATU

PCU

Precision

Reference

Band Gap

PORTE

PORTF

PORTG RG0/CCP3

RG1/TX2/CK2

RG2/RX2/DT2

RG3/CCP4

RG4/CCP5

RF7/SS

RE6

RE7/CCP2

RE5

RE4

RE3

RE2/CS

RE0/RD

RE1/WR

LVD

RA6

Timer0 Timer1 Timer2 Timer3 Timer4

CCP1 CCP2 CCP3 CCP4 CCP5

USART2

10-bit

A/D

RF6/AN11

RF5/AN10/CVREF

RF4/AN9

RF3/AN8

RF2/AN7/C1OUT

RF0/AN5

RF1/AN6/C2OUT

RB4/KBI0

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

Data

EEPROM

0&E was

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 10  2003-2013 Microchip Technology Inc.

FIGURE 1-2: PIC18F8X20 BLOCK DIAGRAM

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

OSC2/CLKO

MCLR/VPP VDD, VSS

PORTA

PORTB

PORTC

RA4/T0CKI

RA5/AN4/LVDIN

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX1/CK1

RC7/RX1/DT1

Brown-out

Reset

USART1

Comparator

Synchronous

BOR

Serial Port

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

Timing

Generation

10-bit

A/D

Data Latch

Data RAM

Address Latch

Address<12>

Bank0, F

BSR FSR0

FSR1

FSR2

inc/dec

logic

Decode

412 4

PCH PCL

PCLATH

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

WREG

BITOP 8

ALU<8>

Address Latch

Program Memory

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

PORTD

RD7/PSP7/AD7:

PCLATU

PCU

Precision

Reference

Band Gap

PORTE

PORTF

PORTG RG0/CCP3

RG1/TX2/CK2

RG2/RX2/DT2

RG3/CCP4

RG4/CCP5

RF7/SS

RE6/AD14

RE7/CCP2/AD15

RE5/AD13

RE4/AD12

RE3/AD11

RE2/CS/AD10

RE0/RD/AD8

RE1/WR/AD9

LVD

PORTH

PORTJ

RJ0/ALE

RJ1/OE

RJ2/WRL

RJ3/WRH

RA6

Timer0 Timer1 Timer2 Timer3 Timer4

CCP1 CCP2 CCP3 CCP4 CCP5

USART2

System Bus Interface

AD15:AD0, A19:A16(1)

Note 1: External memory interface pins are physically multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).

RB0/INT0

RB1/INT1

RB2/INT2

RB3/INT3/CCP2

RB4/KBI0

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

RH7/AN15:RH4/AN12

RH3/AD19:RH0/AD16

RJ4/BA0

RJ5/CE

RJ6/LB

RJ7/UB

RF6/AN11

RF5/AN10/CVREF

RF4/AN9

RF3/AN8

RF2/AN7/C1OUT

RF0/AN5

RF1/AN6/C2OUT

Data

EEPROM

RD0/PSP0/AD0

 2003-2013 Microchip Technology Inc. DS39609C-page 11

PIC18F6520/8520/6620/8620/6720/8720

TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS

Pin Name Pin Number Pin

Type Buffer

Type Description

PIC18F6X20 PIC18F8X20

MCLR/VPP

MCLR

VPP

Master Clear (input) or programming

voltage (output).

Master Clear (Reset) input. This pin is

an active-low Reset to the device.

Programming voltage input.

OSC1/CLKI

OSC1

CLKI

39 49 I

CMOS/ST

CMOS

Oscillator crystal or external clock input.

Oscillator crystal input or external clock

source input. ST buffer when configured

in RC mode; otherwise CMOS.

External clock source input. Always

associated with pin function OSC1

(see OSC1/CLKI, OSC2/CLKO pins).

OSC2/CLKO/RA6

OSC2

CLKO

RA6

40 50 O

I/O

—

TTL

Oscillator crystal or clock output.

Oscillator crystal output.

Connects to crystal or resonator in

Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO,

which has 1/4 the frequency of OSC1

and denotes the instruction cycle rate.

General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I = Input O = Output

P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X20 devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for

proper operation of the part in user or ICSP modes. See parameter D001A for details.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 12  2003-2013 Microchip Technology Inc.

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

AN0

24 30 I/O

ITTL

Analog Digital I/O.

Analog input 0.

RA1/AN1

RA1

AN1

23 29 I/O

ITTL

Analog Digital I/O.

Analog input 1.

RA2/AN2/VREF-

RA2

AN2

VREF-

22 28 I/O

TTL

Analog

Digital I/O.

Analog input 2.

A/D reference voltage (Low) input.

RA3/AN3/VREF+

RA3

AN3

VREF+

21 27 I/O

TTL

Analog

Digital I/O.

Analog input 3.

A/D reference voltage (High) input.

RA4/T0CKI

RA4

T0CKI

28 34 I/O

ST/OD

Digital I/O – Open-drain when

configured as output.

Timer0 external clock input.

RA5/AN4/LVDIN

RA5

AN4

LVDIN

27 33 I/O

TTL

Analog

Digital I/O.

Analog input 4.

Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.

TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I = Input O = Output

P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X20 devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for

proper operation of the part in user or ICSP modes. See parameter D001A for details.

 2003-2013 Microchip Technology Inc. DS39609C-page 13

PIC18F6520/8520/6620/8620/6720/8720

PORTB is a bidirectional I/O port. PORTB

can be software programmed for internal

weak pull-ups on all inputs.

RB0/INT0

RB0

INT0

48 58 I/O

ITTL

ST Digital I/O.

External interrupt 0.

RB1/INT1

RB1

INT1

47 57 I/O

ITTL

ST Digital I/O.

External interrupt 1.

RB2/INT2

RB2

INT2

46 56 I/O

ITTL

ST Digital I/O.

External interrupt 2.

RB3/INT3/CCP2

RB3

INT3

CCP2(1)

45 55 I/O

I/O

TTL

Digital I/O.

External interrupt 3.

Capture2 input, Compare2 output,

PWM2 output.

RB4/KBI0

RB4

KBI0

44 54 I/O

ITTL

ST Digital I/O.

Interrupt-on-change pin.

RB5/KBI1/PGM

RB5

KBI1

PGM

43 53 I/O

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

Low-Voltage ICSP Programming enable

pin.

RB6/KBI2/PGC

RB6

KBI2

PGC

42 52 I/O

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and

ICSP programming clock.

RB7/KBI3/PGD

RB7

KBI3

PGD

37 47 I/O

I/O TTL

ST Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and

ICSP programming data.

TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I = Input O = Output

P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X20 devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for

proper operation of the part in user or ICSP modes. See parameter D001A for details.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 14  2003-2013 Microchip Technology Inc.

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

T1OSO

T13CKI

30 36 I/O

—

Digital I/O.

Timer1 oscillator output.

Timer1/Timer3 external clock input.

RC1/T1OSI/CCP2

RC1

T1OSI

CCP2(2)

29 35 I/O

I/O

CMOS

Digital I/O.

Timer1 oscillator input.

Capture2 input/Compare2 output/

PWM2 output.

RC2/CCP1

RC2

CCP1

33 43 I/O

I/O ST

ST Digital I/O.

Capture1 input/Compare1 output/

PWM1 output.

RC3/SCK/SCL

RC3

SCK

SCL

34 44 I/O

I/O

Digital I/O.

Synchronous serial clock input/output

for SPI mode.

Synchronous serial clock input/output

for I2C mode.

RC4/SDI/SDA

RC4

SDI

SDA

35 45 I/O

I/O

Digital I/O.

SPI data in.

I2C data I/O.

RC5/SDO

RC5

SDO

36 46 I/O

OST

—Digital I/O.

SPI data out.

RC6/TX1/CK1

RC6

TX1

CK1

31 37 I/O

I/O

—

Digital I/O.

USART 1 asynchronous transmit.

USART 1 synchronous clock

(see RX1/DT1).

RC7/RX1/DT1

RC7

RX1

DT1

32 38 I/O

I/O

Digital I/O.

USART 1 asynchronous receive.

USART 1 synchronous data

(see TX1/CK1).

TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I = Input O = Output

P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X20 devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for

proper operation of the part in user or ICSP modes. See parameter D001A for details.

 2003-2013 Microchip Technology Inc. DS39609C-page 15

PIC18F6520/8520/6620/8620/6720/8720

PORTD is a bidirectional I/O port. These

pins have TTL input buffers when external

memory is enabled.

RD0/PSP0/AD0

RD0

PSP0

AD0(3)

58 72 I/O

I/O

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 0.

RD1/PSP1/AD1

RD1

PSP1

AD1(3)

55 69 I/O

I/O

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 1.

RD2/PSP2/AD2

RD2

PSP2

AD2(3)

54 68 I/O

I/O

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 2.

RD3/PSP3/AD3

RD3

PSP3

AD3(3)

53 67 I/O

I/O

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 3.

RD4/PSP4/AD4

RD4

PSP4

AD4(3)

52 66 I/O

I/O

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 4.

RD5/PSP5/AD5

RD5

PSP5

AD5(3)

51 65 I/O

I/O

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 5.

RD6/PSP6/AD6

RD6

PSP6

AD6(3)

50 64 I/O

I/O

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 6.

RD7/PSP7/AD7

RD7

PSP7

AD7(3)

49 63 I/O

I/O

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 7.

TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I = Input O = Output

P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X20 devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for

proper operation of the part in user or ICSP modes. See parameter D001A for details.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 16  2003-2013 Microchip Technology Inc.

PORTE is a bidirectional I/O port.

RE0/RD/AD8

RE0

AD8(3)

I/O

TTL

Digital I/O.

Read control for Parallel Slave Port

(see WR and CS pins).

External memory address/data 8.

RE1/WR/AD9

RE1

AD9(3)

I/O

TTL

Digital I/O.

Write control for Parallel Slave Port

(see CS and RD pins).

External memory address/data 9.

RE2/CS/AD10

RE2

AD10(3)

64 78 I/O

I/O

TTL

Digital I/O.

Chip select control for Parallel Slave

Port (see RD and WR).

External memory address/data 10.

RE3/AD11

RE3

AD11(3)

63 77 I/O

I/O ST

TTL Digital I/O.

External memory address/data 11.

RE4/AD12

RE4

AD12

62 76 I/O

I/O ST

TTL Digital I/O.

External memory address/data 12.

RE5/AD13

RE5

AD13(3)

61 75 I/O

I/O ST

TTL Digital I/O.

External memory address/data 13.

RE6/AD14

RE6

AD14(3)

60 74 I/O

I/O ST

TTL Digital I/O.

External memory address/data 14.

RE7/CCP2/AD15

RE7

CCP2(1,4)

AD15(3)

59 73 I/O

I/O

TTL

Digital I/O.

Capture2 input/Compare2 output/

PWM2 output.

External memory address/data 15.

TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I = Input O = Output

P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X20 devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for

proper operation of the part in user or ICSP modes. See parameter D001A for details.

 2003-2013 Microchip Technology Inc. DS39609C-page 17

PIC18F6520/8520/6620/8620/6720/8720

PORTF is a bidirectional I/O port.

RF0/AN5

RF0

AN5

18 24 I/O

IST

Analog Digital I/O.

Analog input 5.

RF1/AN6/C2OUT

RF1

AN6

C2OUT

17 23 I/O

Analog

Digital I/O.

Analog input 6.

Comparator 2 output.

RF2/AN7/C1OUT

RF2

AN7

C1OUT

16 18 I/O

Analog

Digital I/O.

Analog input 7.

Comparator 1 output.

RF3/AN8

RF1

AN8

15 17 I/O

IST

Analog Digital I/O.

Analog input 8.

RF4/AN9

RF1

AN9

14 16 I/O

IST

Analog Digital I/O.

Analog input 9.

RF5/AN10/CVREF

RF1

AN10

CVREF

13 15 I/O

Analog

Digital I/O.

Analog input 10.

Comparator VREF output.

RF6/AN11

RF6

AN11

12 14 I/O

IST

Analog Digital I/O.

Analog input 11.

RF7/SS

RF7

11 13 I/O

IST

TTL Digital I/O.

SPI slave select input.

TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I = Input O = Output

P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X20 devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for

proper operation of the part in user or ICSP modes. See parameter D001A for details.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 18  2003-2013 Microchip Technology Inc.

PORTG is a bidirectional I/O port.

RG0/CCP3

RG0

CCP3

I/O

I/O ST

ST Digital I/O.

Capture3 input/Compare3 output/

PWM3 output.

RG1/TX2/CK2

RG1

TX2

CK2

I/O

—

Digital I/O.

USART 2 asynchronous transmit.

USART 2 synchronous clock

(see RX2/DT2).

RG2/RX2/DT2

RG2

RX2

DT2

I/O

Digital I/O.

USART 2 asynchronous receive.

USART 2 synchronous data

(see TX2/CK2).

RG3/CCP4

RG3

CCP4

I/O

I/O ST

ST Digital I/O.

Capture4 input/Compare4 output/

PWM4 output.

RG4/CCP5

RG4

CCP5

810

I/O

I/O ST

ST Digital I/O.

Capture5 input/Compare5 output/

PWM5 output.

TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I = Input O = Output

P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X20 devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for

proper operation of the part in user or ICSP modes. See parameter D001A for details.

 2003-2013 Microchip Technology Inc. DS39609C-page 19

PIC18F6520/8520/6620/8620/6720/8720

PORTH is a bidirectional I/O port(5).

RH0/A16

RH0

A16

—79

I/O

OST

TTL Digital I/O.

External memory address 16.

RH1/A17

RH1

A17

—80

I/O

OST

TTL Digital I/O.

External memory address 17.

RH2/A18

RH2

A18

—1

I/O

OST

TTL Digital I/O.

External memory address 18.

RH3/A19

RH3

A19

—2

I/O

OST

TTL Digital I/O.

External memory address 19.

RH4/AN12

RH4

AN12

—22

I/O

IST

Analog Digital I/O.

Analog input 12.

RH5/AN13

RH5

AN13

—21

I/O

IST

Analog Digital I/O.

Analog input 13.

RH6/AN14

RH6

AN14

—20

I/O

IST

Analog Digital I/O.

Analog input 14.

RH7/AN15

RH7

AN15

—19

I/O

IST

Analog Digital I/O.

Analog input 15.

TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I = Input O = Output

P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X20 devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for

proper operation of the part in user or ICSP modes. See parameter D001A for details.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 20  2003-2013 Microchip Technology Inc.

PORTJ is a bidirectional I/O port(5).

RJ0/ALE

RJ0

ALE

—62

I/O

OST

TTL Digital I/O.

External memory address latch enable.

RJ1/OE

RJ1

—61

I/O

OST

TTL Digital I/O.

External memory output enable.

RJ2/WRL

RJ2

WRL

—60

I/O

OST

TTL Digital I/O.

External memory write low control.

RJ3/WRH

RJ3

WRH

—59

I/O

OST

TTL Digital I/O.

External memory write high control.

RJ4/BA0

RJ4

BA0

—39

I/O

OST

TTL Digital I/O.

External memory Byte Address 0 control.

RJ5/CE

RJ5

—40

I/O

OST

TTL Digital I/O.

External memory chip enable control.

RJ6/LB

RJ6

—41

I/O

OST

TTL Digital I/O.

External memory low byte select.

RJ7/UB

RJ7

—42

I/O

OST

TTL Digital I/O.

External memory high byte select.

VSS 9, 25,

41, 56 11, 31,

51, 70 P — Ground reference for logic and I/O pins.

VDD 10, 26,

38, 57 12, 32,

48, 71 P — Positive supply for logic and I/O pins.

AVSS(6) 20 26 P — Ground reference for analog modules.

AVDD(6) 19 25 P — Positive supply for analog modules.

TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I = Input O = Output

P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X20 devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for

proper operation of the part in user or ICSP modes. See parameter D001A for details.

 2003-2013 Microchip Technology Inc. DS39609C-page 21

PIC18F6520/8520/6620/8620/6720/8720

2.0 OSCILLATOR

CONFIGURATIONS

2.1 Oscillator Types

The PIC18FXX20 devices can be operated in eight

different oscillator modes. The user can program three

configuration bits (FOSC2, FOSC1 and FOSC0) to

select one of these eight modes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HS+PLL High-Speed Crystal/Resonator

with PLL enabled

5. RC External Resistor/Capacitor

6. RCIO External Resistor/Capacitor with

I/O pin enabled

7. EC External Clock

8. ECIO External Clock with I/O pin

enabled

2.2 Crystal Oscillator/Ceramic

Resonators

In XT, LP, HS or HS+PLL Oscillator modes, a crystal or

ceramic resonator is connected to the OSC1 and

OSC2 pins to establish oscillation. Figure 2-1 shows

the pin connections.

The PIC18FXX20 oscillator design requires the use of

a parallel cut crystal.

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION

(HS, XT OR LP

CONFIGURATION)

TABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturer’s

specifications.

Note 1: See Table 2-1 and Table 2-2 for recommended

values of C1 and C2.

2: A series resistor (RS) may be required for AT

strip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

Logic

PIC18FXX20

RS(2)

Internal

Ranges Tested:

Mode Freq C1 C2

XT 455 kHz

2.0 MHz

4.0 MHz

68-100 pF

15-68 pF

68-100 pF

15-68 pF

HS 8.0 MHz

16.0 MHz 10-68 pF

10-22 pF 10-68 pF

10-22 pF

These values are for design guidance only.

See notes following this table.

Resonators Used:

2.0 MHz Murata Erie CSA2.00MG  0.5%

4.0 MHz Murata Erie CSA4.00MG  0.5%

8.0 MHz Murata Erie CSA8.00MT  0.5%

16.0 MHz Murata Erie CSA16.00MX  0.5%

All resonators used did not have built-in capacitors.

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

2: When operating below 3V VDD, or when

using certain ceramic resonators at any

voltage, it may be necessary to use high

gain HS mode, try a lower frequency

resonator, or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components, or verify oscillator

performance.

PIC18F6520/8520/6620/8620/6720/8720

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TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

An external clock source may also be connected to the

OSC1 pin in the HS, XT and LP modes, as shown in

Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR

LP OSC CONFIGURATION)

2.3 RC Oscillator

For timing insensitive applications, the “RC” and

“RCIO” device options offer additional cost savings.

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) val-

ues and the operating temperature. In addition to this,

the oscillator frequency will vary from unit to unit, due

to normal process parameter variation. Furthermore,

the difference in lead frame capacitance between pack-

age types will also affect the oscillation frequency,

especially for low CEXT values. The user also needs to

take into account variation due to tolerance of external

R and C components used. Figure 2-3 shows how the

R/C combination is connected.

In the RC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic.

FIGURE 2-3: RC OSCILLATOR MODE

The RCIO Oscillator mode functions like the RC mode,

except that the OSC2 pin becomes an additional

general purpose I/O pin. The I/O pin becomes bit 6 of

PORTA (RA6).

Ranges Tested:

Mode Freq C1 C2

LP 32 kHz 15-22 pF 15-22 pF

200 kHz

XT 1 MHz 15-22 pF 15-22 pF

4 MHz

HS 4 MHz

15-22 pF 15-22 pF8 MHz

20 MHz

Capacitor values are for design guidance only.

These capacitors were tested with the above crystal

frequencies for basic start-up and operation. These

values are not optimized.

Different capacitor values may be required to produce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

See the notes following this table for additional

information.

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

2: When operating below 3V VDD, or when

using certain ceramic resonators at any

voltage, it may be necessary to use the

HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its

own characteristics, the user should

consult the resonator/crystal manufac-

turer for appropriate values of external

components, or verify oscillator

performance.

4: RS may be required to avoid overdriving

crystals with low drive level specification.

5: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

OSC1

OSC2

Open

Clock from

Ext. System PIC18FXX20

OSC2/CLKO

CEXT

REXT

PIC18FXX20

OSC1

FOSC/4

Internal

Clock

VDD

VSS

Recommended values: 3 k  REXT  100 k

CEXT > 20 pF

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PIC18F6520/8520/6620/8620/6720/8720

2.4 External Clock Input

The EC and ECIO Oscillator modes require an external

clock source to be connected to the OSC1 pin. The

feedback device between OSC1 and OSC2 is turned

off in these modes to save current. There is a maximum

1.5 s start-up required after a Power-on Reset, or

wake-up from Sleep mode.

In the EC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 2-4 shows the pin connections for the EC

Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK INPUT

OPERATION

(EC CONFIGURATION)

The ECIO Oscillator mode functions like the EC mode,

except that the OSC2 pin becomes an additional gen-

eral purpose I/O pin. The I/O pin becomes bit 6 of

PORTA (RA6). Figure 2-5 shows the pin connections

for the ECIO Oscillator mode.

FIGURE 2-5: EXTERNAL CLOCK INPUT

OPERATION

(ECIO CONFIGURATION)

2.5 HS/PLL

A Phase Locked Loop circuit (PLL) is provided as a

programmable option for users that want to multiply the

frequency of the incoming crystal oscillator signal by 4.

For an input clock frequency of 10 MHz, the internal

clock frequency will be multiplied to 40 MHz. This is

useful for customers who are concerned with EMI due

to high-frequency crystals.

The PLL is one of the modes of the FOSC<2:0> config-

uration bits. The oscillator mode is specified during

device programming.

The PLL can only be enabled when the oscillator con-

figuration bits are programmed for HS mode. If they are

programmed for any other mode, the PLL is not

enabled and the system clock will come directly from

OSC1. Also, PLL operation cannot be changed “on-

the-fly”. To enable or disable it, the controller must

either cycle through a Power-on Reset, or switch the

clock source from the main oscillator to the Timer1

oscillator and back again. See Section 2.6 “Oscillator

Switching Feature” for details on oscillator switching.

A PLL lock timer is used to ensure that the PLL has

locked before device execution starts. The PLL lock

timer has a time-out that is called TPLL.

FIGURE 2-6: PLL BLOCK DIAGRAM

OSC1

OSC2

FOSC/4

Clock from

Ext. System PIC18FXX20

OSC1

I/O (OSC2)

RA6

Clock from

Ext. System PIC18FXX20

MUX

VCO

Loop

Filter

Divide by 4

Crystal

Osc

OSC2

OSC1

PLL Enable

FIN

FOUT

SYSCLK

Phase

Comparator

(from Configuration HS Osc

bit Register)

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2.6 Oscillator Switching Feature

The PIC18FXX20 devices include a feature that allows

the system clock source to be switched from the main

oscillator to an alternate low-frequency clock source.

For the PIC18FXX20 devices, this alternate clock

source is the Timer1 oscillator. If a low-frequency

crystal (32 kHz, for example) has been attached to the

Timer1 oscillator pins and the Timer1 oscillator has

been enabled, the device can switch to a low-power

execution mode. Figure 2-7 shows a block diagram of

the system clock sources. The clock switching feature

is enabled by programming the Oscillator Switching

Enable (OSCSEN) bit in Configuration Register 1H to a

‘0’. Clock switching is disabled in an erased device.

See Section 12.0 “Timer1 Module” for further details

of the Timer1 oscillator. See Section 23.0 “Special

Features of the CPU” for Configuration register

details.

FIGURE 2-7: DEVICE CLOCK SOURCES

PIC18FXX20

TOSC

4 x PLL

TT1P

TSCLK

Clock

Source

MUX

TOSC/4

Timer1 Oscillator

T1OSCEN

Enable

Oscillator

T1OSO

T1OSI

Clock Source Option

for other Modules

OSC1

OSC2

Sleep

Main Oscillator

When OSCSEN Conhguvation bu : o and T1 OSCEN m is set When OSCSEN and TWOSCEN are m olher slales

 2003-2013 Microchip Technology Inc. DS39609C-page 25

PIC18F6520/8520/6620/8620/6720/8720

2.6.1 SYSTEM CLOCK SWITCH BIT

The system clock source switching is performed under

software control. The system clock switch bit, SCS

(OSCCON<0>), controls the clock switching. When the

SCS bit is ‘0’, the system clock source comes from the

main oscillator that is selected by the FOSC configura-

tion bits in Configuration Register 1H. When the SCS

bit is set, the system clock source will come from the

Timer1 oscillator. The SCS bit is cleared on all forms of

Reset.

Note: The Timer1 oscillator must be enabled

and operating to switch the system clock

source. The Timer1 oscillator is enabled

by setting the T1OSCEN bit in the Timer1

Control register (T1CON). If the Timer1

oscillator is not enabled, then any write to

the SCS bit will be ignored (SCS bit forced

cleared) and the main oscillator will

continue to be the system clock source.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1

— — — — — — —SCS

bit 7 bit 0

bit 7-1 Unimplemented: Read as ‘0’

bit 0 SCS: System Clock Switch bit

When OSCSEN Configuration bit = 0 and T1OSCEN bit is set:

1 = Switch to Timer1 oscillator/clock pin

0 = Use primary oscillator/clock input pin

When OSCSEN and T1OSCEN are in other states:

Bit is forced clear.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC18F6520/8520/6620/8620/6720/8720

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2.6.2 OSCILLATOR TRANSITIONS

PIC18FXX20 devices contain circuitry to prevent

“glitches” when switching between oscillator sources.

Essentially, the circuitry waits for eight rising edges of

the clock source that the processor is switching to. This

ensures that the new clock source is stable and that its

pulse width will not be less than the shortest pulse

width of the two clock sources.

A timing diagram indicating the transition from the main

oscillator to the Timer1 oscillator is shown in Figure 2-8.

The Timer1 oscillator is assumed to be running all the

time. After the SCS bit is set, the processor is frozen at

the next occurring Q1 cycle. After eight synchronization

cycles are counted from the Timer1 oscillator, operation

resumes. No additional delays are required after the

synchronization cycles.

FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR

The sequence of events that takes place when switch-

ing from the Timer1 oscillator to the main oscillator will

depend on the mode of the main oscillator. In addition

to eight clock cycles of the main oscillator, additional

delays may take place.

If the main oscillator is configured for an external

crystal (HS, XT, LP), then the transition will take place

after an oscillator start-up time (TOST) has occurred. A

timing diagram, indicating the transition from the

Timer1 oscillator to the main oscillator for HS, XT and

LP modes, is shown in Figure 2-9.

FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)

Q3Q2Q1Q4Q3Q2

OSC1

Internal

SCS

(OSCCON<0>)

Program PC + 2PC

Note 1:Delay on internal system clock is eight oscillator cycles for synchronization.

T1OSI

Q4 Q1

PC + 4

TSCS

Clock

Counter

System

Q2 Q3 Q4 Q1

TDLY

TT1P

TOSC

21345678

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2

OSC1

Internal

SCS

(OSCCON<0>)

Program PC PC + 2

Note 1:TOST = 1024 TOSC (drawing not to scale).

T1OSI

System Clock

OSC2

TOST

PC + 6

TT1P

TOSC

TSCS

12345678

Counter

‘\\\]\\\\

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If the main oscillator is configured for HS-PLL mode, an

oscillator start-up time (TOST), plus an additional PLL

time-out (TPLL), will occur. The PLL time-out is typically

2 ms and allows the PLL to lock to the main oscillator

frequency. A timing diagram, indicating the transition

from the Timer1 oscillator to the main oscillator for

HS-PLL mode, is shown in Figure 2-10.

FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)

If the main oscillator is configured in the RC, RCIO, EC

or ECIO modes, there is no oscillator start-up time-out.

Operation will resume after eight cycles of the main

oscillator have been counted. A timing diagram,

indicating the transition from the Timer1 oscillator to the

main oscillator for RC, RCIO, EC and ECIO modes, is

shown in Figure 2-11.

FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)

Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2

OSC1

Internal System

SCS

(OSCCON<0>)

Program Counter PC PC + 2

Note 1:TOST = 1024 TOSC (drawing not to scale).

T1OSI

Clock

TOST

PC + 4

TPLL

TOSC

TT1P

TSCS

OSC2

PLL Clock

Input 12345678

Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3

OSC1

Internal System

SCS

(OSCCON<0>)

Program PC PC + 2

Note 1:RC Oscillator mode assumed.

PC + 4

T1OSI

Clock

OSC2

TT1P

TOSC

TSCS

123

45678

Counter

PIC18F6520/8520/6620/8620/6720/8720

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2.7 Effects of Sleep Mode on the

On-Chip Oscillator

When the device executes a SLEEP instruction, the on-

chip clocks and oscillator are turned off and the device

is held at the beginning of an instruction cycle (Q1

state). With the oscillator off, the OSC1 and OSC2

signals will stop oscillating. Since all the transistor

switching currents have been removed, Sleep mode

achieves the lowest current consumption of the device

(only leakage currents). Enabling any on-chip feature

that will operate during Sleep will increase the current

consumed during Sleep. The user can wake from

Sleep through external Reset, Watchdog Timer Reset

or through an interrupt.

2.8 Power-up Delays

Power up delays are controlled by two timers so that no

external Reset circuitry is required for most

applications. The delays ensure that the device is kept

in Reset until the device power supply and clock are

stable. For additional information on Reset operation,

see Section 3.0 “Reset”.

The first timer is the Power-up Timer (PWRT), which

optionally provides a fixed delay of 72 ms (nominal) on

power-up only (POR and BOR). The second timer is

the Oscillator Start-up Timer (OST), intended to keep

the chip in Reset until the crystal oscillator is stable.

With the PLL enabled (HS/PLL Oscillator mode), the

time-out sequence following a Power-on Reset is differ-

ent from other oscillator modes. The time-out sequence

is as follows: First, the PWRT time-out is invoked after

a POR time delay has expired. Then, the Oscillator

Start-up Timer (OST) is invoked. However, this is still

not a sufficient amount of time to allow the PLL to lock

at high frequencies. The PWRT timer is used to provide

an additional fixed 2 ms (nominal) time-out to allow the

PLL ample time to lock to the incoming clock frequency.

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC Mode OSC1 Pin OSC2 Pin

RC Floating, external resistor should pull high At logic low

RCIO Floating, external resistor should pull high Configured as PORTA, bit 6

ECIO Floating Configured as PORTA, bit 6

EC Floating At logic low

LP, XT and HS Feedback inverter disabled at quiescent

voltage level Feedback inverter disabled at quiescent

voltage level

Note: See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset.

 2003-2013 Microchip Technology Inc. DS39609C-page 29

PIC18F6520/8520/6620/8620/6720/8720

3.0 RESET

The PIC18FXX20 devices differentiate between

various kinds of Reset:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during Sleep

d) Watchdog Timer (WDT) Reset (during normal

operation)

e) Programmable Brown-out Reset (PBOR)

f) RESET Instruction

g) Stack Full Reset

h) Stack Underflow Reset

Most registers are unaffected by a Reset. Their status

is unknown on POR and unchanged by all other

Resets. The other registers are forced to a “Reset

state” on Power-on Reset, MCLR, WDT Reset, Brown-

out Reset, MCLR Reset during Sleep and by the

RESET instruction.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal

operation. Status bits from the RCON register, RI, TO,

PD, POR and BOR, are set or cleared differently in

different Reset situations, as indicated in Table 3-2.

These bits are used in software to determine the nature

of the Reset. See Table 3-3 for a full description of the

Reset states of all registers.

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 3-1.

The Enhanced MCU devices have a MCLR noise filter

in the MCLR Reset path. The filter will detect and

ignore small pulses. The MCLR pin is not driven low by

any internal Resets, including the WDT.

FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset

MCLR

VDD

OSC1

WDT

Module

VDD Rise

Detect

OST/PWRT

On-chip

RC OSC

(1)

WDT

Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST(2)

Enable PWRT

Sleep

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.

2: See Table 3-1 for time-out situations.

Brown-out

Reset BOREN

RESET Instruction

Stack

Pointer Stack Full/Underflow Reset

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DS39609C-page 30  2003-2013 Microchip Technology Inc.

3.1 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected. To take advantage of the POR

circuitry, tie the MCLR pin through a 1 k to 10 k

resistor to VDD. This will eliminate external RC

components usually needed to create a Power-on

Reset delay. A minimum rise rate for VDD is specified

(parameter D004). For a slow rise time, see Figure 3-2.

When the device starts normal operation (i.e., exits the

Reset condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

FIGURE 3-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

3.2 Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out

(parameter #33) only on power-up from the POR. The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in Reset as long as the PWRT is active.

The PWRT’s time delay allows VDD to rise to an accept-

able level. A configuration bit is provided to enable/

disable the PWRT.

The power-up time delay will vary from chip-to-chip due

to VDD, temperature and process variation. See DC

parameter #33 for details.

3.3 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycles (from OSC1 input) delay after the

PWRT delay is over (parameter #32). This ensures that

the crystal oscillator or resonator has started and

stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset, or wake-up from

Sleep.

3.4 PLL Lock Time-out

With the PLL enabled, the time-out sequence following

a Power-on Reset is different from other oscillator

modes. A portion of the Power-up Timer is used to

provide a fixed time-out that is sufficient for the PLL to

lock to the main oscillator frequency. This PLL lock

time-out (TPLL) is typically 2 ms and follows the

oscillator start-up time-out.

3.5 Brown-out Reset (BOR)

A configuration bit, BOREN, can disable (if clear/

programmed), or enable (if set) the Brown-out Reset

circuitry. If VDD falls below parameter D005 for greater

than parameter #35, the brown-out situation will reset

the chip. A Reset may not occur if VDD falls below

parameter D005 for less than parameter #35. The chip

will remain in Brown-out Reset until VDD rises above

BVDD. If the Power-up Timer is enabled, it will be

invoked after VDD rises above BVDD; it then will keep

the chip in Reset for an additional time delay (parame-

ter #33). If VDD drops below BVDD while the Power-up

Timer is running, the chip will go back into a Brown-out

Reset and the Power-up Timer will be initialized. Once

VDD rises above BVDD, the Power-up Timer will

execute the additional time delay.

3.6 Time-out Sequence

On power-up, the time-out sequence is as follows:

First, PWRT time-out is invoked after the POR time

delay has expired. Then, OST is activated. The total

time-out will vary based on oscillator configuration and

the status of the PWRT. For example, in RC mode with

the PWRT disabled, there will be no time-out at all.

Figures 3-3 through 3-7 depict time-out sequences on

power-up.

Since the time-outs occur from the POR pulse, the

time-outs will expire if MCLR is kept low long enough.

Bringing MCLR high will begin execution immediately

(Figure 3-5). This is useful for testing purposes, or to

synchronize more than one PIC18FXX20 device

operating in parallel.

Table 3-2 shows the Reset conditions for some Special

Function Registers, while Table 3-3 shows the Reset

conditions for all of the registers.

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 k is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

3: R1 = 1 k to 10 k will limit any current flow-

ing into MCLR from external capacitor C, in

the event of MCLR/VPP pin breakdown due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

VDD

MCLR

PIC18FXX20

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PIC18F6520/8520/6620/8620/6720/8720

TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS

TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR

RCON REGISTER

Oscillator

Configuration

Power-up(2)

Brown-out Wake-up from

Sleep or

Oscillator Switch

PWRTE = 0PWRTE = 1

HS with PLL enabled(1) 72 ms + 1024 TOSC

+ 2ms 1024 TOSC

+ 2 ms 72 ms(2) + 1024 TOSC

+ 2 ms 1024 TOSC + 2 ms

HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms(2) + 1024 TOSC 1024 TOSC

EC 72 ms 1.5 s72 ms

(2) 1.5 s(3)

External RC 72 ms — 72 ms(2) —

Note 1: 2 ms is the nominal time required for the 4xPLL to lock.

2: 72 ms is the nominal power-up timer delay, if implemented.

3: 1.5 s is the recovery time from Sleep. There is no recovery time from oscillator switch.

R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

IPEN ——RITO PD POR BOR

bit 7 bit 0

Note 1: Refer to Section 4.14 “RCON Register” for bit definitions.

Condition Program

Counter RCON

Power-on Reset 0000h 0--1 1100 1 1 1 0 0 u u

MCLR Reset during normal

operation 0000h 0--u uuuu u u u u u u u

Software Reset during normal

operation 0000h 0--0 uuuu 0 u u u u u u

Stack Full Reset during normal

operation 0000h 0--u uu11 u u u u u u 1

Stack Underflow Reset during

normal operation 0000h 0--u uu11 u u u u u 1 u

MCLR Reset during Sleep 0000h 0--u 10uu u 1 0 u u u u

WDT Reset 0000h 0--u 01uu 1 0 1 u u u u

WDT Wake-up PC + 2 u--u 00uu u 0 0 u u u u

Brown-out Reset 0000h 0--1 11u0 1 1 1 1 0 u u

Interrupt wake-up from Sleep PC + 2(1) u--u 00uu u 1 0 u u u u

Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (0x000008h or 0x000018h).

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TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

TOSU PIC18F6X20 PIC18F8X20 ---0 0000 ---0 0000 ---0 uuuu(3)

TOSH PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu(3)

TOSL PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu(3)

STKPTR PIC18F6X20 PIC18F8X20 00-0 0000 uu-0 0000 uu-u uuuu(3)

PCLATU PIC18F6X20 PIC18F8X20 ---0 0000 ---0 0000 ---u uuuu

PCLATH PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

PCL PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 PC + 2(2)

TBLPTRU PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu

TBLPTRH PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

TBLPTRL PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

TABLAT PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

PRODH PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

PRODL PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

INTCON PIC18F6X20 PIC18F8X20 0000 000x 0000 000u uuuu uuuu(1)

INTCON2 PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu(1)

INTCON3 PIC18F6X20 PIC18F8X20 1100 0000 1100 0000 uuuu uuuu(1)

INDF0 PIC18F6X20 PIC18F8X20 N/A N/A N/A

POSTINC0 PIC18F6X20 PIC18F8X20 N/A N/A N/A

POSTDEC0 PIC18F6X20 PIC18F8X20 N/A N/A N/A

PREINC0 PIC18F6X20 PIC18F8X20 N/A N/A N/A

PLUSW0 PIC18F6X20 PIC18F8X20 N/A N/A N/A

FSR0H PIC18F6X20 PIC18F8X20 ---- xxxx ---- uuuu ---- uuuu

FSR0L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

WREG PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

INDF1 PIC18F6X20 PIC18F8X20 N/A N/A N/A

POSTINC1 PIC18F6X20 PIC18F8X20 N/A N/A N/A

POSTDEC1 PIC18F6X20 PIC18F8X20 N/A N/A N/A

PREINC1 PIC18F6X20 PIC18F8X20 N/A N/A N/A

PLUSW1 PIC18F6X20 PIC18F8X20 N/A N/A N/A

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.

 2003-2013 Microchip Technology Inc. DS39609C-page 33

PIC18F6520/8520/6620/8620/6720/8720

FSR1H PIC18F6X20 PIC18F8X20 ---- xxxx ---- uuuu ---- uuuu

FSR1L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

BSR PIC18F6X20 PIC18F8X20 ---- 0000 ---- 0000 ---- uuuu

INDF2 PIC18F6X20 PIC18F8X20 N/A N/A N/A

POSTINC2 PIC18F6X20 PIC18F8X20 N/A N/A N/A

POSTDEC2 PIC18F6X20 PIC18F8X20 N/A N/A N/A

PREINC2 PIC18F6X20 PIC18F8X20 N/A N/A N/A

PLUSW2 PIC18F6X20 PIC18F8X20 N/A N/A N/A

FSR2H PIC18F6X20 PIC18F8X20 ---- xxxx ---- uuuu ---- uuuu

FSR2L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

STATUS PIC18F6X20 PIC18F8X20 ---x xxxx ---u uuuu ---u uuuu

TMR0H PIC18F6X20 PIC18F8X20 0000 0000 uuuu uuuu uuuu uuuu

TMR0L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

T0CON PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu

OSCCON PIC18F6X20 PIC18F8X20 ---- ---0 ---- ---0 ---- ---u

LVDCON PIC18F6X20 PIC18F8X20 --00 0101 --00 0101 --uu uuuu

WDTCON PIC18F6X20 PIC18F8X20 ---- ---0 ---- ---0 ---- ---u

RCON(4) PIC18F6X20 PIC18F8X20 0--q 11qq 0--q qquu u--u qquu

TMR1H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

TMR1L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

T1CON PIC18F6X20 PIC18F8X20 0-00 0000 u-uu uuuu u-uu uuuu

TMR2 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

PR2 PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 1111 1111

T2CON PIC18F6X20 PIC18F8X20 -000 0000 -000 0000 -uuu uuuu

SSPBUF PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

SSPADD PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

SSPSTAT PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

SSPCON1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

SSPCON2 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 34  2003-2013 Microchip Technology Inc.

ADRESH PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

ADRESL PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu

ADCON1 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu

ADCON2 PIC18F6X20 PIC18F8X20 0--- -000 0--- -000 u--- -uuu

CCPR1H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu

CCPR2H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

CCP2CON PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu

CCPR3H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR3L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

CCP3CON PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

CVRCON PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

CMCON PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

TMR3H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

TMR3L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

T3CON PIC18F6X20 PIC18F8X20 0000 0000 uuuu uuuu uuuu uuuu

PSPCON PIC18F6X20 PIC18F8X20 0000 ---- 0000 ---- uuuu ----

SPBRG1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

RCREG1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

TXREG1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

TXSTA1 PIC18F6X20 PIC18F8X20 0000 -010 0000 -010 uuuu -uuu

RCSTA1 PIC18F6X20 PIC18F8X20 0000 000x 0000 000x uuuu uuuu

EEADRH PIC18F6X20 PIC18F8X20 ---- --00 ---- --00 ---- --uu

EEADR PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

EEDATA PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

EECON2 PIC18F6X20 PIC18F8X20 ---- ---- ---- ---- ---- ----

EECON1 PIC18F6X20 PIC18F8X20 xx-0 x000 uu-0 u000 uu-0 u000

TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.

 2003-2013 Microchip Technology Inc. DS39609C-page 35

PIC18F6520/8520/6620/8620/6720/8720

IPR3 PIC18F6X20 PIC18F8X20 --11 1111 --11 1111 --uu uuuu

PIR3 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu

PIE3 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu

IPR2 PIC18F6X20 PIC18F8X20 -1-1 1111 -1-1 1111 -u-u uuuu

PIR2 PIC18F6X20 PIC18F8X20 -0-0 0000 -0-0 0000 -u-u uuuu(1)

PIE2 PIC18F6X20 PIC18F8X20 -0-0 0000 -0-0 0000 -u-u uuuu

IPR1 PIC18F6X20 PIC18F8X20 0111 1111 0111 1111 uuuu uuuu

PIR1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu(1)

PIE1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

MEMCON PIC18F6X20 PIC18F8X20 0-00 --00 0-00 --00 u-uu --uu

TRISJ PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu

TRISH PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu

TRISG PIC18F6X20 PIC18F8X20 ---1 1111 ---1 1111 ---u uuuu

TRISF PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu

TRISE PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu

TRISD PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu

TRISC PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu

TRISB PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu

TRISA(5,6) PIC18F6X20 PIC18F8X20 -111 1111(5) -111 1111(5) -uuu uuuu(5)

LATJ PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

LATH PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

LATG PIC18F6X20 PIC18F8X20 ---x xxxx ---u uuuu ---u uuuu

LATF PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

LATE PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

LATD PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

LATC PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

LATB PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

LATA(5,6) PIC18F6X20 PIC18F8X20 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5)

TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 36  2003-2013 Microchip Technology Inc.

PORTJ PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

PORTH PIC18F6X20 PIC18F8X20 0000 xxxx 0000 uuuu uuuu uuuu

PORTG PIC18F6X20 PIC18F8X20 ---x xxxx uuuu uuuu ---u uuuu

PORTF PIC18F6X20 PIC18F8X20 x000 0000 u000 0000 u000 0000

PORTE PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

PORTD PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

PORTC PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

PORTB PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

PORTA(5,6) PIC18F6X20 PIC18F8X20 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5)

TMR4 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

PR4 PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu

T4CON PIC18F6X20 PIC18F8X20 -000 0000 -000 0000 -uuu uuuu

CCPR4H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR4L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

CCP4CON PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

CCPR5H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR5L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu

CCP5CON PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

SPBRG2 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

RCREG2 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

TXREG2 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu

TXSTA2 PIC18F6X20 PIC18F8X20 0000 -010 0000 -010 uuuu -uuu

RCSTA2 PIC18F6X20 PIC18F8X20 0000 000x 0000 000x uuuu uuuu

TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.

 2003-2013 Microchip Technology Inc. DS39609C-page 37

PIC18F6520/8520/6620/8620/6720/8720

FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA 1 k RESISTOR)

FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

TIME-0

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 38  2003-2013 Microchip Technology Inc.

FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kRESISTOR)

FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED

(MCLR TIED TO VDD VIA 1 kRESISTOR)

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

IINTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

PLL TIME-OUT

TPLL

Note: TOST = 1024 clock cycles.

TPLL  2 ms max. First three stages of the PWRT timer.

 2003-2013 Microchip Technology Inc. DS39609C-page 39

PIC18F6520/8520/6620/8620/6720/8720

4.0 MEMORY ORGANIZATION

There are three memory blocks in PIC18FXX20

devices. They are:

• Program Memory

• Data RAM

• Data EEPROM

Data and program memory use separate busses,

which allows for concurrent access of these blocks.

Additional detailed information for Flash program

memory and data EEPROM is provided in Section 5.0

“Flash Program Memory” and Section 7.0 “Data

EEPROM Memory”, respectively.

In addition to on-chip Flash, the PIC18F8X20 devices

are also capable of accessing external program mem-

ory through an external memory bus. Depending on the

selected operating mode (discussed in Section 4.1.1

“PIC18F8X20 Program Memory Modes”), the con-

trollers may access either internal or external program

memory exclusively, or both internal and external mem-

ory in selected blocks. Additional information on the

External Memory Interface is provided in Section 6.0

“External Memory Interface”.

4.1 Program Memory Organization

A 21-bit program counter is capable of addressing the

2-Mbyte program memory space. Accessing a location

between the physically implemented memory and the

2-Mbyte address will cause a read of all ‘0’s (a NOP

instruction).

Devices in the PIC18FXX20 family can be divided into

three groups, based on program memory size. The

PIC18FX520 devices (PIC18F6520 and PIC18F8520)

have 32 Kbytes of on-chip Flash memory, equivalent to

16,384 single-word instructions. The PIC18FX620

devices (PIC18F6620 and PIC18F8620) have

64 Kbytes of on-chip Flash memory, equivalent to

32,768 single-word instructions. Finally, the

PIC18FX720 devices (PIC18F6720 and PIC18F8720)

have 128 Kbytes of on-chip Flash memory, equivalent

to 65,536 single-word instructions.

For all devices, the Reset vector address is at 0000h

and the interrupt vector addresses are at 0008h and

0018h.

The program memory maps for all of the PIC18FXX20

devices are compared in Figure 4-1.

4.1.1 PIC18F8X20 PROGRAM MEMORY

MODES

PIC18F8X20 devices differ significantly from their

PIC18 predecessors in their utilization of program

memory. In addition to available on-chip Flash program

memory, these controllers can also address up to

2 Mbytes of external program memory through the

External Memory Interface. There are four distinct

operating modes available to the controllers:

• Microprocessor (MP)

• Microprocessor with Boot Block (MPBB)

• Extended Microcontroller (EMC)

• Microcontroller (MC)

The Program Memory mode is determined by setting

the two Least Significant bits of the CONFIG3L config-

uration byte, as shown in Register 4-1. (See also

Section 23.1 “Configuration Bits” for additional

details on the device configuration bits.)

The Program Memory modes operate as follows:

•The Microprocessor Mode permits access only

to external program memory; the contents of the

on-chip Flash memory are ignored. The 21-bit

program counter permits access to a 2-Mbyte

linear program memory space.

•The Microprocessor with Boot Block Mode

accesses on-chip Flash memory from addresses

000000h to 0007FFh for PIC18F8520 devices

and from 000000h to 0001FFh for PIC18F8620

and PIC18F8720 devices. Above this, external

program memory is accessed all the way up to

the 2-Mbyte limit. Program execution automati-

cally switches between the two memories, as

required.

•The Microcontroller Mode accesses only on-

chip Flash memory. Attempts to read above the

physical limit of the on-chip Flash (7FFFh for the

PIC18F8520, 0FFFFh for the PIC18F8620,

1FFFFh for the PIC18F8720) causes a read of all

‘0’s (a NOP instruction). The Microcontroller mode

is also the only operating mode available to

PIC18F6X20 devices.

•The Extended Microcontroller Mode allows

access to both internal and external program

memories as a single block. The device can

access its entire on-chip Flash memory; above

this, the device accesses external program

memory up to the 2-Mbyte program space limit.

As with Boot Block mode, execution automatically

switches between the two memories, as required.

In all modes, the microcontroller has complete access

to data RAM and EEPROM.

Figure 4-2 compares the memory maps of the different

Program Memory modes. The differences between on-

chip and external memory access limitations are more

fully explained in Table 4-1.

f f

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 40  2003-2013 Microchip Technology Inc.

FIGURE 4-1: INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18FXX20 DEVICES

TABLE 4-1: MEMORY ACCESS FOR PIC18F8X20 PROGRAM MEMORY MODES

PC<20:0>

Stack Level 1



Stack Level 31

Reset Vector

Low Priority



CALL,RCALL,RETURN

RETFIE,RETLW

On-Chip Flash

Program Memory

High Priority

User Memory Space

1FFFFFh

010000h

00FFFFh

200000h

On-Chip Flash

Program Memory

On-Chip Flash

Program Memory

Read ‘0’ Read ‘0’Read ‘0’

008000h

007FFFh

020000h

01FFFFh

000000h

000018h

000008h

1FFFFFh

200000h

1FFFFFh

200000h

PIC18FX520 PIC18FX620 PIC18FX720

Interrupt Vector

000000h

000018h

000008h

000000h

000018h

000008h

Note: Size of memory regions not to scale.

(32 Kbyte) (64 Kbyte) (128 Kbyte)

Operating Mode

Internal Program Memory External Program Memory

Execution

From Table Read

From Table Write To Execution

From Table Read

From Table Write To

Microprocessor No Access No Access No Access Yes Yes Yes

Microprocessor

with Boot Block

Yes Yes Yes Yes Yes Yes

Microcontroller Yes Yes Yes No Access No Access No Access

Extended

Microcontroller

Yes Yes Yes Yes Yes Yes

 2003-2013 Microchip Technology Inc. DS39609C-page 41

PIC18F6520/8520/6620/8620/6720/8720

FIGURE 4-2: MEMORY MAPS FOR PIC18F8X20 PROGRAM MEMORY MODES

R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1

WAIT — — — — —PM1PM0

bit 7 bit 0

bit 7 WAIT: External Bus Data Wait Enable bit

1 = Wait selections unavailable, device will not wait

0 = Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>)

bit 6-2 Unimplemented: Read as ‘0’

bit 1-0 PM1:PM0: Processor Data Memory Mode Select bits

11 = Microcontroller mode

10 = Microprocessor mode

01 = Microcontroller with Boot Block mode

00 = Extended Microcontroller mode

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

- n = Value after erase ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Microprocessor

Mode (MP)

000000h

1FFFFFh

External

Program

Memory External

Program

Memory

1FFFFFh

000000h

On-Chip

Program

Memory

Extended

Microcontroller

Mode (EMC)

Microcontroller

Mode (MC)

000000h

External On-Chip

Program Space Execution

On-Chip

Program

Memory

1FFFFFh

Reads

Boot+1

1FFFFFh

Boot

Microprocessor

with Boot Block

Mode (MPBB)

000000h

On-Chip

Program

Memory

External

Program

Memory

Memory Flash

On-Chip

Program

Memory

(No

access)

‘0’s

External On-Chip

Memory Flash

On-Chip

Flash

External On-Chip

Memory Flash

Boundary Values for Microprocessor with Boot Block, Microcontroller and Extended Microcontroller modes(1)

Note 1: PIC18F6X20 devices are included here for completeness, to show the boundaries of their Boot Blocks and program memory spaces.

Device Boot Boot+1 Boundary Boundary+1 Available

Memory Mode(s)

PIC18F6520 0007FFh 000800h 007FFFh 008000h MC

PIC18F6620 0001FFh 000200h 00FFFFh 010000h MC

PIC18F6720 0001FFh 000200h 01FFFFh 020000h MC

PIC18F8520 0007FFh 000800h 007FFFh 008000h MP, MPBB, MC, EMC

PIC18F8620 0001FFh 000200h 00FFFFh 010000h MP, MPBB, MC, EMC

PIC18F8720 0001FFh 000200h 01FFFFh 020000h MP, MPBB, MC, EMC

Boundary

Boundary+1 Boundary

Boundary+1

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 42  2003-2013 Microchip Technology Inc.

4.2 Return Address Stack

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC

(Program Counter) is pushed onto the stack when a

CALL or RCALL instruction is executed, or an interrupt

is Acknowledged. The PC value is pulled off the stack

on a RETURN, RETLW or a RETFIE instruction. PCLATU

and PCLATH are not affected by any of the RETURN or

CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a

5-bit stack pointer, with the stack pointer initialized to

00000b after all Resets. There is no RAM associated

with stack pointer 00000b. This is only a Reset value.

During a CALL type instruction, causing a push onto the

stack, the stack pointer is first incremented and the

RAM location pointed to by the stack pointer is written

with the contents of the PC. During a RETURN type

instruction, causing a pop from the stack, the contents

of the RAM location pointed to by the STKPTR are

transferred to the PC and then the stack pointer is

decremented.

The stack space is not part of either program or data

space. The stack pointer is readable and writable and

the address on the top of the stack is readable and writ-

able through SFR registers. Data can also be pushed

to, or popped from the stack using the top-of-stack

SFRs. Status bits indicate if the stack pointer is at, or

beyond the 31 levels provided.

4.2.1 TOP-OF-STACK ACCESS

The top of the stack is readable and writable. Three

contents of the stack location pointed to by the

STKPTR register. This allows users to implement a

software stack if necessary. After a CALL, RCALL or

interrupt, the software can read the pushed value by

reading the TOSU, TOSH and TOSL registers. These

values can be placed on a user defined software stack.

At return time, the software can replace the TOSU,

TOSH and TOSL and do a return.

The user must disable the global interrupt enable bits

during this time to prevent inadvertent stack

operations.

4.2.2 RETURN STACK POINTER

(STKPTR)

The STKPTR register contains the stack pointer value,

the STKFUL (Stack Full) status bit and the STKUNF

(Stack Underflow) status bits. Register 4-2 shows the

STKPTR register. The value of the stack pointer can be

0 through 31. The stack pointer increments when val-

ues are pushed onto the stack and decrements when

values are popped off the stack. At Reset, the stack

pointer value will be ‘0’. The user may read and write

the stack pointer value. This feature can be used by a

Real-Time Operating System for return stack

maintenance.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit can only be cleared in software or

by a POR.

The action that takes place when the stack becomes

full, depends on the state of the STVREN (Stack Over-

flow Reset Enable) configuration bit. Refer to

Section 24.0 “Instruction Set Summary” for a

description of the device configuration bits. If STVREN

is set (default), the 31st push will push the (PC + 2)

value onto the stack, set the STKFUL bit and reset the

device. The STKFUL bit will remain set and the stack

pointer will be set to ‘0’.

If STVREN is cleared, the STKFUL bit will be set on the

31st push and the stack pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and STKPTR will remain at 31.

When the stack has been popped enough times to

unload the stack, the next pop will return a value of zero

to the PC and sets the STKUNF bit, while the stack

pointer remains at ‘0’. The STKUNF bit will remain set

until cleared in software or a POR occurs.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the Reset vector, where the

stack conditions can be verified and

appropriate actions can be taken.

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PIC18F6520/8520/6620/8620/6720/8720

FIGURE 4-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

4.2.3 PUSH AND POP INSTRUCTIONS

Since the Top-of-Stack (TOS) is readable and writable,

the ability to push values onto the stack and pull values

off the stack, without disturbing normal program

execution, is a desirable option. To push the current PC

value onto the stack, a PUSH instruction can be

executed. This will increment the stack pointer and load

the current PC value onto the stack. TOSU, TOSH and

TOSL can then be modified to place a return address

on the stack.

The ability to pull the TOS value off of the stack and

replace it with the value that was previously pushed

onto the stack, without disturbing normal execution, is

achieved by using the POP instruction. The POP

instruction discards the current TOS by decrementing

the stack pointer. The previous value pushed onto the

stack then becomes the TOS value.

4.2.4 STACK FULL/UNDERFLOW RESETS

These Resets are enabled by programming the

STVREN configuration bit. When the STVREN bit is

disabled, a full or underflow condition will set the

appropriate STKFUL or STKUNF bit, but not cause a

device Reset. When the STVREN bit is enabled, a full

or underflow condition will set the appropriate STKFUL

or STKUNF bit and then cause a device Reset. The

STKFUL or STKUNF bits are only cleared by the user

software or a POR Reset.

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0

bit 7 bit 0

bit 7 STKFUL: Stack Full Flag bit

1 = Stack became full or overflowed

0 = Stack has not become full or overflowed

bit 6 STKUNF: Stack Underflow Flag bit

1 = Stack underflow occurred

0 = Stack underflow did not occur

bit 5 Unimplemented: Read as ‘0’

bit 4-0 SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

00011

0x001A34

11111

11110

11101

00010

00001

00000

00010

Return Address Stack

Top-of-Stack 0x000D58

TOSLTOSHTOSU 0x340x1A0x00

STKPTR<4:0>

PIC18F6520/8520/6620/8620/6720/8720

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4.3 Fast Register Stack

A “fast interrupt return” option is available for interrupts.

A Fast Register Stack is provided for the Status, WREG

and BSR registers and is only one in depth. The stack

is not readable or writable and is loaded with the

current value of the corresponding register when the

processor vectors for an interrupt. The values in the

registers are then loaded back into the working regis-

ters, if the FAST RETURN instruction is used to return

from the interrupt.

A low or high priority interrupt source will push values

into the stack registers. If both low and high priority

interrupts are enabled, the stack registers cannot be

used reliably for low priority interrupts. If a high priority

interrupt occurs while servicing a low priority interrupt,

the stack register values stored by the low priority

interrupt will be overwritten.

If high priority interrupts are not disabled during low

priority interrupts, users must save the key registers in

software during a low priority interrupt.

If no interrupts are used, the fast register stack can be

used to restore the Status, WREG and BSR registers at

the end of a subroutine call. To use the fast register

stack for a subroutine call, a FAST CALL instruction

must be executed.

Example 4-1 shows a source code example that uses

the fast register stack.

EXAMPLE 4-1: FAST REGISTER STACK

CODE EXAMPLE

4.4 PCL, PCLATH and PCLATU

The program counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21 bits

wide. The low byte is called the PCL register; this reg-

ister is readable and writable. The high byte is called

the PCH register. This register contains the PC<15:8>

bits and is not directly readable or writable; updates to

the PCH register may be performed through the

PCLATH register. The upper byte is called PCU. This

readable or writable; updates to the PCU register may

be performed through the PCLATU register.

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the LSB of the PCL is fixed to a value of

‘0’. The PC increments by 2 to address sequential

instructions in the program memory.

The CALL, RCALL, GOTO and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

The contents of PCLATH and PCLATU will be trans-

ferred to the program counter by an operation that

writes PCL. Similarly, the upper two bytes of the

program counter will be transferred to PCLATH and

PCLATU by an operation that reads PCL. This is useful

for computed offsets to the PC (see Section 4.8.1

“Computed GOTO”).

4.5 Clocking Scheme/Instruction

Cycle

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the

program counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

are shown in Figure 4-4.

FIGURE 4-4: CLOCK/INSTRUCTION CYCLE

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK



SUB1 



RETURN FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKO

(RC mode)

PC PC+2 PC+4

Fetch INST (PC)

Execute INST (PC-2)

Fetch INST (PC+2)

Execute INST (PC)

Fetch INST (PC+4)

Execute INST (PC+2)

Internal

Phase

Clock

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PIC18F6520/8520/6620/8620/6720/8720

4.6 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined, such that fetch takes one instruction cycle,

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

then two cycles are required to complete the instruction

(Example 4-2).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW

4.7 Instructions in Program Memory

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even address (LSB = 0). Figure 4-5 shows an

example of how instruction words are stored in the pro-

gram memory. To maintain alignment with instruction

boundaries, the PC increments in steps of 2 and the

LSB will always read ‘0’ (see Section 4.4 “PCL,

PCLATH and PCLATU”).

The CALL and GOTO instructions have an absolute

program memory address embedded into the

instruction. Since instructions are always stored on

word boundaries, the data contained in the instruction

is a word address. The word address is written to

PC<20:1>, which accesses the desired byte address in

program memory. Instruction #2 in Figure 4-5 shows

how the instruction “GOTO 000006h” is encoded in the

program memory. Program branch instructions, which

encode a relative address offset, operate in the same

manner. The offset value stored in a branch instruction

represents the number of single-word instructions that

the PC will be offset by. Section 24.0 “Instruction Set

Summary” provides further details of the instruction

set.

FIGURE 4-5: INSTRUCTIONS IN PROGRAM MEMORY

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed”

from the pipeline, while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. BRA SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

Word Address

LSB = 1LSB = 0

Program Memory

Byte Locations  000000h

000002h

000004h

000006h

Instruction 1: MOVLW 055h 0Fh 55h 000008h

Instruction 2: GOTO 000006h EFh 03h 00000Ah

F0h 00h 00000Ch

Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh

F4h 56h 000010h

000012h

000014h

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 46  2003-2013 Microchip Technology Inc.

4.7.1 TWO-WORD INSTRUCTIONS

The PIC18FXX20 devices have four two-word instruc-

tions: MOVFF, CALL, GOTO and LFSR. The second word

of these instructions has the 4 MSBs set to ‘1’s and is

a special kind of NOP instruction. The lower 12 bits of

the second word contain data to be used by the instruc-

tion. If the first word of the instruction is executed, the

data in the second word is accessed. If the second

word of the instruction is executed by itself (first word

was skipped), it will execute as a NOP. This action is

necessary when the two-word instruction is preceded

by a conditional instruction that changes the PC. A pro-

gram example that demonstrates this concept is shown

in Example 4-3. Refer to Section 24.0 “Instruction

Set Summary” for further details of the instruction set.

EXAMPLE 4-3: TWO-WORD INSTRUCTIONS

4.8 Look-up Tables

Look-up tables are implemented two ways. These are:

• Computed GOTO

• Table Reads

4.8.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL).

A look-up table can be formed with an ADDWF PCL

instruction and a group of RETLW 0xnn instructions.

WREG is loaded with an offset into the table before

executing a call to that table. The first instruction of the

called routine is the ADDWF PCL instruction. The next

instruction executed will be one of the RETLW 0xnn

instructions, that returns the value 0xnn to the calling

function.

The offset value (value in WREG) specifies the number

of bytes that the program counter should advance.

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

4.8.2 TABLE READS/TABLE WRITES

A better method of storing data in program memory

allows 2 bytes of data to be stored in each instruction

location.

Look-up table data may be stored 2 bytes per program

word by using table reads and writes. The Table Pointer

(TBLPTR) specifies the byte address and the Table

Latch (TABLAT) contains the data that is read from, or

written to program memory. Data is transferred to/from

program memory, one byte at a time.

A description of the table read/table write operation is

shown in Section 5.0 “Flash Program Memory”.

CASE 1:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction

1111 0100 0101 0110 ; 2nd operand holds address of REG2

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes

1111 0100 0101 0110 ; 2nd operand becomes NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code

 2003-2013 Microchip Technology Inc. DS39609C-page 47

PIC18F6520/8520/6620/8620/6720/8720

4.9 Data Memory Organization

The data memory is implemented as static RAM. Each

allowing up to 4096 bytes of data memory. The data

memory map is in turn divided into 16 banks of

256 bytes each. The lower 4 bits of the Bank Select

accessed. The upper 4 bits of the BSR are not

implemented.

The data memory space contains both Special Func-

tion Registers (SFR) and General Purpose Registers

(GPR). The SFRs are used for control and status of the

controller and peripheral functions, while GPRs are

used for data storage and scratch pad operations in the

user’s application. The SFRs start at the last location of

Bank 15 (0FFFh) and extend downwards. Any remain-

ing space beyond the SFRs in the Bank may be imple-

mented as GPRs. GPRs start at the first location of

Bank 0 and grow upwards. Any read of an

unimplemented location will read as ‘0’s.

PIC18FX520 devices have 2048 bytes of data RAM,

extending from Bank 0 to Bank 7 (000h through 7FFh).

PIC18FX620 and PIC18FX720 devices have

3840 bytes of data RAM, extending from Bank 0 to

Bank 14 (000h through EFFh). The organization of the

data memory space for these devices is shown in

Figure 4-6 and Figure 4-7.

The entire data memory may be accessed directly or

indirectly. Direct addressing may require the use of the

BSR register. Indirect addressing requires the use of a

File Select Register (FSRn) and a corresponding Indi-

rect File Operand (INDFn). Each FSR holds a 12-bit

address value that can be used to access any location

in the data memory map without banking.

The instruction set and architecture allow operations

across all banks. This may be accomplished by indirect

addressing, or by the use of the MOVFF instruction. The

MOVFF instruction is a two-word/two-cycle instruction

that moves a value from one register to another.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle,

regardless of the current BSR values, an Access Bank

is implemented. A segment of Bank 0 and a segment of

Bank 15 comprise the Access RAM. Section 4.10

“Access Bank” provides a detailed description of the

Access RAM.

4.9.1 GENERAL PURPOSE

The register file can be accessed either directly or indi-

rectly. Indirect addressing operates using a File Select

operation of indirect addressing is shown in

Section 4.12 “Indirect Addressing, INDF and FSR

Registers”.

Enhanced MCU devices may have banked memory in

the GPR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other Resets.

Data RAM is available for use as General Purpose

Registers by all instructions. The top section of Bank 15

(F60h to FFFh) contains SFRs. All other banks of data

memory contain GPR registers, starting with Bank 0.

4.9.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

given in Table 4-2 and Table 4-3.

The SFRs can be classified into two sets: those asso-

ciated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described in this section, while those related

to the operation of the peripheral features are

described in the section of that peripheral feature. The

SFRs are typically distributed among the peripherals

whose functions they control.

The unused SFR locations are unimplemented and

read as ‘0’s. The addresses for the SFRs are listed in

Table 4-2.

)J rr

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 48  2003-2013 Microchip Technology Inc.

FIGURE 4-6: DATA MEMORY MAP FOR PIC18FX520 DEVICES

Bank 0

Bank 1

Bank 6

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1110

= 1111

060h

05Fh

F60h

FFFh

00h

5Fh

60h

FFh

Access Bank

When a = 0,

the BSR is ignored and the

Access Bank is used.

The first 96 bytes are General

Purpose RAM (from Bank 0).

The second 160 bytes are

Special Function Registers

(from Bank 15).

When a = 1,

the BSR is used to specify the

RAM location that the instruction

uses.

Bank 7

Bank 2

F5Fh

F00h

EFFh

7FFh

300h

2FFh

200h

1FFh

100h

0FFh

000h

= 0011

= 0010

Access RAM

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPRs

SFRs

Unused

Access RAM High

Access RAM Low

Bank 3

6FFh

800h

700h

= 0110

(SFRs)

GPRs

Unused,

GPRs

FFh

00h

Bank 14

Bank 8

to Read as ‘0’

= 0111

= 1000



)J a ))

 2003-2013 Microchip Technology Inc. DS39609C-page 49

PIC18F6520/8520/6620/8620/6720/8720

FIGURE 4-7: DATA MEMORY MAP FOR PIC18FX620 AND PIC18FX720 DEVICES

Bank 0

Bank 1

Bank 13

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1110

= 1111

060h

05Fh

F60h

FFFh

00h

5Fh

60h

FFh

Access Bank

When a = 0,

the BSR is ignored and the

Access Bank is used.

The first 96 bytes are General

Purpose RAM (from Bank 0).

The second 160 bytes are

Special Function Registers

(from Bank 15).

When a = 1,

the BSR is used to specify the

RAM location that the instruction

uses.

Bank 4

Bank 3

Bank 2

F5Fh

F00h

EFFh

3FFh

300h

2FFh

200h

1FFh

100h

0FFh

000h

= 0011

= 0010

Access RAM

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPRs

SFRs

Unused

Access RAM High

Access RAM Low

Bank 14

GPRs

Bank 5

4FFh

400h

DFFh

500h

E00h

= 0100

(SFRs)

GPRs

= 0101

= 1101



PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 50  2003-2013 Microchip Technology Inc.

TABLE 4-2: SPECIAL FUNCTION REGISTER MAP

Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2(3) FBFh CCPR1H F9Fh IPR1

FFEh TOSH FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1

FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1

FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H F9Ch MEMCON(2)

FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh —(1)

FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ

FF9h PCL FD9h FSR2L FB9h CCPR3H F99h TRISH

FF8h TBLPTRU FD8h STATUS FB8h CCPR3L F98h TRISG

FF7h TBLPTRH FD7h TMR0H FB7h CCP3CON F97h TRISF

FF6h TBLPTRL FD6h TMR0L FB6h —(1) F96h TRISE

FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD

FF4h PRODH FD4h —(1) FB4h CMCON F94h TRISC

FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB

FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA

FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ

FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH

FEFh INDF0(3) FCFh TMR1H FAFh SPBRG1 F8Fh LATG

FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG1 F8Eh LATF

FEDh POSTDEC0(3) FCDh T1CON FADh TXREG1 F8Dh LATE

FECh PREINC0(3) FCCh TMR2 FACh TXSTA1 F8Ch LATD

FEBh PLUSW0(3) FCBh PR2 FABh RCSTA1 F8Bh LATC

FEAh FSR0H FCAh T2CON FAAh EEADRH F8Ah LATB

FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA

FE8h WREG FC8h SSPADD FA8h EEDATA F88h PORTJ

FE7h INDF1(3) FC7h SSPSTAT FA7h EECON2 F87h PORTH

FE6h POSTINC1(3) FC6h SSPCON1 FA6h EECON1 F86h PORTG

FE5h POSTDEC1(3) FC5h SSPCON2 FA5h IPR3 F85h PORTF

FE4h PREINC1(3) FC4h ADRESH FA4h PIR3 F84h PORTE

FE3h PLUSW1(3) FC3h ADRESL FA3h PIE3 F83h PORTD

FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC

FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB

FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA

Note 1: Unimplemented registers are read as ‘0’.

2: This register is unused on PIC18F6X20 devices. Always maintain this register clear.

3: This is not a physical register.

 2003-2013 Microchip Technology Inc. DS39609C-page 51

PIC18F6520/8520/6620/8620/6720/8720

Address Name Address Name Address Name Address Name

F7Fh —(1) F5Fh —(1) F3Fh —(1) F1Fh —(1)

F7Eh —(1) F5Eh —(1) F3Eh —(1) F1Eh —(1)

F7Dh —(1) F5Dh —(1) F3Dh —(1) F1Dh —(1)

F7Ch —(1) F5Ch —(1) F3Ch —(1) F1Ch —(1)

F7Bh —(1) F5Bh —(1) F3Bh —(1) F1Bh —(1)

F7Ah —(1) F5Ah —(1) F3Ah —(1) F1Ah —(1)

F79h —(1) F59h —(1) F39h —(1) F19h —(1)

F78h TMR4 F58h —(1) F38h —(1) F18h —(1)

F77h PR4 F57h —(1) F37h —(1) F17h —(1)

F76h T4CON F56h —(1) F36h —(1) F16h —(1)

F75h CCPR4H F55h —(1) F35h —(1) F15h —(1)

F74h CCPR4L F54h —(1) F34h —(1) F14h —(1)

F73h CCP4CON F53h —(1) F33h —(1) F13h —(1)

F72h CCPR5H F52h —(1) F32h —(1) F12h —(1)

F71h CCPR5L F51h —(1) F31h —(1) F11h —(1)

F70h CCP5CON F50h —(1) F30h —(1) F10h —(1)

F6Fh SPBRG2 F4Fh —(1) F2Fh —(1) F0Fh —(1)

F6Eh RCREG2 F4Eh —(1) F2Eh —(1) F0Eh —(1)

F6Dh TXREG2 F4Dh —(1) F2Dh —(1) F0Dh —(1)

F6Ch TXSTA2 F4Ch —(1) F2Ch —(1) F0Ch —(1)

F6Bh RCSTA2 F4Bh —(1) F2Bh —(1) F0Bh —(1)

F6Ah —(1) F4Ah —(1) F2Ah —(1) F0Ah —(1)

F69h —(1) F49h —(1) F29h —(1) F09h —(1)

F68h —(1) F48h —(1) F28h —(1) F08h —(1)

F67h —(1) F47h —(1) F27h —(1) F07h —(1)

F66h —(1) F46h —(1) F26h —(1) F06h —(1)

F65h —(1) F45h —(1) F25h —(1) F05h —(1)

F64h —(1) F44h —(1) F24h —(1) F04h —(1)

F63h —(1) F43h —(1) F23h —(1) F03h —(1)

F62h —(1) F42h —(1) F22h —(1) F02h —(1)

F61h —(1) F41h —(1) F21h —(1) F01h —(1)

F60h —(1) F40h —(1) F20h —(1) F00h —(1)

Note 1: Unimplemented registers are read as ‘0’.

2: This register is not available on PIC18F6X20 devices.

3: This is not a physical register.

TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED)

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 52  2003-2013 Microchip Technology Inc.

TABLE 4-3: REGISTER FILE SUMMARY

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Details

on page:

TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 32, 42

TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 32, 42

TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 32, 42

STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 32, 43

PCLATU —— bit 21 Holding Register for PC<20:16> --10 0000 32, 44

PCLATH Holding Register for PC<15:8> 0000 0000 32, 44

PCL PC Low Byte (PC<7:0>) 0000 0000 32, 44

TBLPTRU ——bit 21

(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 32, 64

TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 32, 64

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 32, 64

TABLAT Program Memory Table Latch 0000 0000 32, 64

PRODH Product Register High Byte xxxx xxxx 32, 85

PRODL Product Register Low Byte xxxx xxxx 32, 85

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 32, 89

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 32, 90

INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 32, 91

INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) n/a 57

POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented

(not a physical register)

n/a 57

POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented

(not a physical register)

n/a 57

PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) n/a 57

PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented

(not a physical register) – value of FSR0 offset by value in WREG

n/a 57

FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 32, 57

FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 32, 57

WREG Working Register xxxx xxxx 32

INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) n/a 57

POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented

(not a physical register)

n/a 57

POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented

(not a physical register)

n/a 57

PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented

(not a physical register)

n/a 57

PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented

(not a physical register) – value of FSR1 offset by value in WREG

n/a 57

FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 33, 57

FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 33, 57

BSR — — — — Bank Select Register ---- 0000 33, 56

INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) n/a 57

POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented

(not a physical register)

n/a 57

POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented

(not a physical register)

n/a 57

Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator

modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

3: These registers are unused on PIC18F6X20 devices; always maintain these clear.

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PIC18F6520/8520/6620/8620/6720/8720

PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented

(not a physical register)

n/a 57

PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented

(not a physical register) – value of FSR2 offset by value in WREG

n/a 57

FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 33, 57

FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 33, 57

STATUS — — —NOVZDCC---x xxxx 33, 59

TMR0H Timer0 Register High Byte 0000 0000 33, 133

TMR0L Timer0 Register Low Byte xxxx xxxx 33, 133

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 33, 131

OSCCON — — — — — — —SCS---- ---0 25, 33

LVDCON —— IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 33, 235

WDTCON — — — — — — —SWDTE---- ---0 33, 250

RCON IPEN ——RITO PD POR BOR 0--1 11qq 33, 60,

101

TMR1H Timer1 Register High Byte xxxx xxxx 33, 135

TMR1L Timer1 Register Low Byte xxxx xxxx 33, 135

T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 33, 135

TMR2 Timer2 Register 0000 0000 33, 141

PR2 Timer2 Period Register 1111 1111 33, 142

T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 33, 141

SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 33, 157

SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 33, 166

SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 33, 158

SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 33, 168

SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 33, 169

ADRESH A/D Result Register High Byte xxxx xxxx 34, 215

ADRESL A/D Result Register Low Byte xxxx xxxx 34, 215

ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 34, 213

ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 34, 214

ADCON2 ADFM — — — — ADCS2 ADCS1 ADCS0 0--- -000 34, 215

CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 34, 151,

152

CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 34, 151,

152

CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 34, 149

CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 34, 151,

152

CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 34, 151,

152

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 34, 149

TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Details

on page:

Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator

modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

3: These registers are unused on PIC18F6X20 devices; always maintain these clear.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 54  2003-2013 Microchip Technology Inc.

CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx 34, 151,

152

CCPR3L Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 34, 151,

152

CCP3CON —— DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 34, 149

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 34, 229

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 34, 223

TMR3H Timer3 Register High Byte xxxx xxxx 34, 143

TMR3L Timer3 Register Low Byte xxxx xxxx 34, 143

T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 34, 143

PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 34, 129

SPBRG1 USART1 Baud Rate Generator 0000 0000 34, 205

RCREG1 USART1 Receive Register 0000 0000 34, 206

TXREG1 USART1 Transmit Register 0000 0000 34, 204

TXSTA1 CSRC TX9 TXEN SYNC —BRGHTRMTTX9D0000 -010 34, 198

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 34, 199

EEADRH — — — — — — EE Adr Register High ---- --00 34, 79

EEADR Data EEPROM Address Register 0000 0000 34, 79

EEDATA Data EEPROM Data Register 0000 0000 34, 79

EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 34, 79

EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 34, 80

IPR3 —— RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 35, 100

PIR3 —— RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 35, 94

PIE3 —— RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 35, 97

IPR2 —CMIP— EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 35, 99

PIR2 —CMIF— EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 35, 93

PIE2 —CMIE— EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 35, 96

IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 35, 98

PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 35, 92

PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 35, 95

MEMCON(3) EBDIS —WAIT1WAIT0——WM1WM00-00 --00 35, 71

TRISJ(3) Data Direction Control Register for PORTJ 1111 1111 35, 125

TRISH(3) Data Direction Control Register for PORTH 1111 1111 35, 122

TRISG — — — Data Direction Control Register for PORTG ---1 1111 35, 120

TRISF Data Direction Control Register for PORTF 1111 1111 35, 117

TRISE Data Direction Control Register for PORTE 1111 1111 35, 114

TRISD Data Direction Control Register for PORTD 1111 1111 35, 111

TRISC Data Direction Control Register for PORTC 1111 1111 35, 109

TRISB Data Direction Control Register for PORTB 1111 1111 35, 106

TRISA — TRISA6(1) Data Direction Control Register for PORTA -111 1111 35, 103

TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Details

on page:

Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator

modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

3: These registers are unused on PIC18F6X20 devices; always maintain these clear.

 2003-2013 Microchip Technology Inc. DS39609C-page 55

PIC18F6520/8520/6620/8620/6720/8720

LATJ(3) Read PORTJ Data Latch, Write PORTJ Data Latch xxxx xxxx 35, 125

LATH(3) Read PORTH Data Latch, Write PORTH Data Latch xxxx xxxx 35, 122

LATG — — — Read PORTG Data Latch, Write PORTG Data Latch ---x xxxx 35, 120

LATF Read PORTF Data Latch, Write PORTF Data Latch xxxx xxxx 35, 117

LATE Read PORTE Data Latch, Write PORTE Data Latch xxxx xxxx 35, 114

LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 35, 111

LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 35, 109

LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 35, 106

LATA —LATA6

(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 35, 103

PORTJ(3) Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 36, 125

PORTH(3) Read PORTH pins, Write PORTH Data Latch xxxx xxxx 36, 122

PORTG — — — Read PORTG pins, Write PORTG Data Latch ---x xxxx 36, 120

PORTF Read PORTF pins, Write PORTF Data Latch xxxx xxxx 36, 117

PORTE Read PORTE pins, Write PORTE Data Latch xxxx xxxx 36, 114

PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 36, 111

PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 36, 109

PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 36, 106

PORTA —RA6

(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 36, 103

TMR4 Timer4 Register 0000 0000 36, 148

PR4 Timer4 Period Register 1111 1111 36, 148

T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 36, 147

CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 36, 151,

152

CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 36, 151,

152

CCP4CON —— DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 0000 0000 36, 149

CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 36, 151,

152

CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 36, 151,

152

CCP5CON —— DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 0000 0000 36, 149

SPBRG2 USART2 Baud Rate Generator 0000 0000 36, 205

RCREG2 USART2 Receive Register 0000 0000 36, 206

TXREG2 USART2 Transmit Register 0000 0000 36, 204

TXSTA2 CSRC TX9 TXEN SYNC —BRGHTRMTTX9D0000 -010 36, 198

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 36, 199

TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Details

on page:

Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator

modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

3: These registers are unused on PIC18F6X20 devices; always maintain these clear.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 56  2003-2013 Microchip Technology Inc.

4.10 Access Bank

The Access Bank is an architectural enhancement,

which is very useful for C compiler code optimization.

The techniques used by the C compiler may also be

useful for programs written in assembly.

This data memory region can be used for:

• Intermediate computational values

• Local variables of subroutines

• Faster context saving/switching of variables

• Common variables

• Faster evaluation/control of SFRs (no banking)

The Access Bank is comprised of the upper 160 bytes

in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.

These two sections will be referred to as Access RAM

High and Access RAM Low, respectively. Figure 4-7

indicates the Access RAM areas.

A bit in the instruction word specifies if the operation is

to occur in the bank specified by the BSR register or in

the Access Bank. This bit is denoted by the ‘a’ bit (for

access bit).

When forced in the Access Bank (a = 0), the last

address in Access RAM Low is followed by the first

address in Access RAM High. Access RAM High maps

the Special Function Registers, so that these registers

can be accessed without any software overhead. This is

useful for testing status flags and modifying control bits.

4.11 Bank Select Register (BSR)

The need for a large general purpose memory space

dictates a RAM banking scheme. The data memory is

partitioned into sixteen banks. When using direct

addressing, the BSR should be configured for the

desired bank.

BSR<3:0> holds the upper 4 bits of the 12-bit RAM

address. The BSR<7:4> bits will always read ‘0’s and

writes will have no effect.

A MOVLB instruction has been provided in the

instruction set to assist in selecting banks.

If the currently selected bank is not implemented, any

read will return all ‘0’s and all writes are ignored. The

Status register bits will be set/cleared as appropriate for

the instruction performed.

Each Bank extends up to FFh (256 bytes). All data

memory is implemented as static RAM.

A MOVFF instruction ignores the BSR, since the 12-bit

addresses are embedded into the instruction word.

Section 4.12 “Indirect Addressing, INDF and FSR

Registers” provides a description of indirect address-

ing, which allows linear addressing of the entire RAM

space.

FIGURE 4-8: DIRECT ADDRESSING

Note 1: For register file map detail, see Table 4-2.

2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the

registers of the Access Bank.

3: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Data

Memory(1)

Direct Addressing

Bank Select(2) Location Select(3)

BSR<3:0> 7 0

From Opcode(3)

00h 01h 0Eh 0Fh

Bank 0 Bank 1 Bank 14 Bank 15

1FFh

100h

0FFh

000h

EFFh

E00h

FFFh

F00h

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4.12 Indirect Addressing, INDF and

FSR Registers

Indirect addressing is a mode of addressing data mem-

ory, where the data memory address in the instruction

is not fixed. An FSR register is used as a pointer to the

data memory location that is to be read or written. Since

this pointer is in RAM, the contents can be modified by

the program. This can be useful for data tables in the

data memory and for software stacks. Figure 4-9

shows the operation of indirect addressing. This shows

the moving of the value to the data memory address,

specified by the value of the FSR register.

Indirect addressing is possible by using one of the

INDF registers. Any instruction using the INDF register

actually accesses the register pointed to by the File

Select Register, FSR. Reading the INDF register itself,

indirectly (FSR = 0), will read 00h. Writing to the INDF

Figure 4-10.

The INDFn register is not a physical register. Address-

ing INDFn actually addresses the register whose

address is contained in the FSRn register (FSRn is a

pointer). This is indirect addressing.

Example 4-4 shows a simple use of indirect addressing

to clear the RAM in Bank 1 (locations 100h-1FFh) in a

minimum number of instructions.

EXAMPLE 4-4: HOW TO CLEAR RAM

(BANK 1) USING

INDIRECT ADDRESSING

There are three indirect addressing registers. To

address the entire data memory space (4096 bytes),

these registers are 12 bits wide. To store the 12 bits of

addressing information, two 8-bit registers are

required. These indirect addressing registers are:

1. FSR0: composed of FSR0H:FSR0L

2. FSR1: composed of FSR1H:FSR1L

3. FSR2: composed of FSR2H:FSR2L

In addition, there are registers INDF0, INDF1 and

INDF2, which are not physically implemented. Reading

or writing to these registers activates indirect address-

ing, with the value in the corresponding FSR register

being the address of the data. If an instruction writes a

value to INDF0, the value will be written to the address

pointed to by FSR0H:FSR0L. A read from INDF1 reads

the data from the address pointed to by

FSR1H:FSR1L. INDFn can be used in code anywhere

an operand can be used.

If INDF0, INDF1 or INDF2 are read indirectly via an

FSR, all ‘0’s are read (zero bit is set). Similarly, if

INDF0, INDF1 or INDF2 are written to indirectly, the

operation will be equivalent to a NOP instruction and the

Status bits are not affected.

4.12.1 INDIRECT ADDRESSING

OPERATION

Each FSR register has an INDF register associated

with it, plus four additional register addresses. Perform-

ing an operation on one of these five registers

determines how the FSR will be modified during

indirect addressing.

When data access is done to one of the five INDFn

locations, the address selected will configure the FSRn

• Do nothing to FSRn after an indirect access

(no change) – INDFn.

• Auto-decrement FSRn after an indirect access

(post-decrement) – POSTDECn.

• Auto-increment FSRn after an indirect access

(post-increment) – POSTINCn.

• Auto-increment FSRn before an indirect access

(pre-increment) – PREINCn.

• Use the value in the WREG register as an offset

to FSRn. Do not modify the value of the WREG or

the FSRn register after an indirect access

(no change) – PLUSWn.

When using the auto-increment or auto-decrement

features, the effect on the FSR is not reflected in the

Status register. For example, if the indirect address

causes the FSR to equal ‘0’, the Z bit will not be set.

Incrementing or decrementing an FSR affects all 12

bits. That is, when FSRnL overflows from an increment,

FSRnH will be incremented automatically.

Adding these features allows the FSRn to be used as a

stack pointer, in addition to its uses for table operations

in data memory.

Each FSR has an address associated with it that

performs an indexed indirect access. When a data

access to this INDFn location (PLUSWn) occurs, the

FSRn is configured to add the signed value in the

WREG register and the value in FSR to form the

address before an indirect access. The FSR value is

not changed.

If an FSR register contains a value that points to one of

the INDFn, an indirect read will read 00h (zero bit is

set), while an indirect write will be equivalent to a NOP

(Status bits are not affected).

If an indirect addressing operation is done where the tar-

get address is an FSRnH or FSRnL register, the write

operation will dominate over the pre- or post-increment/

decrement functions.

LFSR FSR0 ,0x100 ;

NEXT CLRF POSTINC0 ; Clear INDF

; register and

; inc pointer

BTFSS FSR0H, 1 ; All done with

; Bank 1?

GOTO NEXT ; NO, clear next

CONTINUE ; YES, continue

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FIGURE 4-9: INDIRECT ADDRESSING OPERATION

FIGURE 4-10: INDIRECT ADDRESSING

Opcode Address

File Address = Access of an Indirect Addressing Register

FSR

Instruction

Executed

Instruction

Fetched

RAM

Opcode File

BSR<3:0>

FFFh

Note 1: For register file map detail, see Table 4-2.

Data

Memory(1)

Indirect Addressing

FSR Register11 0

0FFFh

0000h

Location Select

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4.13 Status Register

The Status register, shown in Register 4-3, contains the

arithmetic status of the ALU. The Status register can be

the destination for any instruction, as with any other reg-

ister. If the Status register is the destination for an

instruction that affects the Z, DC, C, OV or N bits, then

the write to these five bits is disabled. These bits are set

or cleared according to the device logic. Therefore, the

result of an instruction with the Status register as

destination may be different than intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the Status register as

000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF, MOVFF and MOVWF instructions are used to alter

the Status register, because these instructions do not

affect the Z, C, DC, OV or N bits from the Status regis-

ter. For other instructions not affecting any status bits,

see Table 24-1.

Note: The C and DC bits operate as a borrow

and digit borrow bit respectively, in

subtraction.

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —NOVZDCC

bit 7 bit 0

bit 7-5 Unimplemented: Read as ‘0’

bit 4 N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was

negative (ALU MSB = 1).

1 = Result was negative

0 = Result was positive

bit 3 OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the

7-bit magnitude, which causes the sign bit (bit 7) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)

0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the

2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit

is loaded with either bit 4 or bit 3 of the source register.

bit 0 C: Carry/borrow bit

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the

2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit

is loaded with either the high or low-order bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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4.14 RCON Register

The Reset Control (RCON) register contains flag bits

that allow differentiation between the sources of a

device Reset. These flags include the TO, PD, POR,

BOR and RI bits. This register is readable and writable.

Note 1: If the BOREN configuration bit is set

(Brown-out Reset enabled), the BOR bit

is ‘1’ on a Power-on Reset. After a Brown-

out Reset has occurred, the BOR bit will

be cleared and must be set by firmware to

indicate the occurrence of the next

Brown-out Reset.

2: It is recommended that the POR bit be set

after a Power-on Reset has been

detected, so that subsequent Power-on

Resets may be detected.

R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0

IPEN ——RITO PD POR BOR

bit 7 bit 0

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6-5 Unimplemented: Read as ‘0’

bit 4 RI: RESET Instruction Flag bit

1 = The RESET instruction was not executed

0 = The RESET instruction was executed causing a device Reset

(must be set in software after a Brown-out Reset occurs)

bit 3 TO: Watchdog Time-out Flag bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 2 PD: Power-down Detection Flag bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 1 POR: Power-on Reset Status bit

1 = A Power-on Reset has not occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = A Brown-out Reset has not occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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5.0 FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and

erasable, during normal operation over the entire VDD

range.

A read from program memory is executed on one byte

at a time. A write to program memory is executed on

blocks of 8 bytes at a time. Program memory is erased

in blocks of 64 bytes at a time. A bulk erase operation

may not be issued from user code.

Writing or erasing program memory will cease

instruction fetches until the operation is complete. The

program memory cannot be accessed during the write

or erase, therefore, code cannot execute. An internal

programming timer terminates program memory writes

and erases.

A value written to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

5.1 Table Reads and Table Writes

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data

RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the

data RAM space is 8 bits wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Table read operations retrieve data from program mem-

ory and place it into the data RAM space. Figure 5-1

shows the operation of a table read with program

memory and data RAM.

Table write operations store data from the data memory

space into holding registers in program memory. The

procedure to write the contents of the holding registers

into program memory is detailed in Section 5.5

“Writing to Flash Program Memory”. Figure 5-2

shows the operation of a table write with program

memory and data RAM.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word aligned. Therefore, a table block

can start and end at any byte address. If a table write is

being used to write executable code into program

memory, program instructions will need to be word

aligned.

FIGURE 5-1: TABLE READ OPERATION

Table Pointer(1)

Table Latch (8-bit)

Program Memory

TBLPTRH TBLPTRL TABLAT

TBLPTRU

Instruction: TBLRD*

Note 1: Table Pointer points to a byte in program memory.

Program Memory

(TBLPTR)

Program Memo (TBLPTR)

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FIGURE 5-2: TABLE WRITE OPERATION

5.2 Control Registers

Several control registers are used in conjunction with

the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

5.2.1 EECON1 AND EECON2 REGISTERS

EECON1 is the control register for memory accesses.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the memory write and erase sequences.

Control bit EEPGD determines if the access will be a

program or data EEPROM memory access. When

clear, any subsequent operations will operate on the

data EEPROM memory. When set, any subsequent

operations will operate on the program memory.

Control bit CFGS determines if the access will be to the

configuration/calibration registers, or to program

memory/data EEPROM memory. When set, subse-

quent operations will operate on configuration regis-

ters, regardless of EEPGD (see Section 23.0 “Special

Features of the CPU”). When clear, memory selection

access is determined by EEPGD.

The FREE bit, when set, will allow a program memory

erase operation. When the FREE bit is set, the erase

operation is initiated on the next WR command. When

FREE is clear, only writes are enabled.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset during normal opera-

tion. In these situations, the user can check the

WRERR bit and rewrite the location. It is necessary to

reload the data and address registers (EEDATA and

EEADR), due to Reset values of zero.

The WR control bit, initiates write operations. The bit

cannot be cleared, only set, in software; it is cleared in

hardware at the completion of the write operation. The

inability to clear the WR bit in software prevents the

accidental or premature termination of a write

operation.

Table Pointer(1) Table Latch (8-bit)

TBLPTRH TBLPTRL TABLAT

Program Memory

(TBLPTR)

TBLPTRU

Instruction: TBLWT*

Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by

TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in

Section 5.5 “Writing to Flash Program Memory”.

Holding Registers

Program Memory

Note: Interrupt flag bit, EEIF in the PIR2 register,

is set when the write is complete. It must

be cleared in software.

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R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR WREN WR RD

bit 7 bit 0

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory

0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access configuration registers

0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0 = Perform write only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit

1 = A write operation is prematurely terminated

(any Reset during self-timed programming in normal operation)

0 = The write operation completed

Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows

tracing of the error condition.

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM

0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write

cycle. (The operation is self-timed and the bit is cleared by hardware once write is

complete. The WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit

can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0 = Does not initiate an EEPROM read

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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5.2.2 TABLAT – TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch is used to hold

8-bit data during data transfers between program

memory and data RAM.

5.2.3 TBLPTR – TABLE POINTER

The Table Pointer (TBLPTR) addresses a byte within

the program memory. The TBLPTR is comprised of

three SFR registers: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low-order 21

bits allow the device to address up to 2 Mbytes of

program memory space. The 22nd bit allows access to

the Device ID, the User ID and the configuration bits.

The Table Pointer, TBLPTR, is used by the TBLRD and

TBLWT instructions. These instructions can update the

TBLPTR in one of four ways, based on the table oper-

ation. These operations are shown in Table 5-1. These

operations on the TBLPTR only affect the low-order

21 bits.

5.2.4 TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the

Flash program memory.

When a TBLRD is executed, all 22 bits of the Table

Pointer determine which byte is read from program

memory into TABLAT.

When a TBLWT is executed, the three LSbs of the Table

Pointer (TBLPTR<2:0>) determine which of the eight

program memory holding registers is written to. When

the timed write to program memory (long write) begins,

the 19 MSbs of the Table Pointer, TBLPTR

(TBLPTR<21:3>), will determine which program mem-

ory block of 8 bytes is written to. For more detail, see

Section 5.5 “Writing to Flash Program Memory”.

When an erase of program memory is executed, the

16 MSbs of the Table Pointer (TBLPTR<21:6>) point to

the 64-byte block that will be erased. The Least

Significant bits (TBLPTR<5:0>) are ignored.

Figure 5-3 describes the relevant boundaries of

TBLPTR based on Flash program memory operations.

TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

FIGURE 5-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

Example Operation on Table Pointer

TBLRD*

TBLWT*

TBLPTR is not modified

TBLRD*+

TBLWT*+

TBLPTR is incremented after the read/write

TBLRD*-

TBLWT*-

TBLPTR is decremented after the read/write

TBLRD+*

TBLWT+*

TBLPTR is incremented before the read/write

21 16 15 87 0

ERASE – TBLPTR<20:6>

WRITE – TBLPTR<21:3>

READ – TBLPTR<21:0>

TBLPTRL

TBLPTRH

TBLPTRU

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5.3 Reading the Flash Program

Memory

The TBLRD instruction is used to retrieve data from

program memory and places it into data RAM. Table

reads from program memory are performed one byte at

a time.

TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

automatically for the next table read operation.

The internal program memory is typically organized by

words. The Least Significant bit of the address selects

between the high and low bytes of the word. Figure 5-4

shows the interface between the internal program

memory and the TABLAT.

FIGURE 5-4: READS FROM FLASH PROGRAM MEMORY

EXAMPLE 5-1: READING A FLASH PROGRAM MEMORY WORD

(Even Byte Address)

Program Memory

(Odd Byte Address)

TBLRD TABLAT

TBLPTR = xxxxx1

FETCH

Instruction Register

(IR) Read Register

TBLPTR = xxxxx0

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWF TBLPTRU ; address of the word

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_WORD

TBLRD*+ ; read into TABLAT and increment

MOVF TABLAT, W ; get data

MOVWF WORD_EVEN

TBLRD*+ ; read into TABLAT and increment

MOVFW TABLAT, W ; get data

MOVWF WORD_ODD

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5.4 Erasing Flash Program Memory

The minimum erase block is 32 words or 64 bytes. Only

through the use of an external programmer, or through

ICSP control, can larger blocks of program memory be

bulk erased. Word erase in the Flash array is not

supported.

When initiating an erase sequence from the micro-

controller itself, a block of 64 bytes of program memory

is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased.

TBLPTR<5:0> are ignored.

The EECON1 register commands the erase operation.

The EEPGD bit must be set to point to the Flash pro-

gram memory. The WREN bit must be set to enable

write operations. The FREE bit is set to select an erase

operation.

For protection, the write initiate sequence for EECON2

must be used.

A long write is necessary for erasing the internal Flash.

Instruction execution is halted while in a long write

cycle. The long write will be terminated by the internal

programming timer.

5.4.1 FLASH PROGRAM MEMORY

ERASE SEQUENCE

The sequence of events for erasing a block of internal

program memory location is:

1. Load Table Pointer with address of row being

erased.

2. Set the EECON1 register for the erase

operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program

memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

3. Disable interrupts.

4. Write 55h to EECON2.

5. Write AAh to EECON2.

6. Set the WR bit. This will begin the row erase

cycle.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

8. Execute a NOP.

9. Re-enable interrupts.

EXAMPLE 5-2: ERASING A FLASH PROGRAM MEMORY ROW

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

ERASE_ROW

BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BSF EECON1, FREE ; enable Row Erase operation

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

MOVWF EECON2 ; write 55H

Required MOVLW AAh

Sequence MOVWF EECON2 ; write AAH

BSF EECON1, WR ; start erase (CPU stall)

NOP

BSF INTCON, GIE ; re-enable interrupts

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5.5 Writing to Flash Program Memory

The minimum programming block is 4 words or 8 bytes.

Word or byte programming is not supported.

Table writes are used internally to load the holding reg-

isters needed to program the Flash memory. There are

8 holding registers used by the table writes for

programming.

Since the Table Latch (TABLAT) is only a single byte,

the TBLWT instruction has to be executed 8 times for

each programming operation. All of the table write

operations will essentially be short writes, because only

the holding registers are written. At the end of updating

8 registers, the EECON1 register must be written to, to

start the programming operation with a long write.

The long write is necessary for programming the inter-

nal Flash. Instruction execution is halted while in a long

write cycle. The long write will be terminated by the

internal programming timer.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device for byte or word operations.

FIGURE 5-5: TABLE WRITES TO FLASH PROGRAM MEMORY

5.5.1 FLASH PROGRAM MEMORY

WRITE SEQUENCE

The sequence of events for programming an internal

program memory location should be:

1. Read 64 bytes into RAM.

2. Update data values in RAM as necessary.

3. Load Table Pointer with address being erased.

4. Do the row erase procedure.

5. Load Table Pointer with address of first byte

being written.

6. Write the first 8 bytes into the holding registers

with auto-increment.

7. Set the EECON1 register for the write operation:

• set EEPGD bit to point to program memory

• clear the CFGS bit to access program

memory

• set WREN to enable byte writes

8. Disable interrupts.

9. Write 55h to EECON2.

10. Write AAh to EECON2.

11. Set the WR bit. This will begin the write cycle.

12. The CPU will stall for duration of the write (about

2 ms using internal timer).

13. Execute a NOP.

14. Re-enable interrupts.

15. Repeat steps 6-14 seven times, to write

64 bytes.

16. Verify the memory (table read).

This procedure will require about 18 ms to update one

row of 64 bytes of memory. An example of the required

code is given in Example 5-3.

Holding Register

TABLAT

Holding Register

TBLPTR = xxxxx7

Holding Register

TBLPTR = xxxxx1

Holding Register

TBLPTR = xxxxx0

88 8 8

Write Register

TBLPTR = xxxxx2

Program Memory

Note: Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the eight bytes

in the holding register.

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EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY

MOVLW D’64 ; number of bytes in erase block

MOVWF COUNTER

MOVLW BUFFER_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW BUFFER_ADDR_LOW

MOVWF FSR0L

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_BLOCK

TBLRD*+ ; read into TABLAT, and inc

MOVF TABLAT, W ; get data

MOVWF POSTINC0 ; store data

DECFSZ COUNTER ; done?

BRA READ_BLOCK ; repeat

MODIFY_WORD

MOVLW DATA_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW DATA_ADDR_LOW

MOVWF FSR0L

MOVLW NEW_DATA_LOW ; update buffer word

MOVWF POSTINC0

MOVLW NEW_DATA_HIGH

MOVWF INDF0

ERASE_BLOCK

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BSF EECON1, FREE ; enable Row Erase operation

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

MOVWF EECON2 ; write 55H

Required MOVLW AAh

Sequence MOVWF EECON2 ; write AAH

BSF EECON1, WR ; start erase (CPU stall)

NOP

BSF INTCON, GIE ; re-enable interrupts

TBLRD*- ; dummy read decrement

WRITE_BUFFER_BACK

MOVLW 8 ; number of write buffer groups of 8 bytes

MOVWF COUNTER_HI

MOVLW BUFFER_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW BUFFER_ADDR_LOW

MOVWF FSR0L

PROGRAM_LOOP

MOVLW 8 ; number of bytes in holding register

MOVWF COUNTER

WRITE_WORD_TO_HREGS

MOVFF POSTINC0, WREG ; get low byte of buffer data

; present data to table latch

TBLWT+* ; write data, perform a short write

; to internal TBLWT holding register.

DECFSZ COUNTER ; loop until buffers are full

BRA WRITE_WORD_TO_HREGS

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EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

5.5.2 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

5.5.3 UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. The WRERR bit is set when a

write operation is interrupted by a MCLR Reset, or a

WDT Time-out Reset during normal operation. In these

situations, users can check the WRERR bit and rewrite

the location.

5.5.4 PROTECTION AGAINST

SPURIOUS WRITES

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 23.0 “Special Features of the

CPU” for more detail.

5.6 Flash Program Operation During

Code Protection

See Section 23.0 “Special Features of the CPU” for

details on code protection of Flash program memory.

TABLE 5-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

PROGRAM_MEMORY

BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

MOVWF EECON2 ; write 55H

Required MOVLW AAh

Sequence MOVWF EECON2 ; write AAH

BSF EECON1, WR ; start program (CPU stall)

NOP

BSF INTCON, GIE ; re-enable interrupts

DECFSZ COUNTER_HI ; loop until done

BRA PROGRAM_LOOP

BCF EECON1, WREN ; disable write to memory

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte

(TBLPTR<20:16>)

--00 0000 --00 0000

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000

TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000

TABLAT Program Memory Table Latch 0000 0000 0000 0000

INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 0000 0000 0000

EECON2 EEPROM Control Register 2 (not a physical register) — —

EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000

IPR2 —CMIP —EEIPBCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111

PIR2 —CMIF —EEIFBCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000

PIE2 —CMIE —EEIEBCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000

Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.

Shaded cells are not used during Flash/EEPROM access.

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6.0 EXTERNAL MEMORY

INTERFACE

The External Memory Interface is a feature of the

PIC18F8X20 devices that allows the controller to

access external memory devices (such as Flash,

EPROM, SRAM, etc.) as program or data memory.

The physical implementation of the interface uses 27

pins. These pins are reserved for external address/data

bus functions; they are multiplexed with I/O port pins on

four ports. Three I/O ports are multiplexed with the

address/data bus, while the fourth port is multiplexed

with the bus control signals. The I/O port functions are

enabled when the EBDIS bit in the MEMCON register

is set (see Register 6-1). A list of the multiplexed pins

and their functions is provided in Table 6-1.

As implemented in the PIC18F8X20 devices, the

interface operates in a similar manner to the external

memory interface introduced on PIC18C601/801

microcontrollers. The most notable difference is that

the interface on PIC18F8X20 devices only operates in

16-bit modes. The 8-bit mode is not supported.

For a more complete discussion of the operating modes

that use the external memory interface, refer to

Section 4.1.1 “PIC18F8X20 Program Memory

Modes”.

6.1 Program Memory Modes and the

External Memory Interface

As previously noted, PIC18F8X20 controllers are

capable of operating in any one of four program

memory modes, using combinations of on-chip and

external program memory. The functions of the multi-

plexed port pins depend on the program memory

mode selected, as well as the setting of the EBDIS bit.

In Microprocessor Mode, the external bus is always

active and the port pins have only the external bus

function.

In Microcontroller Mode, the bus is not active and

the pins have their port functions only. Writes to the

MEMCOM register are not permitted.

In Microprocessor with Boot Block or Extended

Microcontroller Mode, the external program memory

bus shares I/O port functions on the pins. When the

device is fetching or doing table read/table write

operations on the external program memory space, the

pins will have the external bus function. If the device is

fetching and accessing internal program memory loca-

tions only, the EBDIS control bit will change the pins

from external memory to I/O port functions. When

EBDIS = 0, the pins function as the external bus.

When EBDIS = 1, the pins function as I/O ports.

Note: The External Memory Interface is not

implemented on PIC18F6X20 (64-pin)

devices.

Note: Maximum FOSC for the PIC18FX520 is

limited to 25 MHz when using the external

memory interface.

R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

EBDIS —WAIT1WAIT0——WM1WM0

bit7 bit0

bit 7 EBDIS: External Bus Disable bit

1 = External system bus disabled, all external bus drivers are mapped as I/O ports

0 = External system bus enabled and I/O ports are disabled

bit 6 Unimplemented: Read as ‘0’

bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits

11 = Table reads and writes will wait 0 TCY

10 = Table reads and writes will wait 1 TCY

01 = Table reads and writes will wait 2 TCY

00 = Table reads and writes will wait 3 TCY

bit 3-2 Unimplemented: Read as ‘0’

bit 1-0 WM<1:0>: TBLWRT Operation with 16-bit Bus bits

1x = Word Write mode: TABLAT<0> and TABLAT<1> word output, WRH active when

TABLAT<1> written

01 = Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB)

will activate

00 = Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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If the device fetches or accesses external memory

while EBDIS = 1, the pins will switch to external bus. If

the EBDIS bit is set by a program executing from

external memory, the action of setting the bit will be

delayed until the program branches into the internal

memory. At that time, the pins will change from

external bus to I/O ports.

When the device is executing out of internal memory

(EBDIS = 0) in Microprocessor with Boot Block mode,

or Extended Microcontroller mode, the control signals

will NOT be active. They will go to a state where the

AD<15:0> and A<19:16> are tri-state; the CE, OE,

WRH, WRL, UB and LB signals are ‘1’ and ALE and

BA0 are ‘0’.

TABLE 6-1: PIC18F8X20 EXTERNAL BUS – I/O PORT FUNCTIONS

Name Port Bit Function

RD0/AD0 PORTD bit 0 Input/Output or System Bus Address bit 0 or Data bit 0.

RD1/AD1 PORTD bit 1 Input/Output or System Bus Address bit 1 or Data bit 1.

RD2/AD2 PORTD bit 2 Input/Output or System Bus Address bit 2 or Data bit 2.

RD3/AD3 PORTD bit 3 Input/Output or System Bus Address bit 3 or Data bit 3.

RD4/AD4 PORTD bit 4 Input/Output or System Bus Address bit 4 or Data bit 4.

RD5/AD5 PORTD bit 5 Input/Output or System Bus Address bit 5 or Data bit 5.

RD6/AD6 PORTD bit 6 Input/Output or System Bus Address bit 6 or Data bit 6.

RD7/AD7 PORTD bit 7 Input/Output or System Bus Address bit 7 or Data bit 7.

RE0/AD8 PORTE bit 0 Input/Output or System Bus Address bit 8 or Data bit 8.

RE1/AD9 PORTE bit 1 Input/Output or System Bus Address bit 9 or Data bit 9.

RE2/AD10 PORTE bit 2 Input/Output or System Bus Address bit 10 or Data bit 10.

RE3/AD11 PORTE bit 3 Input/Output or System Bus Address bit 11 or Data bit 11.

RE4/AD12 PORTE bit 4 Input/Output or System Bus Address bit 12 or Data bit 12.

RE5/AD13 PORTE bit 5 Input/Output or System Bus Address bit 13 or Data bit 13.

RE6/AD14 PORTE bit 6 Input/Output or System Bus Address bit 14 or Data bit 14.

RE7/AD15 PORTE bit 7 Input/Output or System Bus Address bit 15 or Data bit 15.

RH0/A16 PORTH bit 0 Input/Output or System Bus Address bit 16.

RH1/A17 PORTH bit 1 Input/Output or System Bus Address bit 17.

RH2/A18 PORTH bit 2 Input/Output or System Bus Address bit 18.

RH3/A19 PORTH bit 3 Input/Output or System Bus Address bit 19.

RJ0/ALE PORTJ bit 0 Input/Output or System Bus Address Latch Enable (ALE) Control pin.

RJ1/OE PORTJ bit 1 Input/Output or System Bus Output Enable (OE) Control pin.

RJ2/WRL PORTJ bit 2 Input/Output or System Bus Write Low (WRL) Control pin.

RJ3/WRH PORTJ bit 3 Input/Output or System Bus Write High (WRH) Control pin.

RJ4/BA0 PORTJ bit 4 Input/Output or System Bus Byte Address bit 0.

RJ5/CE PORTJ bit 5 Input/Output or System Bus Chip Enable (CE) Control pin.

RJ6/LB PORTJ bit 6 Input/Output or System Bus Lower Byte Enable (LB) Control pin.

RJ7/UB PORTJ bit 7 Input/Output or System Bus Upper Byte Enable (UB) Control pin.

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6.2 16-bit Mode

The External Memory Interface implemented in

PIC18F8X20 devices operates only in 16-bit mode.

The mode selection is not software configurable, but is

programmed via the configuration bits.

The WM<1:0> bits in the MEMCON register determine

three types of connections in 16-bit mode. They are

referred to as:

• 16-bit Byte Write

• 16-bit Word Write

• 16-bit Byte Select

These three different configurations allow the designer

maximum flexibility in using 8-bit and 16-bit memory

devices.

For all 16-bit modes, the Address Latch Enable (ALE)

pin indicates that the address bits A<15:0> are

available on the External Memory Interface bus.

Following the address latch, the Output Enable signal

(OE) will enable both bytes of program memory at once

to form a 16-bit instruction word. The Chip Enable

signal (CE) is active at any time that the microcontroller

accesses external memory, whether reading or writing;

it is inactive (asserted high) whenever the device is in

Sleep mode.

In Byte Select mode, JEDEC standard Flash memories

will require BA0 for the byte address line and one I/O

line to select between Byte and Word mode. The other

16-bit modes do not need BA0. JEDEC standard static

RAM memories will use the UB or LB signals for byte

selection.

6.2.1 16-BIT BYTE WRITE MODE

Figure 6-1 shows an example of 16-bit Byte Write

mode for PIC18F8X20 devices. This mode is used for

two separate 8-bit memories connected for 16-bit oper-

ation. This generally includes basic EPROM and Flash

devices. It allows table writes to byte-wide external

memories.

During a TBLWT instruction cycle, the TABLAT data is

presented on the upper and lower bytes of the

AD15:AD0 bus. The appropriate WRH or WRL control

line is strobed on the LSb of the TBLPTR.

FIGURE 6-1: 16-BIT BYTE WRITE MODE EXAMPLE

AD<7:0>

A<19:16>

ALE

D<15:8>

373 A<x:0>

D<7:0>

A<19:0> A<x:0>

D<7:0>

373

WRH

OE OE

WR(1) WR(1)

CE CE

Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.

WRL

D<7:0>

(LSB)(MSB)

PIC18F8X20

D<7:0>

AD<15:8>

Address Bus

Data Bus

Control Lines

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6.2.2 16-BIT WORD WRITE MODE

Figure 6-2 shows an example of 16-bit Word Write

mode for PIC18F8X20 devices. This mode is used for

word-wide memories, which includes some of the

EPROM and Flash type memories. This mode allows

opcode fetches and table reads from all forms of 16-bit

memory and table writes to any type of word-wide

external memories. This method makes a distinction

between TBLWT cycles to even or odd addresses.

During a TBLWT cycle to an even address

(TBLPTR<0> = 0), the TABLAT data is transferred to a

holding latch and the external address data bus is

tri-stated for the data portion of the bus cycle. No write

signals are activated.

During a TBLWT cycle to an odd address

(TBLPTR<0> = 1), the TABLAT data is presented on

the upper byte of the AD15:AD0 bus. The contents of

the holding latch are presented on the lower byte of the

AD15:AD0 bus.

The WRH signal is strobed for each write cycle; the

WRL pin is unused. The signal on the BA0 pin indicates

the LSb of TBLPTR, but it is left unconnected. Instead,

the UB and LB signals are active to select both bytes.

The obvious limitation to this method is that the table

write must be done in pairs on a specific word boundary

to correctly write a word location.

FIGURE 6-2: 16-BIT WORD WRITE MODE EXAMPLE

AD<7:0>

PIC18F8X20

AD<15:8>

ALE

373 A<20:1>

373

WRH

A<19:16>

A<x:0>

D<15:0>

OE WR(1) CE

D<15:0>

JEDEC Word

EPROM Memory

Address Bus

Data Bus

Control Lines

Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.

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6.2.3 16-BIT BYTE SELECT MODE

Figure 6-3 shows an example of 16-bit Byte Select

mode for PIC18F8X20 devices. This mode allows table

write operations to word-wide external memories with

byte selection capability. This generally includes both

word-wide Flash and SRAM devices.

During a TBLWT cycle, the TABLAT data is presented

on the upper and lower byte of the AD15:AD0 bus. The

WRH signal is strobed for each write cycle; the WRL

pin is not used. The BA0 or UB/LB signals are used to

select the byte to be written, based on the Least

Significant bit of the TBLPTR register.

Flash and SRAM devices use different control signal

combinations to implement Byte Select mode. JEDEC

standard Flash memories require that a controller I/O

port pin be connected to the memory’s BYTE/WORD

pin to provide the select signal. They also use the BA0

signal from the controller as a byte address. JEDEC

standard static RAM memories, on the other hand, use

the UB or LB signals to select the byte.

FIGURE 6-3: 16-BIT BYTE SELECT MODE EXAMPLE

AD<7:0>

PIC18F8X20

AD<15:8>

ALE

373 A<20:1>

373

WRH

A<19:16>

WRL

BA0

JEDEC Word

A<x:1>

D<15:0>

A<20:1>

D<15:0>

I/O

OE WR(1)

BYTE/WORD

Flash Memory

JEDEC Word

A<x:1>

D<15:0>

OE WR(1)

SRAM Memory

138

Address Bus

Data Bus

Control Lines

Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.

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6.2.4 16-BIT MODE TIMING

The presentation of control signals on the external

memory bus is different for the various operating

modes. Typical signal timing diagrams are shown in

Figure 6-4 through Figure 6-6.

FIGURE 6-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)

FIGURE 6-5: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED

MICROCONTROLLER MODE)

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q4Q4 Q4 Q4

ALE

3AABh

WRH

WRL

AD<15:0>

BA0

CF33h 9256h

0E55h

‘1’ ‘1’

‘1’

Table Read

of 92h

from 199E67h

1 TCY Wait

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

Apparent Q

Actual Q

A<19:16> 0Ch

00h

CE ‘0’

‘0’

Memory

Cycle

Instruction

Execution TBLRD Cycle 1 TBLRD Cycle 2

Opcode Fetch

MOVLW 55h

from 007556h

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

A<19:16>

ALE

AD<15:0>

Opcode Fetch Opcode Fetch Opcode Fetch

TBLRD *

TBLRD Cycle 1

ADDLW 55h

from 000100h

Q2Q1 Q3 Q4

0Ch

CF33h

TBLRD 92h

from 199E67h

9256h

from 000104h

Memory

Cycle

Instruction

Execution INST(PC-2) TBLRD Cycle 2

MOVLW 55h

from 000102h

MOVLW

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FIGURE 6-6: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE)

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

A<19:16>

ALE

3AAAh

AD<15:0>

00h 00h

Opcode Fetch Opcode Fetch

SLEEP

from 007554h

Bus Inactive

0003h

3AABh

0E55h

Memory

Cycle

Instruction

Execution INST(PC-2)

Sleep Mode,

MOVLW 55h

from 007556h

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NOTES:

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7.0 DATA EEPROM MEMORY

The data EEPROM is readable and writable during

normal operation over the entire VDD range. The data

memory is not directly mapped in the register file

space. Instead, it is indirectly addressed through the

Special Function Registers (SFR).

There are five SFRs used to read and write the

program and data EEPROM memory. These registers

are:

• EECON1

• EECON2

• EEDATA

• EEADRH

• EEADR

The EEPROM data memory allows byte read and write.

When interfacing to the data memory block, EEDATA

holds the 8-bit data for read/write. EEADR and

EEADRH hold the address of the EEPROM location

being accessed. These devices have 1024 bytes of

data EEPROM with an address range from 00h to

3FFh.

The EEPROM data memory is rated for high erase/

write cycles. A byte write automatically erases the loca-

tion and writes the new data (erase-before-write). The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature, as well as

from chip to chip. Please refer to parameter D122 (see

Section 26.0 “Electrical Characteristics”) for exact

limits.

7.1 EEADR and EEADRH

The address register pair can address up to a maxi-

mum of 1024 bytes of data EEPROM. The two Most

Significant bits of the address are stored in EEADRH,

while the remaining eight Least Significant bits are

stored in EEADR. The six Most Significant bits of

EEADRH are unused and are read as ‘0’.

7.2 EECON1 and EECON2 Registers

EECON1 is the control register for EEPROM memory

accesses.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the EEPROM write sequence.

Control bits, RD and WR, initiate read and write opera-

tions, respectively. These bits cannot be cleared, only

set, in software. They are cleared in hardware at the

completion of the read or write operation. The inability

to clear the WR bit in software prevents the accidental

or premature termination of a write operation.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset or a WDT Time-out Reset during normal opera-

tion. In these situations, the user can check the

WRERR bit and rewrite the location. It is necessary to

reload the data and address registers (EEDATA and

EEADR) due to the Reset condition forcing the

contents of the registers to zero.

Note: Interrupt flag bit, EEIF in the PIR2 register,

is set when write is complete. It must be

cleared in software.

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R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR WREN WR RD

bit 7 bit 0

bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit

1 = Access Flash program memory

0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access configuration or calibration registers

0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0 = Perform write only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit

1 = A write operation is prematurely terminated

(any MCLR or any WDT Reset during self-timed programming in normal operation)

0 = The write operation completed

Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows

tracing of the error condition.

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM

0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit

can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0 = Does not initiate an EEPROM read

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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7.3 Reading the Data EEPROM

Memory

To read a data memory location, the user must write the

address to the EEADRH:EEADR register pair, clear the

EEPGD control bit (EECON1<7>), clear the CFGS

control bit (EECON1<6>) and then set the RD control

bit (EECON1<0>). The data is available for the very

next instruction cycle; therefore, the EEDATA register

can be read by the next instruction. EEDATA will hold

this value until another read operation, or until it is

written to by the user (during a write operation).

EXAMPLE 7-1: DATA EEPROM READ

7.4 Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must

first be written to the EEADRH:EEADR register pair

and the data written to the EEDATA register. Then the

sequence in Example 7-2 must be followed to initiate

the write cycle.

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code

execution (i.e., runaway programs). The WREN bit

should be kept clear at all times, except when updating

the EEPROM. The WREN bit is not cleared

by hardware

After a write sequence has been initiated, EECON1,

EEADRH, EEADR and EEDATA cannot be modified.

The WR bit will be inhibited from being set unless the

WREN bit is set. Both WR and WREN cannot be set

with the same instruction.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EEPROM Write Complete

Interrupt Flag bit (EEIF) is set. The user may either

enable this interrupt, or poll this bit. EEIF must be

cleared by software.

EXAMPLE 7-2: DATA EEPROM WRITE

MOVLW DATA_EE_ADDRH ;

MOVWF EEADRH ; Upper bits of Data Memory Address to read

MOVLW DATA_EE_ADDR ;

MOVWF EEADR ; Lower bits of Data Memory Address to read

BCF EECON1, EEPGD ; Point to DATA memory

BCF EECON1, CFGS ; Access EEPROM

BSF EECON1, RD ; EEPROM Read

MOVF EEDATA, W ; W = EEDATA

MOVLW DATA_EE_ADDRH ;

MOVWF EEADRH ; Upper bits of Data Memory Address to write

MOVLW DATA_EE_ADDR ;

MOVWF EEADR ; Lower bits of Data Memory Address to write

MOVLW DATA_EE_DATA ;

MOVWF EEDATA ; Data Memory Value to write

BCF EECON1, EEPGD ; Point to DATA memory

BCF EECON1, CFGS ; Access EEPROM

BSF EECON1, WREN ; Enable writes

BCF INTCON, GIE ; Disable Interrupts

MOVLW 55h ;

Required MOVWF EECON2 ; Write 55h

Sequence MOVLW AAh ;

MOVWF EECON2 ; Write AAh

BSF EECON1, WR ; Set WR bit to begin write

BSF INTCON, GIE ; Enable Interrupts

; User code execution

BCF EECON1, WREN ; Disable writes on write complete (EEIF set)

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7.5 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

7.6 Protection Against Spurious Write

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared.

Also, the Power-up Timer (72 ms duration) prevents

EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

7.7 Operation During Code-Protect

Data EEPROM memory has its own code-protect

mechanism. External read and write operations are

disabled if either of these mechanisms are enabled.

The microcontroller itself can both read and write to the

internal data EEPROM, regardless of the state of the

code-protect configuration bit. Refer to Section 23.0

“Special Features of the CPU” for additional

information.

7.8 Using the Data EEPROM

The data EEPROM is a high endurance, byte address-

able array that has been optimized for the storage of

frequently changing information (e.g., program vari-

ables or other data that are updated often). Frequently

changing values will typically be updated more often

than specification D124. If this is not the case, an array

refresh must be performed. For this reason, variables

that change infrequently (such as constants, IDs,

calibration, etc.) should be stored in Flash program

memory.

A simple data EEPROM refresh routine is shown in

Example 7-3.

EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE

Note: If data EEPROM is only used to store

constants and/or data that changes rarely,

an array refresh is likely not required. See

specification D124.

CLRF EEADR ; Start at address 0

CLRF EEADRH ;

BCF EECON1, CFGS ; Set for memory

BCF EECON1, EEPGD ; Set for Data EEPROM

BCF INTCON, GIE ; Disable interrupts

BSF EECON1, WREN ; Enable writes

Loop ; Loop to refresh array

BSF EECON1, RD ; Read current address

MOVLW 55h ;

MOVWF EECON2 ; Write 55h

MOVLW AAh ;

MOVWF EECON2 ; Write AAh

BSF EECON1, WR ; Set WR bit to begin write

BTFSC EECON1, WR ; Wait for write to complete

BRA $-2

INCFSZ EEADR, F ; Increment address

BRA Loop ; Not zero, do it again

INCFSZ EEADRH, F ; Increment the high address

BRA Loop ; Not zero, do it again

BCF EECON1, WREN ; Disable writes

BSF INTCON, GIE ; Enable interrupts

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TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

EEADRH — — — — — — EE Addr Register High ---- --00 ---- --00

EEADR EEPROM Address Register 0000 0000 0000 0000

EEDATA EEPROM Data Register 0000 0000 0000 0000

EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----

EECON1 EEPGD CFGS —FREE WRERR WREN WR RD xx-0 x000 uu-0 u000

IPR2 —CMIP —EEIPBCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111

PIR2 —CMIF —EEIFBCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000

PIE2 —CMIE —EEIEBCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000

Legend: x = unknown, u = unchanged, r = reserved, – = unimplemented, read as ‘0’.

Shaded cells are not used during Flash/EEPROM access.

PIC18F6520/8520/6620/8620/6720/8720

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NOTES:

 2003-2013 Microchip Technology Inc. DS39609C-page 85

PIC18F6520/8520/6620/8620/6720/8720

8.0 8 X 8 HARDWARE MULTIPLIER

8.1 Introduction

An 8 x 8 hardware multiplier is included in the ALU of

the PIC18FXX20 devices. By making the multiply a

hardware operation, it completes in a single instruction

cycle. This is an unsigned multiply that gives a 16-bit

result. The result is stored in the 16-bit product register

pair (PRODH:PRODL). The multiplier does not affect

any flags in the ALUSTA register.

Making the 8 x 8 multiplier execute in a single cycle

gives the following advantages:

• Higher computational throughput

• Reduces code size requirements for multiply

algorithms

The performance increase allows the device to be used

in applications previously reserved for Digital Signal

Processors.

Table 8-1 shows a performance comparison between

enhanced devices using the single-cycle hardware

multiply and performing the same function without the

hardware multiply.

8.2 Operation

Example 8-1 shows the sequence to do an 8 x 8

unsigned multiply. Only one instruction is required

when one argument of the multiply is already loaded in

the WREG register.

Example 8-2 shows the sequence to do an 8 x 8 signed

multiply. To account for the sign bits of the arguments,

each argument’s Most Significant bit (MSb) is tested

and the appropriate subtractions are done.

EXAMPLE 8-1: 8 x 8 UNSIGNED

MULTIPLY ROUTINE

EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

TABLE 8-1: PERFORMANCE COMPARISON

MOVF ARG1, W ;

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

MOVF ARG1, W ;

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

BTFSC ARG2, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG1

MOVF ARG2, W ;

BTFSC ARG1, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

Routine Multiply Method Program

Memory

(Words)

Cycles

(Max)

Time

@ 40 MHz @ 10 MHz @ 4 MHz

8 x 8 unsigned Without hardware multiply 13 69 6.9 s27.6 s69 s

Hardware multiply 1 1 100 ns 400 ns 1 s

8 x 8 signed Without hardware multiply 33 91 9.1 s36.4 s91 s

Hardware multiply 6 6 600 ns 2.4 s6 s

16 x 16 unsigned Without hardware multiply 21 242 24.2 s96.8 s242 s

Hardware multiply 28 28 2.8 s 11.2 s28 s

16 x 16 signed Without hardware multiply 52 254 25.4 s 102.6 s254 s

Hardware multiply 35 40 4.0 s16.0 s40 s

ﬂﬂ

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 86  2003-2013 Microchip Technology Inc.

Example 8-3 shows the sequence to do a 16 x 16

unsigned multiply. Equation 8-1 shows the algorithm

that is used. The 32-bit result is stored in four registers,

RES3:RES0.

EQUATION 8-1: 16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8-3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

Example 8-4 shows the sequence to do a 16 x 16

signed multiply. Equation 8-2 shows the algorithm

used. The 32-bit result is stored in four registers,

RES3:RES0. To account for the sign bits of the argu-

ments, each argument pairs’ Most Significant bit (MSb)

is tested and the appropriate subtractions are done.

EQUATION 8-2: 16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8-4: 16 x 16 SIGNED

MULTIPLY ROUTINE

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L ->

; PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H ->

; PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L

= (ARG1H  ARG2H  216) +

(ARG1H  ARG2L  28) +

(ARG1L  ARG2H  28) +

(ARG1L  ARG2L)

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L ->

; PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H ->

; PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?

BRA SIGN_ARG1 ; no, check ARG1

MOVF ARG1L, W ;

SUBWF RES2 ;

MOVF ARG1H, W ;

SUBWFB RES3

;

SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?

BRA CONT_CODE ; no, done

MOVF ARG2L, W ;

SUBWF RES2 ;

MOVF ARG2H, W ;

SUBWFB RES3

;

CONT_CODE

RES3:RES0

= ARG1H:ARG1L  ARG2H:ARG2L

= (ARG1H  ARG2H  216) +

(ARG1H  ARG2L  28) +

(ARG1L  ARG2H  28) +

(ARG1L  ARG2L) +

(-1  ARG2H<7>  ARG1H:ARG1L  216) +

(-1  ARG1H<7>  ARG2H:ARG2L  216)

 2003-2013 Microchip Technology Inc. DS39609C-page 87

PIC18F6520/8520/6620/8620/6720/8720

9.0 INTERRUPTS

The PIC18FXX20 devices have multiple interrupt

sources and an interrupt priority feature that allows

each interrupt source to be assigned a high or a low

priority level. The high priority interrupt vector is at

000008h, while the low priority interrupt vector is at

000018h. High priority interrupt events will override any

low priority interrupts that may be in progress.

There are thirteen registers which are used to control

interrupt operation. They are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2, PIR3

• PIE1, PIE2, PIE3

• IPR1, IPR2, IPR3

It is recommended that the Microchip header files,

supplied with MPLAB® IDE, be used for the symbolic bit

names in these registers. This allows the assembler/

compiler to automatically take care of the placement of

these bits within the specified register.

Each interrupt source has three bits to control its

operation. The functions of these bits are:

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the

IPEN bit (RCON<7>). When interrupt priority is

enabled, there are two bits which enable interrupts

globally. Setting the GIEH bit (INTCON<7>) enables all

interrupts that have the priority bit set. Setting the GIEL

bit (INTCON<6>) enables all interrupts that have the

priority bit cleared. When the interrupt flag, enable bit

and appropriate global interrupt enable bit are set, the

interrupt will vector immediately to address 000008h or

000018h, depending on the priority level. Individual

interrupts can be disabled through their corresponding

enable bits.

When the IPEN bit is cleared (default state), the

interrupt priority feature is disabled and interrupts are

compatible with PIC® mid-range devices. In Compati-

bility mode, the interrupt priority bits for each source

have no effect. INTCON<6> is the PEIE bit, which

enables/disables all peripheral interrupt sources.

INTCON<7> is the GIE bit, which enables/disables all

interrupt sources. All interrupts branch to address

000008h in Compatibility mode.

When an interrupt is responded to, the Global Interrupt

Enable bit is cleared to disable further interrupts. If the

IPEN bit is cleared, this is the GIE bit. If interrupt priority

levels are used, this will be either the GIEH or GIEL bit.

High priority interrupt sources can interrupt a low

priority interrupt.

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address

(000008h or 000018h). Once in the Interrupt Service

Routine, the source(s) of the interrupt can be deter-

mined by polling the interrupt flag bits. The interrupt

flag bits must be cleared in software before re-enabling

interrupts to avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIE bit (GIEH or GIEL

if priority levels are used), which re-enables interrupts.

For external interrupt events, such as the INT pins or

the PORTB input change interrupt, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one or two-cycle instructions.

Individual interrupt flag bits are set, regardless of the

status of their corresponding enable bit or the GIE bit.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 88  2003-2013 Microchip Technology Inc.

FIGURE 9-1: INTERRUPT LOGIC

TMR0IE

GIEH/GIE

GIEL/PEIE

Wake-up if in Sleep mode

Interrupt to CPU

Vector to Location

0008h

INT2IF

INT2IE

INT2IP

INT1IF

INT1IE

INT1IP

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP

IPEN

TMR0IF

TMR0IP

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

RBIF

RBIE

RBIP

INT0IF

INT0IE

GIEL/PEIE

Interrupt to CPU

Vector to Location

IPEN

0018h

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

TMR1IF

TMR1IE

TMR1IP

XXXXIF

XXXXIE

XXXXIP

Additional Peripheral Interrupts

TMR1IF

TMR1IE

TMR1IP

High Priority Interrupt Generation

Low Priority Interrupt Generation

XXXXIF

XXXXIE

XXXXIP

Additional Peripheral Interrupts

GIE/GEIH

When \PEN RCON<7> : 0 When \PEN RCON<7> : 1 When \PEN RCON<7> : 0 When \PEN RCON<7> : 1

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9.1 INTCON Registers

The INTCON registers are readable and writable

registers, which contain various enable, priority and

flag bits.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit. User software should ensure

the appropriate interrupt flag bits are clear

prior to enabling an interrupt. This feature

allows for software polling.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

bit 7 bit 0

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN (RCON<7>) = 0:

1 = Enables all unmasked interrupts

0 = Disables all interrupts

When IPEN (RCON<7>) = 1:

1 = Enables all high priority interrupts

0 = Disables all interrupts

bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN (RCON<7>) = 0:

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

When IPEN (RCON<7>) = 1:

1 = Enables all low priority peripheral interrupts

0 = Disables all low priority peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt

0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt

0 = Disables the INT0 external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1 INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared in software)

0 = The INT0 external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

Note: A mismatch condition will continue to set this bit. Reading PORTB will end the

mismatch condition and allow the bit to be cleared.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP

bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG0: External Interrupt 0 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 5 INTEDG1: External Interrupt 1 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 4 INTEDG2: External Interrupt 2 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 3 INTEDG3: External Interrupt 3 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 INT3IP: INT3 External Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0 RBIP: RB Port Change Interrupt Priority bit

1 = High priority

0 = Low priority

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

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R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF

bit 7 bit 0

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 = High priority

0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 INT3IE: INT3 External Interrupt Enable bit

1 = Enables the INT3 external interrupt

0 = Disables the INT3 external interrupt

bit 4 INT2IE: INT2 External Interrupt Enable bit

1 = Enables the INT2 external interrupt

0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt

0 = Disables the INT1 external interrupt

bit 2 INT3IF: INT3 External Interrupt Flag bit

1 = The INT3 external interrupt occurred (must be cleared in software)

0 = The INT3 external interrupt did not occur

bit 1 INT2IF: INT2 External Interrupt Flag bit

1 = The INT2 external interrupt occurred (must be cleared in software)

0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared in software)

0 = The INT1 external interrupt did not occur

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

Cagture mode. Comgare mode. PWM mode.

PIC18F6520/8520/6620/8620/6720/8720

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9.2 PIR Registers

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are three Peripheral Interrupt

Flag Registers (PIR1, PIR2 and PIR3).

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt and after servicing

that interrupt.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write has occurred

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete

bit 5 RC1IF: USART1 Receive Interrupt Flag bit

1 = The USART1 receive buffer, RCREG, is full (cleared when RCREG is read)

0 = The USART1 receive buffer is empty

bit 4 TX1IF: USART Transmit Interrupt Flag bit

1 = The USART1 transmit buffer, TXREG, is empty (cleared when TXREG is written)

0 = The USART1 transmit buffer is full

bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow

Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Cagture mode. Cumgare mode. FWM mode.

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U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—CMIF— EEIF BCLIF LVDIF TMR3IF CCP2IF

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6 CMIF: Comparator Interrupt Flag bit

1 = The comparator input has changed (must be cleared in software)

0 = The comparator input has not changed

bit 5 Unimplemented: Read as ‘0’

bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit

1 = The write operation is complete (must be cleared in software)

0 = The write operation is not complete, or has not been started

bit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision occurred while the SSP module (configured in I2C Master mode)

was transmitting (must be cleared in software)

0 = No bus collision occurred

bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit

1 = A low-voltage condition occurred (must be cleared in software)

0 = The device voltage is above the Low-Voltage Detect trip point

bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit

1 = TMR3 register overflowed (must be cleared in software)

0 = TMR3 register did not overflow

bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1 or TMR3 register capture occurred (must be cleared in software)

0 = No TMR1 or TMR3 register capture occurred

Compare mode:

1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software)

0 = No TMR1 or TMR3 register compare match occurred

PWM mode:

Unused in this mode.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Capture mode. Cumgare mode. FWM mode.

PIC18F6520/8520/6620/8620/6720/8720

DS39609C-page 94  2003-2013 Microchip Technology Inc.

U-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

—— RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF

bit 7 bit 0

bit 7- 6 Unimplemented: Read as ‘0’

bit 5 RC2IF: USART2 Receive Interrupt Flag bit

1 = The USART2 receive buffer, RCREG, is full (cleared when RCREG is read)

0 = The USART2 receive buffer is empty

bit 4 TX2IF: USART2 Transmit Interrupt Flag bit

1 = The USART2 transmit buffer, TXREG, is empty (cleared when TXREG is written)

0 = The USART2 transmit buffer is full

bit 3 TMR4IF: TMR3 Overflow Interrupt Flag bit

1 = TMR4 register overflowed (must be cleared in software)

0 = TMR4 register did not overflow

bit 2-0 CCPxIF: CCPx Interrupt Flag bit (CCP Modules 3, 4 and 5)

Capture mode:

1 = A TMR1 or TMR3 register capture occurred (must be cleared in software)

0 = No TMR1 or TMR3 register capture occurred

Compare mode:

1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software)

0 = No TMR1 or TMR3 register compare match occurred

PWM mode:

Unused in this mode.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003-2013 Microchip Technology Inc. DS39609C-page 95

PIC18F6520/8520/6620/8620/6720/8720

9.3 PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Enable registers (PIE1, PIE2 and PIE3).

When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit must

be set to enable any of these peripheral interrupts.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit 5 RC1IE: USART1 Receive Interrupt Enable bit

1 = Enables the USART1 receive interrupt

0 = Disables the USART1 receive interrupt

bit 4 TX1IE: USART1 Transmit Interrupt Enable bit

1 = Enables the USART1 transmit interrupt

0 = Disables the USART1 transmit interrupt

bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit

1 = Enables the MSSP interrupt

0 = Disables the MSSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC18F6520/8520/6620/8620/6720/8720

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U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—CMIE— EEIE BCLIE LVDIE TMR3IE CCP2IE

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6 CMIE: Comparator Interrupt Enable bit

1 = Enables the comparator interrupt

0 = Disables the comparator interrupt

bit 5 Unimplemented: Read as ‘0’

bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit

1 = Enables the write operation interrupt

0 = Disables the write operation interrupt

bit 3 BCLIE: Bus Collision Interrupt Enable bit

1 = Enables the bus collision interrupt

0 = Disables the bus collision interrupt

bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit

1 = Enables the Low-Voltage Detect interrupt

0 = Disables the Low-Voltage Detect interrupt

bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit

1 = Enables the TMR3 overflow interrupt

0 = Disables the TMR3 overflow interrupt

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5 RC2IE: USART2 Receive Interrupt Enable bit

1 = Enables the USART2 receive interrupt

0 = Disables the USART2 receive interrupt

bit 4 TX2IE: USART2 Transmit Interrupt Enable bit

1 = Enables the USART2 transmit interrupt

0 = Disables the USART2 transmit interrupt

bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit

1 = Enables the TMR4 to PR4 match interrupt

0 = Disables the TMR4 to PR4 match interrupt

bit 2-0 CCPxIE: CCPx Interrupt Enable bit (CCP Modules 3, 4 and 5)

1 = Enables the CCPx interrupt

0 = Disables the CCPx interrupt

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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9.4 IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Priority Registers (IPR1, IPR2 and IPR3). The

operation of the priority bits requires that the Interrupt

Priority Enable (IPEN) bit be set.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP

bit 7 bit 0

bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)

1 = High priority

0 = Low priority

bit 6 ADIP: A/D Converter Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 RC1IP: USART1 Receive Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4 TX1IP: USART1 Transmit Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit

1 = High priority

0 = Low priority

bit 2 CCP1IP: CCP1 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

—CMIP— EEIP BCLIP LVDIP TMR3IP CCP2IP

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6 CMIP: Comparator Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 Unimplemented: Read as ‘0’

bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3 BCLIP: Bus Collision Interrupt Priority bit

1 = High priority

0 = Low priority

bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0 CCP2IP: CCP2 Interrupt Priority bit

1 = High priority

0 = Low priority

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

—— RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5 RC2IP: USART2 Receive Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4 TX2IP: USART2 Transmit Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit

1 = High priority

0 = Low priority

bit 2-0 CCPxIP: CCPx Interrupt Priority bit (CCP Modules 3, 4 and 5)

1 = High priority

0 = Low priority

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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9.5 RCON Register

The RCON register contains the IPEN bit, which is

used to enable prioritized interrupts. The functions of

the other bits in this register are discussed in more

detail in Section 4.14 “RCON Register”.

R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0

IPEN ——RITO PD POR BOR

bit 7 bit 0

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16 Compatibility mode)

bit 6-5 Unimplemented: Read as ‘0’

bit 4 RI: RESET Instruction Flag bit

For details of bit operation, see Register 4-4.

bit 3 TO: Watchdog Time-out Flag bit

For details of bit operation, see Register 4-4.

bit 2 PD: Power-Down Detection Flag bit

For details of bit operation, see Register 4-4.

bit 1 POR: Power-on Reset Status bit

For details of bit operation, see Register 4-4.

bit 0 BOR: Brown-out Reset Status bit

For details of bit operation, see Register 4-4.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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9.6 INT0 Interrupt

External interrupts on the RB0/INT0, RB1/INT1,

RB2/INT2 and RB3/INT3 pins are edge-triggered:

either rising, if the corresponding INTEDGx bit is set in

the INTCON2 register, or falling, if the INTEDGx bit is

clear. When a valid edge appears on the RBx/INTx pin,

the corresponding flag bit, INTxF, is set. This interrupt

can be disabled by clearing the corresponding enable

bit, INTxE. Flag bit, INTxF, must be cleared in software

in the Interrupt Service Routine before re-enabling the

interrupt. All external interrupts (INT0, INT1, INT2 and

INT3) can wake-up the processor from Sleep if bit

INTxIE was set prior to going into Sleep. If the Global

Interrupt Enable bit, GIE, is set, the processor will

branch to the interrupt vector following wake-up.

The interrupt priority for INT, INT2 and INT3 is deter-

mined by the value contained in the interrupt priority

bits: INT1IP (INTCON3<6>), INT2IP (INTCON3<7>)

and INT3IP (INTCON2<1>). There is no priority bit

associated with INT0; it is always a high priority

interrupt source.

9.7 TMR0 Interrupt

In 8-bit mode (which is the default), an overflow in the

TMR0 register (FFh 00h) will set flag bit TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L regis-

ters (FFFFh  0000h) will set flag bit TMR0IF. The

interrupt can be enabled/disabled by setting/clearing

enable bit, TMR0IE (INTCON<5>). Interrupt priority for

Timer0 is determined by the value contained in the

interrupt priority bit, TMR0IP (INTCON2<2>). See

Section 11.0 “Timer0 Module” for further details on

the Timer0 module.

9.8 PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>).

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

9.9 Context Saving During Interrupts

During an interrupt, the return PC value is saved on the

stack. Additionally, the WREG, Status and BSR registers

are saved on the fast return stack. If a fast return from

interrupt is not used (see Section 4.3 “Fast Register

Stack”), the user may need to save the WREG, Status

and BSR registers in software. Depending on the user’s

application, other registers may also need to be saved.

Example 9-1 saves and restores the WREG, Status and

BSR registers during an Interrupt Service Routine.

EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF W_TEMP ; W_TEMP is in virtual bank

MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere

MOVFF BSR, BSR_TEMP ; BSR located anywhere

;

; USER ISR CODE

;

MOVFF BSR_TEMP, BSR ; Restore BSR

MOVF W_TEMP, W ; Restore WREG

MOVFF STATUS_TEMP, STATUS ; Restore STATUS

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10.0 I/O PORTS

Depending on the device selected, there are either

seven or nine I/O ports available on PIC18FXX20

devices. Some of their pins are multiplexed with one or

more alternate functions from the other peripheral fea-

tures on the device. In general, when a peripheral is

enabled, that pin may not be used as a general

purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRIS register (data direction register)

• PORT register (reads the levels on the pins of the

device)

• LAT register (output latch)

The Data Latch (LAT register) is useful for read-modify-

write operations on the value that the I/O pins are

driving.

A simplified version of a generic I/O port and its

operation is shown in Figure 10-1.

FIGURE 10-1: SIMPLIFIED BLOCK

DIAGRAM OF PORT/LAT/

TRIS OPERATION

10.1 PORTA, TRISA and LATA

Registers

PORTA is a 7-bit wide, bidirectional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding PORTA pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISA bit (= 0) will

make the corresponding PORTA pin an output (i.e., put

the contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch.

The Data Latch register (LATA) is also memory

mapped. Read-modify-write operations on the LATA

PORTA.

The RA4 pin is multiplexed with the Timer0 module

clock input to become the RA4/T0CKI pin. The RA4/

T0CKI pin is a Schmitt Trigger input and an open-drain

output. All other RA port pins have TTL input levels and

full CMOS output drivers.

The RA6 pin is only enabled as a general I/O pin in

ECIO and RCIO Oscillator modes.

The other PORTA pins are multiplexed with analog

inputs and the analog VREF+ and VREF- inputs. The

operation of each pin is selected by clearing/setting the

control bits in the ADCON1 register (A/D Control

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

EXAMPLE 10-1: INITIALIZING PORTA

WR LAT +

Data Latch

I/O pin

RD Port

WR Port

TRIS

RD LAT

Data Bus

Note: On a Power-on Reset, RA5 and RA3:RA0

are configured as analog inputs and read

as ‘0’. RA6 and RA4 are configured as

digital inputs.

CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches

CLRF LATA ; Alternate method

; to clear output

; data latches

MOVLW 0x0F ; Configure A/D

MOVWF ADCON1 ; for digital inputs

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISA ; Set RA<3:0> as inputs

; RA<5:4> as outputs

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FIGURE 10-2: BLOCK DIAGRAM OF

RA3:RA0 AND RA5 PINS FIGURE 10-3: BLOCK DIAGRAM OF

RA4/T0CKI PIN

FIGURE 10-4: BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O)

Data

Bus

WR LATA

WR TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

VSS

VDD

I/O pin(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

Analog

Input

Mode

TTL

Input

Buffer

To A/D Converter and LVD Modules

RD LATA

PORTA

Data

Bus

WR TRISA

RD PORTA

Data Latch

TRIS Latch

Schmitt

Trigger

Input

Buffer

VSS

I/O pin(1)

TMR0 Clock Input

RD LATA

WR LATA

PORTA

Note 1: I/O pins have protection diodes to VDD and VSS.

RD TRISA

Data Bus

WR LATA

Data Latch

TRIS Latch

RD PORTA

VSS

VDD

I/O pin(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

or PORTA

RD LATA

ECRA6 or

TTL

Input

Buffer

ECRA6 or RCRA6 Enable

RCRA6 Enable

TRISA

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TABLE 10-1: PORTA FUNCTIONS

TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/AN0 bit 0 TTL Input/output or analog input.

RA1/AN1 bit 1 TTL Input/output or analog input.

RA2/AN2/VREF- bit 2 TTL Input/output or analog input or VREF-.

RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+.

RA4/T0CKI bit 4 ST Input/output or external clock input for Timer0.

Output is open-drain type.

RA5/AN4/LVDIN bit 5 TTL Input/output or slave select input for synchronous serial port or analog

input, or Low-Voltage Detect input.

OSC2/CLKO/RA6 bit 6 TTL OSC2 or clock output, or I/O pin.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 -u0u 0000

LATA — LATA Data Output Register -xxx xxxx -uuu uuuu

TRISA — PORTA Data Direction Register -111 1111 -111 1111

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’.

Shaded cells are not used by PORTA.

WW 9 4&7 RD LATE :L: L4; ﬁ RD FORTE

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10.2 PORTB, TRISB and LATB

Registers

PORTB is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISB bit (= 0)

will make the corresponding PORTB pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

PORTB.

EXAMPLE 10-2: INITIALIZING PORTB

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit RBPU (INTCON2<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

Four of the PORTB pins (RB3:RB0) are the external

interrupt pins, INT3 through INT0. In order to use these

pins as external interrupts, the corresponding TRISB

bit must be set to ‘1’.

The other four PORTB pins (RB7:RB4) have an inter-

rupt-on-change feature. Only pins configured as inputs

can cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RB Port Change

Interrupt with Flag bit, RBIF (INTCON<0>).

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of PORTB (except with the

MOVFF instruction). This will end the mismatch

condition.

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit, RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

RB3 can be configured by the configuration bit

CCP2MX, as the alternate peripheral pin for the CCP2

module. This is only available when the device is

configured in Microprocessor, Microprocessor with

Boot Block, or Extended Microcontroller operating

modes.

The RB5 pin is used as the LVP programming pin.

When the LVP configuration bit is programmed, this pin

loses the I/O function and become a programming test

function.

FIGURE 10-5: BLOCK DIAGRAM OF

RB7:RB4 PINS

Note: On a Power-on Reset, these pins are

configured as digital inputs.

CLRF PORTB ; Initialize PORTB by

; clearing output

; data latches

CLRF LATB ; Alternate method

; to clear output

; data latches

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISB ; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Note: When LVP is enabled, the weak pull-up on

RB5 is disabled.

Data Latch

From other

RBPU(2)

VDD

I/O pin(1)

Data Bus

WR LATB

WR TRISB

Set RBIF

TRIS Latch

RD TRISB

RD PORTB

RB7:RB4 pins

Weak

Pull-up

RD PORTB

Latch

TTL

Input

Buffer ST

Buffer

RB7:RB5 in Serial Programming Mode

RD LATB

or PORTB

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (INTCON2<7>).

WW; x /\ HD Tms HD Pun H44 7 3 )7” % > RD LATE ﬂ ﬁ ﬁ j RD FORTE #3

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FIGURE 10-6: BLOCK DIAGRAM OF RB2:RB0 PINS

FIGURE 10-7: BLOCK DIAGRAM OF RB3 PIN

Data Latch

RBPU(2)

VDD

Data Bus

WR Port

WR TRIS

RD TRIS

RD Port

Weak

Pull-up

RD Port

INTx

I/O pin(1)

TTL

Input

Buffer

Schmitt Trigger

Buffer

TRIS Latch

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

Data Latch

VDD

Data Bus

WR LATB or

WR TRISB

RD TRISB

RD PORTB

Weak

Pull-up

CCP2 or INT3

TTL

Input

Buffer

Schmitt Trigger

Buffer

TRIS Latch

RD LATB

WR PORTB

RBPU(2)

Enable(3)

CCP Output

RD PORTB

CCP Output(3) 1

VDD

VSS

I/O pin(1)

CCP2MX

CCP2MX = 0

Note 1: I/O pin has diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).

3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device

is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.

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TABLE 10-3: PORTB FUNCTIONS

TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit# Buffer Function

RB0/INT0 bit 0 TTL/ST(1) Input/output pin or external interrupt input 0.

Internal software programmable weak pull-up.

RB1/INT1 bit 1 TTL/ST(1) Input/output pin or external interrupt input 1.

Internal software programmable weak pull-up.

RB2/INT2 bit 2 TTL/ST(1) Input/output pin or external interrupt input 2.

Internal software programmable weak pull-up.

RB3/INT3/CCP2(3) bit 3 TTL/ST(4) Input/output pin or external interrupt input 3. Capture2 input/Compare2

output/PWM output (when CCP2MX configuration bit is enabled, all

PIC18F8X20 operating modes except Microcontroller mode).

Internal software programmable weak pull-up.

RB4/KBI0 bit 4 TTL Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

RB5/KBI1/PGM bit 5 TTL/ST(2) Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

Low-voltage ICSP enable pin.

RB6/KBI2/PGC bit 6 TTL/ST(2) Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

Serial programming clock.

RB7/KBI3/PGD bit 7 TTL/ST(2) Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: RC1 is the alternate assignment for CCP2 when CCP2MX is not set (all operating modes except

Microcontroller mode).

4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

LATB LATB Data Output Register xxxx xxxx uuuu uuuu

TRISB PORTB Data Direction Register 1111 1111 1111 1111

INTCON GIE/

GIEH

PEIE/

GIEL

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 1111 1111

INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 1100 0000

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

: PORTC/Perwpheral om Select RD LATC F X _jji L g F

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10.3 PORTC, TRISC and LATC

Registers

PORTC is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISC bit (= 0)

will make the corresponding PORTC pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATC) is also memory

mapped. Read-modify-write operations on the LATC

PORTC.

PORTC is multiplexed with several peripheral functions

(Table 10-5). PORTC pins have Schmitt Trigger input

buffers.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an

output, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the

corresponding peripheral section for the correct TRIS

bit settings.

The pin override value is not loaded into the TRIS

RC1 is normally configured by configuration bit,

CCP2MX, as the default peripheral pin of the CCP2

module (default/erased state, CCP2MX = 1).

EXAMPLE 10-3: INITIALIZING PORTC

FIGURE 10-8: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

Note: On a Power-on Reset, these pins are

configured as digital inputs.

CLRF PORTC ; Initialize PORTC by

; clearing output

; data latches

CLRF LATC ; Alternate method

; to clear output

; data latches

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISC ; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

PORTC/Peripheral Out Select

Data Bus

WR LATC

WR TRISC

Data Latch

TRIS Latch

RD TRISC

Peripheral Data Out 0

VDD

VSS

RD PORTC

Peripheral Data In

I/O pin(1)

WR PORTC

RD LATC

Schmitt

Trigger

Note 1: I/O pins have diode protection to VDD and VSS.

2: Peripheral Output Enable is only active if Peripheral Select is active.

TRIS

Override

Peripheral Output

Logic

TRIS OVERRIDE

Pin Override Peripheral

RC0 Yes Timer1 Osc for

Timer1/Timer3

RC1 Yes Timer1 Osc for

Timer1/Timer3,

CCP2 I/O

RC2 Yes CCP1 I/O

RC3 Yes SPI/I2C

Master Clock

RC4 Yes I2C Data Out

RC5 Yes SPI Data Out

RC6 Yes USART1 Async

Xmit, Sync Clock

RC7 Yes USART1 Sync

Data Out

Enable(2)

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TABLE 10-5: PORTC FUNCTIONS

TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit# Buffer Type Function

RC0/T1OSO/T13CKI bit 0 ST Input/output port pin, Timer1 oscillator output or Timer1/Timer3

clock input.

RC1/T1OSI/CCP2(1) bit 1 ST Input/output port pin, Timer1 oscillator input or Capture2 input/

Compare2 output/PWM output (when CCP2MX configuration bit is

disabled).

RC2/CCP1 bit 2 ST Input/output port pin or Capture1 input/Compare1 output/

PWM1 output.

RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI and I2C

modes.

RC4/SDI/SDA bit 4 ST RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode).

RC5/SDO bit 5 ST Input/output port pin or synchronous serial port data output.

RC6/TX1/CK1 bit 6 ST Input/output port pin, addressable USART1 asynchronous transmit or

addressable USART1 synchronous clock.

RC7/RX1/DT1 bit 7 ST Input/output port pin, addressable USART1 asynchronous receive or

addressable USART1 synchronous data.

Legend: ST = Schmitt Trigger input

Note 1: RB3 is the alternate assignment for CCP2 when CCP2MX is set.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

LATC LATC Data Output Register xxxx xxxx uuuu uuuu

TRISC PORTC Data Direction Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged

:Di HD LATD 1 Data Bus W iv a D N HD TR‘SD :1‘ /‘ /\ \1 _L @

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10.4 PORTD, TRISD and LATD

Registers

PORTD is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISD bit (= 0)

will make the corresponding PORTD pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

PORTD.

PORTD is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually configurable as an input or

output.

PORTD is multiplexed with the system bus as the

external memory interface; I/O port functions are only

available when the system bus is disabled, by setting

the EBDIS bit in the MEMCOM register

(MEMCON<7>). When operating as the external mem-

ory interface, PORTD is the low-order byte of the

multiplexed address/data bus (AD7:AD0).

PORTD can also be configured as an 8-bit wide micro-

processor port (Parallel Slave Port) by setting control

bit PSPMODE (TRISE<4>). In this mode, the input

buffers are TTL. See Section 10.10 “Parallel Slave

Port” for additional information on the Parallel Slave

Port (PSP).

EXAMPLE 10-4: INITIALIZING PORTD

FIGURE 10-9: PORTD BLOCK DIAGRAM IN I/O PORT MODE

Note: On a Power-on Reset, these pins are

configured as digital inputs.

CLRF PORTD ; Initialize PORTD by

; clearing output

; data latches

CLRF LATD ; Alternate method

; to clear output

; data latches

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISD ; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

Data Bus

WR LATD

WR TRISD

Data Latch

TRIS Latch

RD TRISD

I/O pin(1)

RD LATD

or PORTD

VDD

VSS

RD PORTD

PSP Read

PSP Write

Note 1: I/O pins have diode protection to VDD and VSS.

TTL Buffer

Schmitt Trigger

Input Buffer

PORTD/CCP1 Select

PSPMODE

RD LATD Data Bus RD PORTD > /\ J ﬂ F RD TFHSD Instruction Read

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FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE

Instruction Register

Bus Enable

Data/TRIS Out

Drive Bus

System Bus

Control

Data Bus

WR LATD

WR TRISD

RD PORTD

Data Latch

TRIS Latch

RD TRISD

TTL

Input

Buffer

I/O pin(1)

RD LATD

or PORTD

Port

Data

Instruction Read

Note 1: I/O pins have protection diodes to VDD and VSS.

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TABLE 10-7: PORTD FUNCTIONS

TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Name Bit# Buffer Type Function

RD0/PSP0/AD0 bit 0 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0.

RD1/PSP1/AD1 bit 1 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1.

RD2/PSP2/AD2 bit 2 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 2 or address/data bus bit 2.

RD3/PSP3/AD3 bit 3 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 3 or address/data bus bit 3.

RD4/PSP4/AD4 bit 4 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 4 or address/data bus bit 4.

RD5/PSP5/AD5 bit 5 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 5 or address/data bus bit 5.

RD6/PSP6/AD6 bit 6 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 6 or address/data bus bit 6.

RD7/PSP7/AD7 bit 7 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 7 or address/data bus bit 7.

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel

Slave Port mode.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu

LATD LATD Data Output Register xxxx xxxx uuuu uuuu

TRISD PORTD Data Direction Register 1111 1111 1111 1111

PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ----

MEMCON EBDIS —WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0-00 --00

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.

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10.5 PORTE, TRISE and LATE

Registers

PORTE is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISE. Setting a

TRISE bit (= 1) will make the corresponding PORTE

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISE bit (= 0)

will make the corresponding PORTE pin an output (i.e.,

put the contents of the output latch on the selected pin).

Read-modify-write operations on the LATE register,

read and write the latched output value for PORTE.

PORTE is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually configurable as an input or

output. PORTE is multiplexed with the CCP module

(Table 10-9).

On PIC18F8X20 devices, PORTE is also multiplexed

with the system bus as the external memory interface;

the I/O bus is available only when the system bus is

disabled, by setting the EBDIS bit in the MEMCON

Microprocessor or Extended Microcontroller mode,

then the PORTE<7:0> becomes the high byte of the

address/data bus for the external program memory

interface. In Microcontroller mode, the PORTE<2:0>

pins become the control inputs for the Parallel Slave

Port when bit PSPMODE (PSPCON<4>) is set. (Refer

to Section 4.1.1 “PIC18F8X20 Program Memory

Modes” for more information on program memory

modes.)

When the Parallel Slave Port is active, three PORTE

pins (RE0/RD/AD8, RE1/WR/AD9 and RE2/CS/AD10)

function as its control inputs. This automatically occurs

when the PSPMODE bit (PSPCON<4>) is set. Users

must also make certain that bits TRISE<2:0> are set to

configure the pins as digital inputs and the ADCON1

control functions are summarized in Table 10-9.

Pin RE7 can be configured as the alternate peripheral

pin for CCP module 2 when the device is operating in

Microcontroller mode. This is done by clearing the

configuration bit, CCP2MX, in configuration register,

CONFIG3H (CONFIG3H<0>).

EXAMPLE 10-5: INITIALIZING PORTE

Note: For PIC18F8X20 (80-pin) devices operat-

ing in Extended Microcontroller mode,

PORTE defaults to the system bus on

Power-on Reset.

CLRF PORTE ; Initialize PORTE by

; clearing output

; data latches

CLRF LATE ; Alternate method

; to clear output

; data latches

MOVLW 0x03 ; Value used to

; initialize data

; direction

MOVWF TRISE ; Set RE1:RE0 as inputs

; RE7:RE2 as outputs

Perlphera‘ om Select WR TRISE x —3‘jj RD TRISE ﬂ RD LATE Data Bus RD FORTE > ﬂ A ﬂ H RD TRISE

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FIGURE 10-11: PORTE BLOCK DIAGRAM IN I/O MODE

FIGURE 10-12: PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE

Peripheral Out Select

Data Bus

WR LATE

WR TRISE

Data Latch

TRIS Latch

RD TRISE

Peripheral Data Out 0

VDD

VSS

RD PORTE

Peripheral Data In

I/O pin(1)

or WR PORTE

RD LATE

Schmitt

Trigger

Note 1: I/O pins have diode protection to VDD and VSS.

TRIS

Override

Peripheral Enable

TRIS OVERRIDE

Pin Override Peripheral

RE0 Yes External Bus

RE1 Yes External Bus

RE2 Yes External Bus

RE3 Yes External Bus

RE4 Yes External Bus

RE5 Yes External Bus

RE6 Yes External Bus

RE7 Yes External Bus

Instruction Register

Bus Enable

Data/TRIS Out

Drive Bus

System Bus

Control

Data Bus

WR LATE

WR TRISE

RD PORTE

Data Latch

TRIS Latch

RD TRISE

TTL

Input

Buffer

I/O pin(1)

RD LATE

or PORTE

Port

Data

Instruction Read

Note 1: I/O pins have protection diodes to VDD and VSS.

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TABLE 10-9: PORTE FUNCTIONS

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name Bit# Buffer Type Function

RE0/RD/AD8 bit 0 ST/TTL(1) Input/output port pin, read control for Parallel Slave Port or

address/data bit 8

For RD (PSP Control mode):

1 = Not a read operation

0 = Read operation, reads PORTD register (if chip selected)

RE1/WR/AD9 bit 1 ST/TTL(1) Input/output port pin, write control for Parallel Slave Port or

address/data bit 9

For WR (PSP Control mode):

1 = Not a write operation

0 = Write operation, writes PORTD register (if chip selected)

RE2/CS/AD10 bit 2 ST/TTL(1) Input/output port pin, chip select control for Parallel Slave Port or

address/data bit 10

For CS (PSP Control mode):

1 = Device is not selected

0 = Device is selected

RE3/AD11 bit 3 ST/TTL(1) Input/output port pin or address/data bit 11.

RE4/AD12 bit 4 ST/TTL(1) Input/output port pin or address/data bit 12.

RE5/AD13 bit 5 ST/TTL(1) Input/output port pin or address/data bit 13.

RE6/AD14 bit 6 ST/TTL(1) Input/output port pin or address/data bit 14.

RE7/CCP2/AD15 bit 7 ST/TTL(1) Input/output port pin, Capture2 input/Compare2 output/PWM output

(PIC18F8X20 devices in Microcontroller mode only) or

address/data bit 15.

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O or CCP mode and TTL buffers when in System Bus or PSP

Control mode.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

TRISE PORTE Data Direction Control Register 1111 1111 1111 1111

PORTE Read PORTE pin/Write PORTE Data Latch xxxx xxxx uuuu uuuu

LATE Read PORTE Data Latch/Write PORTE Data Latch xxxx xxxx uuuu uuuu

MEMCON EBDIS —WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0000 --00

PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ----

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTE.

«M

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10.6 PORTF, LATF and TRISF Registers

PORTF is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISF. Setting a

TRISF bit (= 1) will make the corresponding PORTF pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISF bit (= 0) will

make the corresponding PORTF pin an output (i.e., put

the contents of the output latch on the selected pin).

Read-modify-write operations on the LATF register,

read and write the latched output value for PORTF.

PORTF is multiplexed with several analog peripheral

functions, including the A/D converter inputs and

comparator inputs, outputs and voltage reference.

EXAMPLE 10-6: INITIALIZING PORTF

FIGURE 10-13: PORTF RF1/AN6/C2OUT, RF2/AN7/C1OUT PINS BLOCK DIAGRAM

Note 1: On a Power-on Reset, the RF6:RF0 pins

are configured as inputs and read as ‘0’.

2: To configure PORTF as digital I/O, turn off

comparators and set ADCON1 value.

CLRF PORTF ; Initialize PORTF by

; clearing output

; data latches

CLRF LATF ; Alternate method

; to clear output

; data latches

MOVLW 0x07 ;

MOVWF CMCON ; Turn off comparators

MOVLW 0x0F ;

MOVWF ADCON1 ; Set PORTF as digital I/O

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISF ; Set RF3:RF0 as inputs

; RF5:RF4 as outputs

; RF7:RF6 as inputs

Port/Comparator Select

Data Bus

WR LATF

WR TRISF

Data Latch

TRIS Latch

RD TRISF

Comparator Data Out 0

VDD

VSS

RD PORTF

I/O pin

WR PORTF

RD LATF

Schmitt

Trigger

Note 1: I/O pins have diode protection to VDD and VSS.

Analog

Input

Mode

To A/D Converter

RD LATF RD TRISF $7 w Bus W; R ﬂ ﬂ /\ RD PDHTF >

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FIGURE 10-14: RF6:RF3 AND RF0 PINS

BLOCK DIAGRAM FIGURE 10-15: RF7 PIN BLOCK

DIAGRAM

Data

Bus

WR LATF

WR TRISF

Data Latch

TRIS Latch

RD TRISF

RD PORTF

VSS

VDD

I/O pin

Analog

Input

Mode

Input

Buffer

To A/D Converter or Comparator Input

RD LATF

WR PORTF

Note 1: I/O pins have diode protection to VDD and VSS.

Data

Bus

WR LATF

WR TRISF

RD PORTF

Data Latch

TRIS Latch

RD TRISF

Schmitt

Trigger

Input

Buffer

I/O pin

RD LATF

WR PORTF

Note: I/O pins have diode protection to VDD and VSS.

TTL

Input

Buffer

SS Input

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TABLE 10-11: PORTF FUNCTIONS

TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF

Name Bit# Buffer Type Function

RF0/AN5 bit 0 ST Input/output port pin or analog input.

RF1/AN6/C2OUT bit 1 ST Input/output port pin, analog input or comparator 2 output.

RF2/AN7/C1OUT bit 2 ST Input/output port pin, analog input or comparator 1 output.

RF3/AN8 bit 3 ST Input/output port pin or analog input/comparator input.

RF4/AN9 bit 4 ST Input/output port pin or analog input/comparator input.

RF5/AN10/CVREF bit 5 ST Input/output port pin, analog input/comparator input or

comparator reference output.

RF6/AN11 bit 6 ST Input/output port pin or analog input/comparator input.

RF7/SS bit 7 ST/TTL Input/output port pin or slave select pin for synchronous serial port.

Legend: ST = Schmitt Trigger input, TTL = TTL input

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

TRISF PORTF Data Direction Control Register 1111 1111 1111 1111

PORTF Read PORTF pin/Write PORTF Data Latch xxxx xxxx uuuu uuuu

LATF Read PORTF Data Latch/Write PORTF Data Latch 0000 0000 uuuu uuuu

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTF.

PORTGJPenpheral Out Se‘ed RD LATG X N F n ﬂ] % E T

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10.7 PORTG, TRISG and LATG

Registers

PORTG is a 5-bit wide, bidirectional port. The corre-

sponding data direction register is TRISG. Setting a

TRISG bit (= 1) will make the corresponding PORTG

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISG bit (= 0)

will make the corresponding PORTC pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATG) is also memory

mapped. Read-modify-write operations on the LATG

PORTG.

PORTG is multiplexed with both CCP and USART

functions (Table 10-13). PORTG pins have Schmitt

Trigger input buffers.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTG pin. Some

peripherals override the TRIS bit to make a pin an

output, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the

corresponding peripheral section for the correct TRIS

bit settings.

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register,

without concern due to peripheral overrides.

EXAMPLE 10-7: INITIALIZING PORTG

FIGURE 10-16: PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

Note: On a Power-on Reset, these pins are

configured as digital inputs.

CLRF PORTG ; Initialize PORTG by

; clearing output

; data latches

CLRF LATG ; Alternate method

; to clear output

; data latches

MOVLW 0x04 ; Value used to

; initialize data

; direction

MOVWF TRISG ; Set RG1:RG0 as outputs

; RG2 as input

; RG4:RG3 as inputs

PORTG/Peripheral Out Select

Data Bus

WR LATG

WR TRISG

Data Latch

TRIS Latch

RD TRISG

Peripheral Data Out 0

VDD

VSS

RD PORTG

Peripheral Data In

I/O pin(1)

WR PORTG

RD LATG

Schmitt

Trigger

Note 1: I/O pins have diode protection to VDD and VSS.

2: Peripheral Output Enable is only active if Peripheral Select is active.

TRIS

Override

Peripheral Output

Logic

TRIS OVERRIDE

Pin Override Peripheral

RG0 Yes CCP3 I/O

RG1 Yes USART1 Async

Xmit, Sync Clock

RG2 Yes USART1 Async

Rcv, Sync Data

Out

RG3 Yes CCP4 I/O

RG4 Yes CCP5 I/O

Enable(2)

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TABLE 10-13: PORTG FUNCTIONS

TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG

Name Bit# Buffer Type Function

RG0/CCP3 bit 0 ST Input/output port pin or Capture3 input/Compare3 output/PWM3 output.

RG1/TX2/CK2 bit 1 ST Input/output port pin, addressable USART2 asynchronous transmit or

addressable USART2 synchronous clock.

RG2/RX2/DT2 bit 2 ST Input/output port pin, addressable USART2 asynchronous receive or

addressable USART2 synchronous data.

RG3/CCP4 bit 3 ST Input/output port pin or Capture4 input/Compare4 output/PWM4 output.

RG4/CCP5 bit 4 ST Input/output port pin or Capture5 input/Compare5 output/PWM5 output.

Legend: ST = Schmitt Trigger input

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

PORTG — — — Read PORTF pin/Write PORTF Data Latch ---x xxxx ---u uuuu

LATG — — — LATG Data Output Register ---x xxxx ---u uuuu

TRISG — — — Data Direction Control Register for PORTG ---1 1111 ---1 1111

Legend: x = unknown, u = unchanged

: i3 1 E 7% x 7%; $7 74$ JD; 7 R X RD TRISH /\ J ﬂ 7%; /\ A /\

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10.8 PORTH, LATH and TRISH

Registers

PORTH is an 8-bit wide, bidirectional I/O port. The cor-

responding data direction register is TRISH. Setting a

TRISH bit (= 1) will make the corresponding PORTH

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISH bit (= 0)

will make the corresponding PORTH pin an output (i.e.,

put the contents of the output latch on the selected pin).

Read-modify-write operations on the LATH register,

read and write the latched output value for PORTH.

Pins RH7:RH4 are multiplexed with analog inputs

AN15:AN12. Pins RH3:RH0 are multiplexed with the

system bus as the external memory interface; they are

the high-order address bits, A19:A16. By default, pins

RH7:RH4 are enabled as A/D inputs and pins

RH3:RH0 are enabled as the system address bus.

inputs. Register MEMCON configures RH3:RH0 as I/O

or system bus pins.

EXAMPLE 10-8: INITIALIZING PORTH

FIGURE 10-17: RH3:RH0 PINS BLOCK

DIAGRAM IN I/O MODE

FIGURE 10-18: RH7:RH4 PINS BLOCK

DIAGRAM IN I/O MODE

Note: PORTH is available only on PIC18F8X20

devices.

Note 1: On Power-on Reset, PORTH pins

RH7:RH4 default to A/D inputs and read

as ‘0’.

2: On Power-on Reset, PORTH pins

RH3:RH0 default to system bus signals.

CLRF PORTH ; Initialize PORTH by

; clearing output

; data latches

CLRF LATH ; Alternate method

; to clear output

; data latches

MOVLW 0Fh ;

MOVWF ADCON1 ;

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISH ; Set RH3:RH0 as inputs

; RH5:RH4 as outputs

; RH7:RH6 as inputs

Data

Bus

WR LATH

WR TRISH

RD PORTH

Data Latch

TRIS Latch

RD TRISH

Schmitt

Trigger

Input

Buffer

I/O pin(1)

RD LATH

PORTH

Note 1: I/O pins have diode protection to VDD and VSS.

Data

Bus

WR LATH

WR TRISH

RD PORTH

Data Latch

TRIS Latch

RD TRISH

Schmitt

Trigger

Input

Buffer

I/O pin(1)

RD LATH

PORTH

To A/D Converter

Note 1: I/O pins have diode protection to VDD and VSS.

RD FORTH D /\ J

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FIGURE 10-19: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE

To Instruction Register

External Enable

Address Out

Drive System

System Bus

Control

Data Bus

WR LATH

WR TRISH

RD PORTH

Data Latch

TRIS Latch

RD TRISH

TTL

Input

Buffer

I/O pin(1)

RD LATD

PORTH

Port

Data

Instruction Read

Note 1: I/O pins have diode protection to VDD and VSS.

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TABLE 10-15: PORTH FUNCTIONS

TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH

Name Bit# Buffer Type Function

RH0/A16 bit 0 ST/TTL(1) Input/output port pin or address bit 16 for external memory interface.

RH1/A17 bit 1 ST/TTL(1) Input/output port pin or address bit 17 for external memory interface.

RH2/A18 bit 2 ST/TTL(1) Input/output port pin or address bit 18 for external memory interface.

RH3/A19 bit 3 ST/TTL(1) Input/output port pin or address bit 19 for external memory interface.

RH4/AN12 bit 4 ST Input/output port pin or analog input channel 12.

RH5/AN13 bit 5 ST Input/output port pin or analog input channel 13.

RH6/AN14 bit 6 ST Input/output port pin or analog input channel 14.

RH7/AN15 bit 7 ST Input/output port pin or analog input channel 15.

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel

Slave Port mode.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

TRISH PORTH Data Direction Control Register 1111 1111 1111 1111

PORTH Read PORTH pin/Write PORTH Data Latch xxxx xxxx uuuu uuuu

LATH Read PORTH Data Latch/Write PORTH Data Latch xxxx xxxx uuuu uuuu

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000

MEMCON EBDIS —WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0-00 --00

Legend: x = unknown, u = unchanged, – = unimplemented. Shaded cells are not used by PORTH.

RD TRISJ :7

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10.9 PORTJ, TRISJ and LATJ

Registers

PORTJ is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISJ. Setting a

TRISJ bit (= 1) will make the corresponding PORTJ pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISJ bit (= 0) will

make the corresponding PORTJ pin an output (i.e., put

the contents of the output latch on the selected pin).

The Data Latch register (LATJ) is also memory

mapped. Read-modify-write operations on the LATJ

PORTJ.

PORTJ is multiplexed with the system bus as the exter-

nal memory interface; I/O port functions are only avail-

able when the system bus is disabled. When operating

as the external memory interface, PORTJ provides the

control signal to external memory devices. The RJ5 pin

is not multiplexed with any system bus functions.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTJ pin. Some

peripherals override the TRIS bit to make a pin an

output, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the corre-

sponding peripheral section for the correct TRIS bit

settings.

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register,

without concern due to peripheral overrides.

EXAMPLE 10-9: INITIALIZING PORTJ

FIGURE 10-20: PORTJ BLOCK DIAGRAM

IN I/O MODE

Note: PORTJ is available only on PIC18F8X20

devices.

Note: On a Power-on Reset, these pins are

configured as digital inputs.

CLRF PORTJ ; Initialize PORTG by

; clearing output

; data latches

CLRF LATJ ; Alternate method

; to clear output

; data latches

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISJ ; Set RJ3:RJ0 as inputs

; RJ5:RJ4 as output

; RJ7:RJ6 as inputs

Data

Bus

WR LATJ

WR TRISJ

RD PORTJ

Data Latch

TRIS Latch

RD TRISJ

Schmitt

Trigger

Input

Buffer

I/O pin(1)

RD LATJ

PORTJ

Note 1: I/O pins have diode protection to VDD and VSS.

RD PORTJ RD LATJ RD TRISJ \ ﬁt: .7 ‘ ﬂ [A RD PORTJ RD LATJ Data Bus WR LATJ RD TRISJ W 59:2: [A

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FIGURE 10-21: RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE

FIGURE 10-22: RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE

External Enable

Control Out

Drive System

System Bus

Control

Data Bus

WR LATJ

WR TRISJ

RD PORTJ

Data Latch

TRIS Latch

RD TRISJ

I/O pin(1)

RD LATJ

PORTJ

Port

Data

Note 1: I/O pins have diode protection to VDD and VSS.

WM = 01

UB/LB Out

Drive System

System Bus

Control

Data Bus

WR LATJ

WR TRISJ

RD PORTJ

Data Latch

TRIS Latch

RD TRISJ

I/O pin(1)

RD LATJ

PORTJ

Port

Data

Note 1: I/O pins have diode protection to VDD and VSS.

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TABLE 10-17: PORTJ FUNCTIONS

TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ

Name Bit# Buffer Type Function

RJ0/ALE bit 0 ST Input/output port pin or address latch enable control for external memory

interface.

RJ1/OE bit 1 ST Input/output port pin or output enable control for external memory interface.

RJ2/WRL bit 2 ST Input/output port pin or write low byte control for external memory interface.

RJ3/WRH bit 3 ST Input/output port pin or write high byte control for external memory interface.

RJ4/BA0 bit 4 ST Input/output port pin or byte address 0 control for external memory interface.

RJ5/CE bit 5 ST Input/output port pin or chip enable control for external memory interface.

RJ6/LB bit 6 ST Input/output port pin or lower byte select control for external memory

interface.

RJ7/UB bit 7 ST Input/output port pin or upper byte select control for external memory

interface.

Legend: ST = Schmitt Trigger input

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

PORTJ Read PORTJ pin/Write PORTJ Data Latch xxxx xxxx uuuu uuuu

LATJ LATJ Data Output Register xxxx xxxx uuuu uuuu

TRISJ Data Direction Control Register for PORTJ 1111 1111 1111 1111

Legend: x = unknown, u = unchanged

||||||||||||| |||||||||||||

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10.10 Parallel Slave Port

PORTD also operates as an 8-bit wide Parallel Slave

Port, or microprocessor port, when control bit

PSPMODE (PSPCON<4>) is set. It is asynchronously

readable and writable by the external world through the

RD control input pin, RE0/RD/AD8 and the WR control

input pin, RE1/WR/AD9.

The PSP can directly interface to an 8-bit micro-

processor data bus. The external microprocessor can

read or write the PORTD latch as an 8-bit latch. Setting

bit PSPMODE enables port pin RE0/RD/AD8 to be the

RD input, RE1/WR/AD9 to be the WR input and RE2/

CS/AD10 to be the CS (Chip Select) input. For this

functionality, the corresponding data direction bits of

the TRISE register (TRISE<2:0>) must be configured

as inputs (set). The A/D port configuration bits,

PCFG2:PCFG0 (ADCON1<2:0>), must be set which

will configure pins RE2:RE0 as digital I/O.

A write to the PSP occurs when both the CS and WR

lines are first detected low. A read from the PSP occurs

when both the CS and RD lines are first detected low.

The PORTE I/O pins become control inputs for the

microprocessor port when bit PSPMODE

(PSPCON<4>) is set. In this mode, the user must make

sure that the TRISE<2:0> bits are set (pins are config-

ured as digital inputs) and the ADCON1 is configured

for digital I/O. In this mode, the input buffers are TTL.

FIGURE 10-23: PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE PORT)

Note: For PIC18F8X20 devices, the Parallel

Slave Port is available only in

Microcontroller mode.

Data Bus

WR LATD RDx

RD PORTD

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR1<7>)

Read

Chip Select

Write

Note: I/O pin has protection diodes to VDD and VSS.

TTL

PORTD

RD LATD

Data Latch

TRIS Latch

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FIGURE 10-24: PARALLEL SLAVE PORT WRITE WAVEFORMS

R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0

IBF OBF IBOV PSPMODE — — — —

bit 7 bit 0

bit 7 IBF: Input Buffer Full Status bit

1 = A word has been received and is waiting to be read by the CPU

0 = No word has been received

bit 6 OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word

0 = The output buffer has been read

bit 5 IBOV: Input Buffer Overflow Detect bit

1 = A write occurred when a previously input word has not been read

(must be cleared in software)

0 = No overflow occurred

bit 4 PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel Slave Port mode

0 = General Purpose I/O mode

bit 3-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

OBF

PSPIF

PORTD<7:0>

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FIGURE 10-25: PARALLEL SLAVE PORT READ WAVEFORMS

TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

PSPIF

OBF

PORTD<7:0>

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu

LATD LATD Data Output bits xxxx xxxx uuuu uuuu

TRISD PORTD Data Direction bits 1111 1111 1111 1111

PORTE — — — — — Read PORTE pin/

Write PORTE Data Latch

0000 0000 0000 0000

LATE — — — — — LATE Data Output bits xxxx xxxx uuuu uuuu

TRISE — — — — — PORTE Data Direction bits 1111 1111 1111 1111

PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ----

INTCON GIE/

GIEH

PEIE/

GIEL

TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.

Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.

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11.0 TIMER0 MODULE

The Timer0 module has the following features:

• Software selectable as an 8-bit or

16-bit timer/counter

• Readable and writable

• Dedicated 8-bit software programmable prescaler

• Clock source selectable to be external or internal

• Interrupt-on-overflow from FFh to 00h in 8-bit

mode and FFFFh to 0000h in 16-bit mode

• Edge select for external clock

Figure 11-1 shows a simplified block diagram of the

Timer0 module in 8-bit mode and Figure 11-2 shows a

simplified block diagram of the Timer0 module in 16-bit

mode.

The T0CON register (Register 11-1) is a readable and

writable register that controls all the aspects of Timer0,

including the prescale selection.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0

bit 7 bit 0

bit 7 TMR0ON: Timer0 On/Off Control bit

1 = Enables Timer0

0 = Stops Timer0

bit 6 T08BIT: Timer0 8-bit/16-bit Control bit

1 = Timer0 is configured as an 8-bit timer/counter

0 = Timer0 is configured as a 16-bit timer/counter

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKO)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Timer0 Prescaler Assignment bit

1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.

0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits

111 = 1:256 prescale value

110 = 1:128 prescale value

101 = 1:64 prescale value

100 = 1:32 prescale value

011 = 1:16 prescale value

010 = 1:8 prescale value

001 = 1:4 prescale value

000 = 1:2 prescale value

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE

FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

RA4/T0CKI pin

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks TMR0

(2 TCY delay)

Data Bus

PSA

T0PS2, T0PS1, T0PS0 Set Interrupt

Flag bit TMR0IF

on Overflow

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

RA4/T0CKI

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks TMR0L

(2 TCY delay)

Data Bus<7:0>

PSA

T0PS2, T0PS1, T0PS0

Set Interrupt

Flag bit TMR0IF

on Overflow

TMR0

TMR0H

High Byte

Read TMR0L

Write TMR0L

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11.1 Timer0 Operation

Timer0 can operate as a timer or as a counter.

Timer mode is selected by clearing the T0CS bit. In

Timer mode, the Timer0 module will increment every

instruction cycle (without prescaler). If the TMR0 regis-

ter is written, the increment is inhibited for the following

two instruction cycles. The user can work around this

by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting the T0CS bit. In

Counter mode, Timer0 will increment, either on every

rising or falling edge of pin RA4/T0CKI. The increment-

ing edge is determined by the Timer0 Source Edge

Select bit (T0SE). Clearing the T0SE bit selects the

rising edge. Restrictions on the external clock input are

discussed below.

When an external clock input is used for Timer0, it must

meet certain requirements. The requirements ensure

the external clock can be synchronized with the internal

phase clock (TOSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

11.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0

module. The prescaler is not readable or writable.

The PSA and T0PS2:T0PS0 bits determine the

prescaler assignment and prescale ratio.

Clearing bit PSA will assign the prescaler to the Timer0

module. When the prescaler is assigned to the Timer0

module, prescale values of 1:2, 1:4, ..., 1:256 are

selectable.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF TMR0, MOVWF

TMR0, BSF TMR0, x, ..., etc.) will clear the prescaler

count.

11.2.1 SWITCHING PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

control, (i.e., it can be changed “on-the-fly” during

program execution).

11.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0

FFFFh to 0000h in 16-bit mode. This overflow sets the

TMR0IF bit. The interrupt can be masked by clearing

the TMR0IE bit. The TMR0IF bit must be cleared in

software by the Timer0 module Interrupt Service

Routine before re-enabling this interrupt. The TMR0

interrupt cannot awaken the processor from Sleep,

since the timer is shut-off during Sleep.

11.4 16-Bit Mode Timer Reads

and Writes

TMR0H is not the high byte of the timer/counter in

16-bit mode, but is actually a buffered version of the

high byte of Timer0 (refer to Figure 11-2). The high byte

of the Timer0 counter/timer is not directly readable nor

writable. TMR0H is updated with the contents of the

high byte of Timer0 during a read of TMR0L. This pro-

vides the ability to read all 16 bits of Timer0 without

having to verify that the read of the high and low byte

were valid, due to a rollover between successive reads

of the high and low byte.

A write to the high byte of Timer0 must also take place

through the TMR0H Buffer register. Timer0 high byte is

updated with the contents of TMR0H when a write

occurs to TMR0L. This allows all 16 bits of Timer0 to be

updated at once.

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

Note: Writing to TMR0 when the prescaler is

assigned to Timer0, will clear the

prescaler count, but will not change the

prescaler assignment.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

TMR0L Timer0 Module Low Byte Register xxxx xxxx uuuu uuuu

TMR0H Timer0 Module High Byte Register 0000 0000 0000 0000

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111

TRISA — PORTA Data Direction Register -111 1111 -111 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations, read as ‘0’.

Shaded cells are not used by Timer0.

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NOTES:

When TMRTCS : 1. When TMRTCS : El.

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12.0 TIMER1 MODULE

The Timer1 module timer/counter has the following

features:

• 16-bit timer/counter

(two 8-bit registers: TMR1H and TMR1L)

• Readable and writable (both registers)

• Internal or external clock select

• Interrupt-on-overflow from FFFFh to 0000h

• Reset from CCP module special event trigger

Figure 12-1 is a simplified block diagram of the Timer1

module.

module and contains the Timer1 Oscillator Enable bit

(T1OSCEN). Timer1 can be enabled or disabled by

setting or clearing control bit, TMR1ON (T1CON<0>).

Timer1 can also be used to provide Real-Time Clock

(RTC) functionality to applications, with only a minimal

addition of external components and code overhead.

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

bit 7 RD16: 16-bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer1 in one 16-bit operation

0 = Enables register read/write of Timer1 in two 8-bit operations

bit 6 Unimplemented: Read as ‘0’

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1OSCEN: Timer1 Oscillator Enable bit

1 = Timer1 oscillator is enabled

0 = Timer1 oscillator is shut off

The oscillator inverter and feedback resistor are turned off to eliminate power drain.

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit

When TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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12.1 Timer1 Operation

Timer1 can operate in one of these modes:

•As a timer

• As a synchronous counter

• As an asynchronous counter

The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>).

When TMR1CS = 0, Timer1 increments every instruc-

tion cycle. When TMR1CS = 1, Timer1 increments on

every rising edge of the external clock input or the

Timer1 oscillator, if enabled.

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins

become inputs. That is, the TRISC<1:0> value is

ignored and the pins are read as ‘0’.

Timer1 also has an internal “Reset input”. This

Reset can be generated by the CCP module

(see Section 16.0 “Capture/Compare/PWM (CCP)

Modules”).

FIGURE 12-1: TIMER1 BLOCK DIAGRAM

FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE

TMR1H TMR1L

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0 Sleep Input

FOSC/4

Internal

Clock

TMR1ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

TMR1IF

Overflow TMR1

CLR

CCP Special Event Trigger

T1OSCEN

Enable

Oscillator(1)

T1OSC

Interrupt

Flag Bit

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

T1OSI

T1OSO/T13CKI

Timer 1 TMR1L

T1OSC T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

Sleep Input

T1OSCEN

Enable

Oscillator(1)

TMR1IF

Overflow

Interrupt

FOSC/4

Internal

Clock

TMR1ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

T1OSO/T13CKI

T1OSI

TMR1

Flag bit

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

High Byte

Data Bus<7:0>

TMR1H

Read TMR1L

Write TMR1L

CLR

CCP Special Event Trigger

o 0% w% 0

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12.2 Timer1 Oscillator

A crystal oscillator circuit is built-in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit, T1OSCEN (T1CON<3>). The oscil-

lator is a low-power oscillator, rated up to 200 kHz. It

will continue to run during Sleep. It is primarily intended

for a 32 kHz crystal. The circuit for a typical LP oscilla-

tor is shown in Figure 12-3. Table 12-1 shows the

capacitor selection for the Timer1 oscillator.

The user must provide a software time delay to ensure

proper start-up of the Timer1 oscillator

FIGURE 12-3: EXTERNAL

COMPONENTS FOR THE

TIMER1 LP OSCILLATOR

12.2.1 LOW-POWER TIMER1 OPTION

(PIC18FX520 DEVICES ONLY)

The Timer1 oscillator for PIC18LFX520 devices incor-

porates a low-power feature, which allows the oscillator

to automatically reduce its power consumption when

the microcontroller is in Sleep mode.

As high noise environments may cause excessive

oscillator instability in Sleep mode, this option is best

suited for low noise applications where power

conservation is an important design consideration. Due

to the low-power nature of the oscillator, it may also be

sensitive to rapidly changing signals in close proximity.

The oscillator circuit, shown in Figure 12-3, should be

located as close as possible to the microcontroller.

There should be no circuits passing within the oscillator

circuit boundaries other than VSS or VDD.

If a high-speed circuit must be located near the oscilla-

tor (such as the CCP1 pin in output compare or PWM

mode, or the primary oscillator using the OSC2 pin), a

grounded guard ring around the oscillator circuit, as

shown in Figure 12-4, may be helpful when used on a

single-sided PCB or in addition to a ground plane.

FIGURE 12-4: OSCILLATOR CIRCUIT

WITH GROUNDED

GUARD RING

TABLE 12-1: CAPACITOR SELECTION

FOR THE ALTERNATE

OSCILLATOR

Osc Type Freq C1 C2

LP 32 kHz TBD(1) TBD(1)

Crystal to be Tested:

32.768 kHz Epson C-001R32.768K-A  20 PPM

Note 1: Microchip suggests 33 pF as a starting

point in validating the oscillator circuit.

2: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

4: Capacitor values are for design guidance

only.

Note: See the Notes with Table 12-1 for additional

information about capacitor selection.

XTAL

PIC18FXX20

T1OSI

T1OSO

32.768 kHz

33 pF

Note: PIC18FX620/X720 devices have the

standard Timer1 oscillator permanently

selected. PIC18LFX620/X720 devices

have the low-power Timer1 oscillator

permanently selected.

VDD

OSC1

VSS

OSC2

RC0

RC1

RC2

Note: Not drawn to scale.

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12.3 Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR1 interrupt, if enabled, is generated on overflow,

which is latched in interrupt flag bit, TMR1IF

(PIR1<0>). This interrupt can be enabled/disabled by

setting/clearing TMR1 Interrupt Enable bit, TMR1IE

(PIE1<0>).

12.4 Resetting Timer1 Using a CCP

Trigger Output

If the CCP module is configured in Compare mode

to generate a “special event trigger”

(CCP1M3:CCP1M0 = 1011), this signal will reset

Timer1 and start an A/D conversion (if the A/D module

is enabled).

Timer1 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

special event trigger from CCP1, the write will take

precedence.

In this mode of operation, the CCPR1H:CCPR1L

Timer1.

12.5 Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes

(see Figure 12-2). When the RD16 control bit

(T1CON<7>) is set, the address for TMR1H is mapped

to a buffer register for the high byte of Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 high byte buffer. This provides

the user with the ability to accurately read all 16 bits of

Timer1 without having to determine whether a read of

the high byte, followed by a read of the low byte, is

valid, due to a rollover between reads.

A write to the high byte of Timer1 must also take place

through the TMR1H Buffer register. Timer1 high byte is

updated with the contents of TMR1H when a write

occurs to TMR1L. This allows a user to write all 16 bits

to both the high and low bytes of Timer1 at once.

The high byte of Timer1 is not directly readable or writ-

able in this mode. All reads and writes must take place

through the Timer1 High Byte Buffer register. Writes to

TMR1H do not clear the Timer1 prescaler. The

prescaler is only cleared on writes to TMR1L.

12.6 Using Timer1 as a

Real-Time Clock

Adding an external LP oscillator to Timer1 (such as the

one described in Section 12.2 “Timer1 Oscillator”)

gives users the option to include RTC functionality to

their applications. This is accomplished with an inex-

pensive watch crystal to provide an accurate time base

and several lines of application code to calculate the

time. When operating in Sleep mode and using a

battery or supercapacitor as a power source, it can

completely eliminate the need for a separate RTC

device and battery backup.

The application code routine, RTCisr, shown in

Example 12-1, demonstrates a simple method to incre-

ment a counter at one-second intervals using an

Interrupt Service Routine. Incrementing the TMR1

the routine, which increments the seconds counter by

one; additional counters for minutes and hours are

incremented as the previous counter overflow.

Since the register pair is 16 bits wide, counting up to

overflow the register directly from a 32.768 kHz clock

would take 2 seconds. To force the overflow at the

required one-second intervals, it is necessary to

preload it; the simplest method is to set the MSb of

TMR1H with a BSF instruction. Note that the TMR1L

introduce cumulative error over many cycles.

For this method to be accurate, Timer1 must operate in

Asynchronous mode and the Timer1 overflow interrupt

must be enabled (PIE1<0> = 1), as shown in the

routine, RTCinit. The Timer1 oscillator must also be

enabled and running at all times.

Note: The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

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EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE

TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

RTCinit

MOVLW 0x80 ; Preload TMR1 register pair

MOVWF TMR1H ; for 1 second overflow

CLRF TMR1L

MOVLW b’00001111’ ; Configure for external clock,

MOVWF T1OSC ; Asynchronous operation, external oscillator

CLRF secs ; Initialize timekeeping registers

CLRF mins ;

MOVLW .12

MOVWF hours

BSF PIE1, TMR1IE ; Enable Timer1 interrupt

RETURN

RTCisr

BSF TMR1H, 7 ; Preload for 1 sec overflow

BCF PIR1, TMR1IF ; Clear interrupt flag

INCF secs, F ; Increment seconds

MOVLW .59 ; 60 seconds elapsed?

CPFSGT secs

RETURN ; No, done

CLRF secs ; Clear seconds

INCF mins, F ; Increment minutes

MOVLW .59 ; 60 minutes elapsed?

CPFSGT mins

RETURN ; No, done

CLRF mins ; clear minutes

INCF hours, F ; Increment hours

MOVLW .23 ; 24 hours elapsed?

CPFSGT hours

RETURN ; No, done

MOVLW .01 ; Reset hours to 1

MOVWF hours

RETURN ; Done

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

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NOTES:

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13.0 TIMER2 MODULE

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match of PR2

• SSP module optional use of TMR2 output to

generate clock shift

Timer2 has a control register shown in Register 13-1.

Timer2 can be shut-off by clearing control bit, TMR2ON

(T2CON<2>), to minimize power consumption.

Figure 13-1 is a simplified block diagram of the Timer2

module. Register 13-1 shows the Timer2 Control regis-

ter. The prescaler and postscaler selection of Timer2

are controlled by this register.

13.1 Timer2 Operation

Timer2 can be used as the PWM time base for the

PWM mode of the CCP module. The TMR2 register is

readable and writable and is cleared on any device

Reset. The input clock (FOSC/4) has a prescale option

of 1:1, 1:4 or 1:16, selected by control bits,

T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-

put of TMR2 goes through a 4-bit postscaler (which

gives a 1:1 to 1:16 scaling inclusive) to generate a

TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)).

The prescaler and postscaler counters are cleared

when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

•

1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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13.2 Timer2 Interrupt

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to FFh upon Reset.

13.3 Output of TMR2

The output of TMR2 (before the postscaler) is fed to the

synchronous serial port module, which optionally uses

it to generate the shift clock.

FIGURE 13-1: TIMER2 BLOCK DIAGRAM

TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111

TMR2 Timer2 Module Register 0000 0000 0000 0000

T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

PR2 Timer2 Period Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

Comparator

TMR2 Sets Flag

TMR2

Output(1)

Reset

Postscaler

Prescaler

PR2

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

bit TMR2IF

Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.

T2OUTPS3:T2OUTPS0

T2CKPS1:T2CKPS0

When TMRSCS : 1. When TMRSCS : El.

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14.0 TIMER3 MODULE

The Timer3 module timer/counter has the following

features:

• 16-bit timer/counter

(two 8-bit registers; TMR3H and TMR3L)

• Readable and writable (both registers)

• Internal or external clock select

• Interrupt-on-overflow from FFFFh to 0000h

• Reset from CCP module trigger

Figure 14-1 is a simplified block diagram of the Timer3

module.

module and sets the CCP clock source.

module, as well as contains the Timer1 Oscillator

Enable bit (T1OSCEN), which can be a clock source for

Timer3.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

bit 7 bit 0

bit 7 RD16: 16-bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer3 in one 16-bit operation

0 = Enables register read/write of Timer3 in two 8-bit operations

bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits

11 = Timer3 and Timer4 are the clock sources for CCP1 through CCP5

10 = Timer3 and Timer4 are the clock sources for CCP3 through CCP5;

Timer1 and Timer2 are the clock sources for CCP1 and CCP2

01 = Timer3 and Timer4 are the clock sources for CCP2 through CCP5;

Timer1 and Timer2 are the clock sources for CCP1

00 = Timer1 and Timer2 are the clock sources for CCP1 through CCP5

bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit

(Not usable if the system clock comes from Timer1/Timer3.)

When TMR3CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR3CS = 0:

This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1 TMR3CS: Timer3 Clock Source Select bit

1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the

first falling edge)

0 = Internal clock (FOSC/4)

bit 0 TMR3ON: Timer3 On bit

1 = Enables Timer3

0 = Stops Timer3

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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14.1 Timer3 Operation

Timer3 can operate in one of these modes:

•As a timer

• As a synchronous counter

• As an asynchronous counter

The operating mode is determined by the clock select

bit, TMR3CS (T3CON<1>).

When TMR3CS = 0, Timer3 increments every instruc-

tion cycle. When TMR3CS = 1, Timer3 increments on

every rising edge of the Timer1 external clock input or

the Timer1 oscillator, if enabled.

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins

become inputs. That is, the TRISC<1:0> value is

ignored and the pins are read as ‘0’.

Timer3 also has an internal “Reset input”. This Reset

can be generated by the CCP module (see Section 14.0

“Timer3 Module”).

FIGURE 14-1: TIMER3 BLOCK DIAGRAM

FIGURE 14-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE

TMR3H TMR3L

T1OSC

T3SYNC

TMR3CS

T3CKPS1:T3CKPS0

Sleep Input

T1OSCEN

Enable

Oscillator(1)

TMR3IF

Overflow

Interrupt

FOSC/4

Internal

Clock

TMR3ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

T1OSO/

T1OSI

Flag bit

(3)

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

T13CKI

CLR

CCP Special Trigger

T3CCPx

Timer3

TMR3L

T1OSC T3SYNC

TMR3CS

T3CKPS1:T3CKPS0 Sleep Input

T1OSCEN

Enable

Oscillator(1)

FOSC/4

Internal

Clock

TMR3ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

T1OSO/

T1OSI

TMR3

T13CKI

CLR

CCP Special Trigger

T3CCPx

To Timer1 Clock Input

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

High Byte

Data Bus<7:0>

TMR3H

Read TMR3L

Write TMR3L

Set TMR3IF Flag bit

on Overflow

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14.2 Timer1 Oscillator

The Timer1 oscillator may be used as the clock source

for Timer3. The Timer1 oscillator is enabled by setting

the T1OSCEN (T1CON<3>) bit. The oscillator is a low-

power oscillator rated up to 200 kHz. See Section 12.0

“Timer1 Module” for further details.

14.3 Timer3 Interrupt

The TMR3 register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR3 interrupt, if enabled, is generated on overflow,

which is latched in interrupt flag bit, TMR3IF

(PIR2<1>). This interrupt can be enabled/disabled by

setting/clearing TMR3 Interrupt Enable bit, TMR3IE

(PIE2<1>).

14.4 Resetting Timer3 Using a CCP

Trigger Output

If the CCP module is configured in Compare mode

to generate a “special event trigger”

(CCP1M3:CCP1M0 = 1011), this signal will reset

Timer3.

Timer3 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer3 is running in Asynchronous Counter mode,

this Reset operation may not work. In the event that a

write to Timer3 coincides with a special event trigger

from CCP1, the write will take precedence. In this mode

of operation, the CCPR1H:CCPR1L register pair

effectively becomes the period register for Timer3.

TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Note: The special event triggers from the CCP

module will not set interrupt flag bit,

TMR3IF (PIR1<0>).

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

PIR2 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000

PIE2 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000

IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111

TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu

TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu

T1CON RD16 —T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.

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NOTES:

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15.0 TIMER4 MODULE

The Timer4 module timer has the following features:

• 8-bit timer (TMR4 register)

• 8-bit period register (PR4)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR4 match of PR4

Timer4 has a control register shown in Register 15-1.

Timer4 can be shut-off by clearing control bit, TMR4ON

(T4CON<2>), to minimize power consumption. The

prescaler and postscaler selection of Timer4 are also

controlled by this register. Figure 15-1 is a simplified

block diagram of the Timer4 module.

15.1 Timer4 Operation

Timer4 can be used as the PWM time base for the

PWM mode of the CCP module. The TMR4 register is

readable and writable and is cleared on any device

Reset. The input clock (FOSC/4) has a prescale option

of 1:1, 1:4 or 1:16, selected by control bits

T4CKPS1:T4CKPS0 (T4CON<1:0>). The match out-

put of TMR4 goes through a 4-bit postscaler (which

gives a 1:1 to 1:16 scaling inclusive) to generate a

TMR4 interrupt, latched in flag bit, TMR4IF (PIR3<3>).

The prescaler and postscaler counters are cleared

when any of the following occurs:

• a write to the TMR4 register

• a write to the T4CON register

• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset or Brown-out Reset)

TMR4 is not cleared when T4CON is written.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6-3 T4OUTPS3:T4OUTPS0: Timer4 Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

•

1111 = 1:16 Postscale

bit 2 TMR4ON: Timer4 On bit

1 = Timer4 is on

0 = Timer4 is off

bit 1-0 T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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15.2 Timer4 Interrupt

The Timer4 module has an 8-bit period register, PR4,

which is both readable and writable. Timer4 increments

from 00h until it matches PR4 and then resets to 00h on

the next increment cycle. The PR4 register is initialized

to FFh upon Reset.

15.3 Output of TMR4

The output of TMR4 (before the postscaler) is used

only as a PWM time base for the CCP modules. It is not

used as a baud rate clock for the MSSP, as is the

Timer2 output.

FIGURE 15-1: TIMER4 BLOCK DIAGRAM

TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --00 0000

PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000

PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000

TMR4 Timer4 Module Register 0000 0000 0000 0000

T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000

PR4 Timer4 Period Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module.

Comparator

TMR4 Sets Flag

TMR4

Output(1)

Reset

Postscaler

Prescaler

PR4

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

bit TMR4IF

T4OUTPS3:T4OUTPS0

T4CKPS1:T4CKPS0

Caglure mode. Comgave mode. FWM mode. For CCP1 and CCP2. For all other modules.

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16.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

The PIC18FXX20 devices all have five CCP (Capture/

Compare/PWM) modules. Each module contains a

16-bit register, which can operate as a 16-bit Capture

Modulation (PWM) Master/Slave Duty Cycle register.

Table 16-1 shows the timer resources of the CCP

module modes.

The operation of all CCP modules are identical, with

the exception of the special event trigger present on

CCP1 and CCP2.

For the sake of clarity, CCP module operation in the

following sections is described with respect to CCP1.

The descriptions can be applied (with the exception of

the special event triggers) to any of the modules.

Note: Throughout this section, references to

ated with a specific CCP module are

referred to generically by the use of ‘x’ or

‘y’ in place of the specific module number.

Thus, “CCPxCON” might refer to the

control register for CCP1, CCP2, CCP3,

CCP4 or CCP5.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The

eight Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL.

bit 3-0 CCPxM3:CCPxM0: CCP Module x Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCPx module)

0001 = Reserved

0010 = Compare mode, toggle output on match (CCPxIF bit is set)

0011 = Reserved

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, Initialize CCP pin Low; on compare match, force CCP pin High

(CCPIF bit is set)

1001 = Compare mode, Initialize CCP pin High; on compare match, force CCP pin Low

(CCPIF bit is set)

1010 = Compare mode, Generate software interrupt on compare match (CCPIF bit is set,

(CCP pin is unaffected)

1011 = Compare mode, trigger special event (CCPIF bit is set):

For CCP1 and CCP2:

Timer1 or Timer3 is reset on event.

For all other modules:

CCPx pin is unaffected and is configured as an I/O port

(same as CCPxM<3:0> = 1010, above).

11xx =PWM mode

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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16.1 CCP Module Configuration

Each Capture/Compare/PWM module is associated

with a control register (generically, CCPxCON) and a

data register (CCPRx). The data register, in turn, is

comprised of two 8-bit registers: CCPRxL (low byte)

and CCPRxH (high byte). All registers are both

readable and writable.

16.1.1 CCP MODULES AND TIMER

RESOURCES

The CCP modules utilize Timers 1, 2, 3 or 4, depending

on the mode selected. Timer1 and Timer3 are available

to modules in Capture or Compare modes, while

Timer2 and Timer4 are available for modules in PWM

mode.

TABLE 16-1: CCP MODE – TIMER

RESOURCE

The assignment of a particular timer to a module is

determined by the Timer-to-CCP Enable bits in the

T3CON register (Register 14-1). Depending on the

configuration selected, up to four timers may be active

at once, with modules in the same configuration

(Capture/Compare or PWM) sharing timer resources.

The possible configurations are shown in Figure 16-1.

FIGURE 16-1: CCP AND TIMER INTERCONNECT CONFIGURATIONS

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1 or Timer3

Timer2 or Timer4

TMR1

CCP5

TMR2

TMR3

TMR4

CCP4

CCP3

CCP2

CCP1

TMR1

TMR2

TMR3

CCP5

TMR4

CCP4

CCP3

CCP2

CCP1

TMR1

TMR2

TMR3

CCP5

TMR4

CCP4

CCP3

CCP2

CCP1

TMR1

TMR2

TMR3

CCP5

TMR4

CCP4

CCP3

CCP2

CCP1

T3CCP<2:1> = 00 T3CCP<2:1> = 01 T3CCP<2:1> = 10 T3CCP<2:1> = 11

Timer1 is used for all Capture

and Compare operations for

all CCP modules. Timer2 is

used for PWM operations for

all CCP modules. Modules

may share either timer

resource as a common time

base.

Timer3 and Timer4 are not

available.

Timer1 and Timer2 are used

for Capture and Compare or

PWM operations for CCP1

only (depending on selected

mode).

All other modules use either

Timer3 or Timer4. Modules

may share either timer

resource as a common time

base, if they are in Capture/

Compare or PWM modes.

Timer1 and Timer2 are used

for Capture and Compare or

PWM operations for CCP1

and CCP2 only (depending on

the mode selected for each

module). Both modules may

use a timer as a common time

base if they are both in

Capture/Compare or PWM

modes.

The other modules use either

Timer3 or Timer4. Modules

may share either timer

resource as a common time

base if they are in Capture/

Compare or PWM modes.

Timer3 is used for all Capture

and Compare operations for

all CCP modules. Timer4 is

used for PWM operations for

all CCP modules. Modules

may share either timer

resource as a common time

base.

Timer1 and Timer2 are not

available.

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16.2 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the 16-bit

value of the TMR1 or TMR3 registers when an event

occurs on pin RC2/CCP1. An event is defined as one of

the following:

• every falling edge

• every rising edge

• every 4th rising edge

• every 16th rising edge

The event is selected by control bits, CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit, CCP1IF (PIR1<2>), is set; it must

be cleared in software. If another capture occurs before

the value in register CCPR1 is read, the old captured

value is overwritten by the new captured value.

16.2.1 CCP PIN CONFIGURATION

In Capture mode, the RC2/CCP1 pin should be

configured as an input by setting the TRISC<2> bit.

16.2.2 TIMER1/TIMER3 MODE SELECTION

The timers that are to be used with the capture feature

(Timer1 and/or Timer3) must be running in Timer mode,

or Synchronized Counter mode. In Asynchronous

Counter mode, the capture operation may not work. The

timer to be used with each CCP module is selected in the

T3CON register (see Section 16.1.1 “CCP Modules

and Timer Resources”).

16.2.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit, CCP1IF, following any such

change in operating mode.

16.2.4 CCP PRESCALER

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off or the CCP module is not in Capture mode,

the prescaler counter is cleared. This means that any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore, the first capture may be from

a non-zero prescaler. Example 16-1 shows the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 16-1: CHANGING BETWEEN

CAPTURE PRESCALERS

FIGURE 16-2: CAPTURE MODE OPERATION BLOCK DIAGRAM

Note: If the RC2/CCP1 is configured as an out-

put, a write to the port can cause a capture

condition.

CLRF CCP1CON, F ; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF CCP1CON ; Load CCP1CON with

; this value

CCPR1H CCPR1L

TMR1H TMR1L

Set Flag bit CCP1IF

TMR3

Enable

Q’s CCP1CON<3:0>

CCP1 pin

Prescaler

 1, 4, 16

and

Edge Detect

TMR3H TMR3L

TMR1

Enable

T3CCP2

4%:

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16.3 Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against either the TMR1 register

pair value or the TMR3 register pair value. When a

match occurs, the CCP1 pin:

• is driven High

• is driven Low

• toggles output (high-to-low or low-to-high)

• remains unchanged

The action on the pin is based on the value of control

bits, CCP1M3:CCP1M0. At the same time, interrupt

flag bit CCP1IF (CCP2IF) is set.

16.3.1 CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

16.3.2 TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode,

or Synchronized Counter mode, if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

16.3.3 SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen, the CCP1

pin is not affected. Only a CCP interrupt is generated (if

enabled).

16.3.4 SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

The special event trigger output of either CCP1 or

CCP2, resets the TMR1 or TMR3 register pair, depend-

ing on which timer resource is currently selected. This

allows the CCPR1 register to effectively be a 16-bit

programmable period register for Timer1 or Timer3.

The CCP2 Special Event Trigger will also start an A/D

conversion if the A/D module is enabled.

FIGURE 16-3: COMPARE MODE OPERATION BLOCK DIAGRAM

Note: Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to

the default low level. This is not the

PORTC I/O data latch.

Note: The special event trigger from the CCP2

module will not set the Timer1 or Timer3

interrupt flag bits.

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

Output

Logic

Special Event Trigger

Set Flag bit CCP1IF

Match

RC2/CCP1 pin

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

For CCP1 and CCP2 only, the Special Event Trigger will:

Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit

and set bit GO/DONE (ADCON0<2>),

which starts an A/D conversion (CCP2 only)

TMR3H TMR3L

T3CCP2 1

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TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

RCON IPEN — — RI TO PD POR BOR 0--1 11qq 0--q qquu

PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111

PIR2 —CMIE —EEIE BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000

PIE2 —CMIF —EEIF BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000

IPR2 —CMIP —EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 ---1 1111

PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000

PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000

IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111

TRISC PORTC Data Direction Register 1111 1111 1111 1111

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

TMR3H Timer3 Register High Byte xxxx xxxx uuuu uuuu

TMR3L Timer3 Register Low Byte xxxx xxxx uuuu uuuu

T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

CCPRxL(1) Capture/Compare/PWM Register x (LSB) xxxx xxxx uuuu uuuu

CCPRxH(1) Capture/Compare/PWM Register x (MSB) xxxx xxxx uuuu uuuu

CCPxCON(1) — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’.

Shaded cells are not used by Capture and Compare, Timer1 or Timer3.

Note 1: Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module

(CCP1 through CCP5). Bit assignments and Reset values for all registers of the same generic name are identical.

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16.4 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCP1 pin

produces up to a 10-bit resolution PWM output. Since

the CCP1 pin is multiplexed with the PORTC data latch,

the TRISC<2> bit must be cleared to make the CCP1

pin an output.

Figure 16-4 shows a simplified block diagram of the

CCP module in PWM mode.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 16.4.3

“Setup for PWM Operation”.

FIGURE 16-4: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 16-5) has a time base (period)

and a time that the output stays high (duty cycle).

The frequency of the PWM is the inverse of the period

(1/period).

FIGURE 16-5: PWM OUTPUT

16.4.1 PWM PERIOD

The PWM period is specified by writing to the PR2

following formula:

EQUATION 16-1:

PWM frequency is defined as 1/[PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

•TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

• The PWM duty cycle is latched from CCPR1L into

CCPR1H

16.4.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

EQUATION 16-2:

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

doublebuffering is essential for glitchless PWM

operation.

When the CCPR1H and 2-bit latch match TMR2, con-

catenated with an internal 2-bit Q clock or 2 bits of the

TMR2 prescaler, the CCP1 pin is cleared.

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTC I/O data

latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers CCP1CON<5:4>

Clear Timer,

CCP1 pin and

latch D.C.

TRISC<2>

RC2/CCP1

Note 1: 8-bit timer is concatenated with 2-bit internal Q

clock or 2 bits of the prescaler to create 10-bit

time base.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

Note: The Timer2 and Timer4 postscalers (see

Section 13.0 “Timer2 Module”) are not

used in the determination of the PWM

frequency. The postscaler could be used

to have a servo update rate at a different

frequency than the PWM output.

PWM Period = (PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 Prescale Value)

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The maximum PWM resolution (bits) for a given PWM

frequency is given by the equation:

EQUATION 16-3:

16.4.3 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2

2. Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the

TRISC<2> bit.

4. Set the TMR2 prescale value and enable Timer2

by writing to T2CON.

5. Configure the CCP1 module for PWM operation.

TABLE 16-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

TABLE 16-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4

Note: If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

FOSC

FPWM

---------------





log

2log

----------------------------- b i t s=

PWM Resolution (max)

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)1641111

PR2 Value FFh FFh FFh 3Fh 1Fh 17h

Maximum Resolution (bits) 14  10 12  10 10 8 7 6.58