STL33N60M6 Datasheet by STMicroelectronics

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PowerFLAT™ 8x8 HV
NG1DS2PS34D5Z
Drain(5)
Gate(1)
Driver
source (2)
Power
source (3, 4)
Features
Order code VDS RDS(on) max. ID
STL33N60M6 600 V 137 mΩ 21 A
• Reduced switching losses
• Lower RDS(on) per area vs previous generation
• Low gate input resistance
• 100% avalanche tested
• Zener-protected
Applications
• Switching applications
• LLC converters
• Boost PFC converters
Description
The new MDmesh™ M6 technology incorporates the most recent advancements to
the well-known and consolidated MDmesh family of SJ MOSFETs.
STMicroelectronics builds on the previous generation of MDmesh devices through its
new M6 technology, which combines excellent RDS(on) per area improvement with
one of the most effective switching behaviors available, as well as a user-friendly
experience for maximum end-application efficiency.
Product status link
STL33N60M6
Product summary
Order code STL33N60M6
Marking 33N60M6
Package PowerFLAT™ 8x8 HV
Packing Tape and reel
N-channel 600 V, 0.115 Ω typ., 21 A MDmesh™ M6 Power MOSFET
in a PowerFLAT™ 8x8 HV package
STL33N60M6
Datasheet
DS12638 - Rev 3 - August 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
VGS Gate-source voltage ±25 V
ID
Drain current (continuous) at Tcase = 25 °C 21
A
Drain current (continuous) at Tcase = 100 °C 13
IDM(1) Drain current (pulsed) 78 A
PTOT Total dissipation at Tcase = 25 °C 150 W
dv/dt(2) Peak diode recovery voltage slope 15
V/ns
dv/dt(3) MOSFET dv/dt ruggedness 50
Tstg Storage temperature range
-55 to 150 °C
TjOperating junction temperature range
1. Pulse width is limited by safe operating area.
2. ISD ≤ 21 A, di/dt = 400 A/μs, VDS < V(BR)DSS, VDD = 400 V
3. VDS ≤ 480 V
Table 2. Thermal data
Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case 0.83 °C/W
Rthj-pcb (1) Thermal resistance junction-pcb 45 °C/W
1. When mounted on FR-4 board of inch², 2oz Cu.
Table 3. Avalanche characteristics
Symbol Parameter Value Unit
IAR
Avalanche current, repetitive or non-repetitive
(pulse width limited by TJmax)4 A
EAS
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V) 500 mJ
STL33N60M6
Electrical ratings
DS12638 - Rev 3 page 2/15
2Electrical characteristics
(Tcase = 25 °C unless otherwise specified).
Table 4. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source breakdown
voltage VGS = 0 V, ID = 1 mA 600 V
IDSS Zero gate voltage drain current
VGS = 0 V, VDS = 600 V 1
µA
VGS = 0 V, VDS = 600 V,
Tcase = 125 °C(1) 100
IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 µA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3.25 4 4.75 V
RDS(on) Static drain-source on-
resistance VGS = 10 V, ID = 10.5 A 0.115 0.137 Ω
1. Defined by design, not subject to production test.
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance
VDS = 100 V, f = 1 MHz, VGS = 0 V
- 1515 -
pF
Coss Output capacitance - 128 -
Crss Reverse transfer capacitance - 4.2 -
Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 269 - pF
RGIntrinsic gate resistance f = 1 MHz, ID = 0 A - 1.5 - Ω
QgTotal gate charge VDD = 480 V, ID = 25 A,
VGS = 0 to 10 V
(see Figure 14. Test circuit for gate
charge behavior)
- 33.4 -
nC
Qgs Gate-source charge - 7.2 -
Qgd Gate-drain charge - 16.3 -
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS.
Table 6. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD = 300 V, ID = 12.5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 13. Switching times test
circuit for resistive load and Figure
18. Switching time waveform)
- 19.5 -
ns
trRise time - 33 -
td(off) Turn-off delay time - 38.5 -
tfFall time - 7.5 -
STL33N60M6
Electrical characteristics
DS12638 - Rev 3 page 3/15
Table 7. Source-drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISD Source-drain current - 21 A
ISDM (1) Source-drain current (pulsed) - 78 A
VSD (2) Forward on voltage ISD = 21 A, VGS = 0 V - 1.6 V
trr Reverse recovery time ISD = 25 A, di/dt = 100 A/µs,
VDD = 60 V
(see Figure 15. Test circuit for inductive
load switching and diode recovery times)
- 265 ns
Qrr Reverse recovery charge - 3.07 µC
IRRM Reverse recovery current - 23.2 A
trr Reverse recovery time ISD = 25 A, di/dt = 100 A/µs, VDD = 60 V,
Tj = 150 °C
(see Figure 15. Test circuit for inductive
load switching and diode recovery times)
- 374 ns
Qrr Reverse recovery charge - 5.78 µC
IRRM Reverse recovery current - 30.9 A
1. Pulse width is limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
STL33N60M6
Electrical characteristics
DS12638 - Rev 3 page 4/15
Ops-luau n nu: ma mm by R w T,S150 'c Tc:25 'c V :10 V 10 m 1 0 1a slPGIsoszamumcH slPGIsoszamzan mummy ewezammsosasmn
2.1 Electrical characteristics (curves)
Figure 1. Safe operating area
GIPG200620181213SOA
10 1
10 0
10 -1
10 -1 10 0 10 1 10 2
ID
(A)
VDS (V)
tp =1 µs
tp =10 µs
tp =1 ms
tp =10 ms
tp =100 µs
Operation in this area is
limited by R DS(on)
single pulse
TJ≤150 °C
TC=25 °C
VGS=10 V
Figure 2. Thermal impedance
PowerFLAT8x8HVzth
10 -1
10 -2
10 -5 10 -4 10 -3 10 -2
K
t p (s)
Single pulse
δ =0.01
δ =0.1
δ =0.2
δ =0.5
δ =0.05
δ =0.02 Z th =K*R thj-c
δ=t p /
Ƭ
tp
Ƭ
Figure 3. Output characteristics
GIPG150620181232OCH
70
60
50
40
30
20
10
00 4 8 12 16
ID
(A)
VDS (V)
VGS =7 V
VGS =6 V
VGS = 9, 10 V
VGS =5 V
VGS =8 V
Figure 4. Transfer characteristics
GIPG150620181233TCH
70
60
50
40
30
20
10
03 4 5 6 7 8 9
ID
(A)
VGS (V)
VDS = 20 V
Figure 5. Gate charge vs gate-source voltage
GIPG150620181237QVG
12
10
8
6
4
2
0
600
500
400
300
200
100
0
0 8 16 24 32 40
VGS
(V)
VDS
(V)
Qg (nC)
VDD = 480 V
ID = 25 A
VDS
Figure 6. Static drain-source on-resistance
GIPG260620180835RID
0.125
0.120
0.115
0.110
0.1050 4 8 12 16 20
RDS(on)
(Ω)
ID (A)
VGS = 10 V
STL33N60M6
Electrical characteristics (curves)
DS12638 - Rev 3 page 5/15
ewmmmmm
Figure 7. Capacitance variations
GIPG150620181232CVR
10 4
10 3
10 2
10 1
10 0
10 -1 10 0 10 1 10 2
C
(pF)
VDS (V)
CISS
COSS
CRSS
f = 1 MHz
Figure 8. Normalized gate threshold voltage vs
temperature
GIPG150620181230VTH
1.1
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125
VGS(th)
(norm.)
TJ (°C)
ID = 250 μA
Figure 9. Normalized on-resistance vs temperature
GIPG150620181231RON
2.5
2.0
1.5
1.0
0.5
0.0
-75 -25 25 75 125
RDS(on)
(norm.)
VGS = 10 V
TJ (°C)
Figure 10. Normalized V(BR)DSS vs temperature
GIPG150620181231BDV
1.08
1.04
1.00
0.96
0.92
0.88
-75 -25 25 75 125
V(BR)DSS
(norm.)
ID = 1 mA
TJ (°C)
Figure 11. Output capacitance stored energy
GADG200620181116EOS
14
12
10
8
6
4
2
00 100 200 300 400 500 600
EOSS
(µJ)
VDS (V)
Figure 12. Source-drain diode forward characteristics
GIPG260620180841SDF
1.1
1.0
0.9
0.8
0.7
0.6
0.50 4 8 12 16 20
VSD
(V)
ISD (A)
Tj = -50 °C
Tj = 25 °C
Tj = 150 °C
STL33N60M6
Electrical characteristics (curves)
DS12638 - Rev 3 page 6/15
3Test circuits
Figure 13. Switching times test circuit for resistive load
AM15855v1
VGS
PW
VD
RG
RL
D.U.T.
2200
µF
3.3
µF VDD
GND2
(power)
GND1
(driver signal)
+
Figure 14. Test circuit for gate charge behavior
GADG180720181011SA
RL
47 kΩ
2.7 kΩ
1 kΩ
IG= CONST 100 Ω
D.U.T.
+
pulse width
VGS
2200
μF
VG
VDD
GND1 GND2
Figure 15. Test circuit for inductive load switching and
diode recovery times
AM15857v1
A
D
D.U.T.
S
B
G
25Ω
AA
BB
RG
G
FAST
DIODE
D
S
L=100µH
µF
3.3 1000
µF VDD
GND1 GND2
D.U.T.
+
Figure 16. Unclamped inductive load test circuit
AM15858v1
Vi
Pw
VD
ID
D.U.T.
L
2200
µF
3.3
µF VDD
GND1 GND2
+
Figure 17. Unclamped inductive waveform
AM01472v1
V(BR)DSS
VDD
VDD
VD
IDM
ID
Figure 18. Switching time waveform
AM01473v1
0
VGS 90%
VDS
90%
10%
90%
10%
10%
ton
td(on) tr
0
toff
td(off) tf
STL33N60M6
Test circuits
DS12638 - Rev 3 page 7/15
4Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
STL33N60M6
Package information
DS12638 - Rev 3 page 8/15
BuTTuH VIEW E1 E2 D1 EXPOSED FAD 5qu VIEW A3 A1 E Pw m LD WP sEATwG PLANE TOP vIEw
4.1 PowerFLAT™ 8x8 HV package information
Figure 19. PowerFLAT™ 8x8 HV package outline
8222871_Rev_4
STL33N60M6
PowerFLAT™ 8x8 HV package information
DS12638 - Rev 3 page 9/15
Table 8. PowerFLAT™ 8x8 HV mechanical data
Ref.
Dimensions (in mm)
Min. Typ. Max.
A 0.75 0.85 0.95
A1 0.00 0.05
A3 0.10 0.20 0.30
b 0.90 1.00 1.10
D 7.90 8.00 8.10
E 7.90 8.00 8.10
D2 7.10 7.20 7.30
E1 2.65 2.75 2.85
E2 4.25 4.35 4.45
e 2.00 BSC
L 0.40 0.50 0.60
Figure 20. PowerFLAT™ 8x8 HV footprint
8222871_REV_4_footprint
Note: All dimensions are in millimeters.
STL33N60M6
PowerFLAT™ 8x8 HV package information
DS12638 - Rev 3 page 10/15
vvvvvvvvvv OOOOOOOOOOO a» I“ H“ H“
4.2 PowerFLAT™ 8x8 HV packing information
Figure 21. PowerFLAT™ 8x8 HV tape
W (16.00±0.3)
E (1.75±0.1)
F (7.50±0.1)
A0 (8.30±0.1)
P1 (12.00±0.1)
P2 (2.0±0.1) P0 (4.0±0.1)
D0 ( 1.55±0.05)
D1 ( 1.5 Min)
T (0.30±0.05)
B0 (8.30±0.1)
K0 (1.10±0.1)
Note: Base and Bulk qu antity 3000 pcs
8229819_Tape_revA
Note: All dimensions are in millimeters.
Figure 22. PowerFLAT™ 8x8 HV package orientation in carrier tape
STL33N60M6
PowerFLAT™ 8x8 HV packing information
DS12638 - Rev 3 page 11/15
Figure 23. PowerFLAT™ 8x8 HV reel
8229819_Reel_revA
Note: All dimensions are in millimeters.
STL33N60M6
PowerFLAT™ 8x8 HV packing information
DS12638 - Rev 3 page 12/15
Revision history
Table 9. Document revision history
Date Version Changes
02-Jul-2018 1 Initial release.
18-Jul-2018 2 Modified Section 3 Test circuits.
Minor text changes.
02-Aug-2018 3 Updated features in cover page.
STL33N60M6
DS12638 - Rev 3 page 13/15
Contents
1Electrical ratings ..................................................................2
2Electrical characteristics...........................................................3
2.1 Electrical characteristics (curves) .................................................5
3Test circuits .......................................................................7
4Package information...............................................................8
4.1 PowerFLAT™ 8x8 HV package information.........................................8
4.2 PowerFLAT™ 8x8 HV packing information ........................................10
Revision history .......................................................................13
STL33N60M6
Contents
DS12638 - Rev 3 page 14/15
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STL33N60M6
DS12638 - Rev 3 page 15/15