DRV8320(R), DRV8323(R) by Texas Instruments Datasheet

E 1!. B K E I TEXAS INSTRUMENTS swsman rFEBRUARV 2mLREvrsED MARCH 2022 DRV832x 6 to 60-V Three-Phase Smart Gate Driver Device Information DRVESQSR VQFN (48) 7.00 mm X7 00 mm I—‘—| pm mam ; 5%er me: am: am pm E E mum my g 3 "W” Curmm z u Sens: Currant Sense 3x Sunsc mum mmza MM sun mA

PWM

DRV832x

SPI or H/W

Three-Phase

Smart Gate Dri ve r

Gate D ri ve

M

nFAULT

Current

Sense

Current Sense

600 mA

Product

Folder

Order

Now

Technical

Documents

Tools &

Sof tware

Support &

Community

Ref erence

Design

1

Features

DRV8320, DRV8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

DRV832x 6 to 60-V Three-Phase Smart Gate Driver

3 Description

•

Triple Half-Bridge Gate Driver

–

Dri ves 3 High-Side and 3 Low-Side N-Channel

MOSFETs (NMOS)

•

Smart Gate Drive Architecture

–

Adjustable Slew Rate Control

–

10-mA to 1-A Peak Source Current

–

20-mA to 2-A Peak Sink Current

•

Integrated Gate Driver Power Supplies

–

Supports 100% PWM Duty Cycle

–

High-Side Charge Pump

–

Low-Side Linear Regulator

•

6 to 60-V Operating Voltage Range

•

Optional Integrated Buck Regulator

–

LMR16006X SIMPLE SWITCHER®

–

4 to 60-V Operating Voltage Range

–

0.8 to 60-V, 600-mA Output Capability

•

Optional Integrated Triple Current Sense

Amplifiers (CSAs)

–

Adjustable Gain (5, 10, 20, 40 V/V)

–

Bidirectional or Unidirectional Support

•

SPI and Hardware Interface Available

•

6x, 3x, 1x, and Independent PWM Modes

•

Supports 1.8-V, 3.3-V, and 5-V Logic Inputs

•

Low-Power Sleep Mode (12 µA)

•

Linear Voltage Regulator, 3.3 V, 30 mA

•

Compact QFN Packages and Footprints

•

Efficient System Design With Power Blocks

•

Integrated Protection Features

–

VM Undervoltage Lockout (UVLO)

–

Charge Pump Undervoltage (CPUV)

–

MOSFET Overcurrent Protection (OCP)

–

Gate Dri ver Fault (GDF)

–

Thermal Warning and Shutdown (OTW / OTS D)

–

Fault Condition Indicator (nFAULT)

2

Applications

•

Brushless-DC (BLDC) Motor Modules and PMSM

•

Fans, Pumps, and S e rvo Dri ves

•

E-Bikes, E-Scooters, and E-Mobility

•

Cordless Garden and Power Tools, Lawnmowers

•

Cordless Vacuum Cleaners

•

Drones, Robotics, and RC Toy s

•

Industrial and Logistics Robots

The DRV832x family of devices is an integrated gat e

driver for three-phase applications. The devices

provide three half-bridge gate drivers, each capable

of driving high-side and low-side N-channel power

MOSFETs. The DRV832x generates the correct gat e

dri ve voltages using an integrated charge pump for

the high-side MOSFETs and a linear regulator for t he

low-side MOSFETs. The Smart Gate Dri ve

architecture supports peak gate drive currents up to

1-A source and 2-A. The DRV832x can operate from

a single power supply and supports a wide input

supply range of 6 to 60 V for the gate driver and 4 to

60 V for the optional buck regulator.

The 6x, 3x, 1x, and independent input PWM modes

allow for simple interfacing to controller circuits. The

configuration settings for the gate driver and device

are highly configurable through the SPI or hardware

(H/W) interface. The DRV8323 and DRV8323R

devices integrate three low-side current sense

amplifiers that allow bidirectional current sensing on

all three phases of the drive stage. The DRV8320R

and DRV8323R devices integrate a 600-mA buck

regulator.

A low-power sleep mode is provided to achieve low

quiescent current draw by shutting down mos t of t he

internal circuitry. Internal protection functions are

provided for undervoltage lockout, charge pump fault ,

MOSFET overcurrent, MOSFET short circuit, gate

driver fault, and overtemperature. Fault conditions are

indicated on the nFAULT pin with details through t he

device registers for SPI device variants.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM )

DRV8320 WQFN (32) 5.00 mm × 5.00 mm

DRV8320R

VQFN (40)

6.00 mm × 6.00 mm

DRV8323

WQFN (40)

6.00 mm × 6.00 mm

DRV8323R VQFN (48) 7.00 mm × 7.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic

6 to 60 V

Protection

3x Sense A m pl if iers

(DRV8323 only)

Buck Regulator

An IMPORT ANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other i m portant disclaimers. PRODUCT ION DATA.

Controller

N-

Channel

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

2

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Table of Contents

1

Features...................................................................... 1

2

Applications............................................................... 1

3

Description................................................................. 1

4

Revision His t or y........................................................ 2

5

Device Comparison Table ....................................... 4

6

Pin Configuration and Functions ........................... 4

7

Specifications .......................................................... 11

7.1

Absolute Maximum Ratings .................................. 11

7.2

ESD Ratings........................................................ 11

7.3

Recommended Operating Conditions.................... 12

7.4

Thermal Information............................................. 12

7.5

Electrical Characteristics ...................................... 13

7.6

SPI Timing Req ui rem ents..................................... 18

7.7

T ypi ca l Characteristics ......................................... 19

8

Detailed Description ............................................... 21

8.1

Overview............................................................. 21

8.2

Functional Bl o ck Di ag ram..................................... 22

8.3

Feature Description.............................................. 30

8.4

Device Functional Modes ..................................... 50

8.5

Programming....................................................... 51

8.6

Register Maps ..................................................... 53

9

Application and Implementation ......................... 61

9.1

Application Information ........................................ 61

9.2

Typical Ap pli catio n .............................................. 61

10

Pow e r Supply Recommendations ...................... 70

10.1

Bulk Capacitance S i zing .................................... 70

11

Layout ...................................................................... 71

11.1

Layout Guidelines.............................................. 71

11.2

Layout Example ................................................ 72

12

Device and Documentation Support................... 73

12.1

Device Support ................................................. 73

12.2

Documentation Support ..................................... 73

12.3

Related Links .................................................... 73

12.4

Receiving Notification of Documentation Updates 74

12.5 Community Resources....................................... 74

12.6

Trademarks ....................................................... 74

12.7

Electrostatic Discharge Caution ......................... 74

12.8

G l o ssa ry ............................................................ 74

13

Me chanical, Packaging, and Orderable

Information .............................................................. 74

4

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (August 2018) to Revision D Page

•

Added information in the Sleep Mode section on the behavior of GHx and GLx w hen Enable is pulled low …………………50

Changes from Revision B (December 2017) to Revision C

Page

•

Changed the Applications .............................................................................................................................................................. 1

•

Updated input labels for the INLx and INHx signals in the Layout Example imags .................................................................. 72

•

Added the DRV835x device options to the image in the Device Nomenclature section.......................................................... 73

Changes from Revision A (April 2017) to Revision B Page

•

Changed the low -pow er sleep mode supply current from the max imum value (20 µA) to the typical value (12 µA) in

the Features .................................................................................................................................................................................... 1

•

Changed the Applications .............................................................................................................................................................. 1

•

Changed the GA IN value from 45 kΩ to 47 kΩ in the test condition of the amplif ier gain for the H/W device in the

Electrical Characteristics table ..................................................................................................................................................... 15

•

Deleted tEN_nSCS from the SPI Sl ave Mode Timing Diagram ...................................................................................................... 18

•

Added a note to the Synchronous 1x PWM Mode to define !PWM ........................................................................................... 31

•

Updated the Auto Offset Calibration section ............................................................................................................................... 44

•

Updated the VDS Latched Shutdown and VDS Automatic Retry sections .................................................................................. 48

•

Updated the Sleep Mode section................................................................................................................................................. 50

•

Changed the address listed in the title for the Gate Drive LS Register section to the correct register address, 0x04 .......... 58

•

Changed the max imum Qg value for both trapezoidal and sinusoidal commutation the VVM = 8 V example of the

Detailed Design Procedure .......................................................................................................................................................... 63

•

Changed IDRIVEP and IDRIVEN equations in the IDRIVE Configuration section ............................................................................64

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R wwaLcom copyngmcc) 201772022, Taxes \nslrumenls \noorpaated SubmtDacumentatmn Feedback 3 Fmducl Fomeerls DRV8320 DRV8320R DRV8323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

3

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Changes from Original (February 2017) to Revision A Page

•

Changed the test condition for the IBIAS parameter in the Electrical Characteristics table....................................................... 16

•

Changed the G Hx values in the 3x PWM Mode Truth Table .................................................................................................... 31

•

Changed the calibration description and added auto ca librat ion feature d escriptio n .............................................................. 44

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com CURRENT SENSE DRV8320RH Hardware DRVESQSH Hardware DRV8323RH Hardware DRVBSZSRS SPI cm pGNu WLC ch WLE wHa WM WHA cm pGNu WLC ch WLE wHa WM WHA O F O u u u u L4 L4 L4 L4 U u u u u u u L; 11 VI Fl Fl Fl Fl Fl Fl F1 F1 F1 F1 F1 F1 F1 F1 r1r'lr'l 5w as 5% me am Gm 5m G11: Pin Functions—32-Pin DRV8320 Devices GHA 5 5 o mgpsme galedwei ompm Connecumhegaleonhe mgrrrsme power MOSFEI’ GHB 12 12 o mgpsme galedwei ompm Connecumhegaleonhe mgrrrsme power MOSFEI’ cm 13 13 o mgpsme galedwei ompm Connecumhegaleonhe mgrrrsme power MOSFEI’ (1) PWR : puwenl =1npm,o : mnpuL NC = no connechon‘ OD: open—dramompm 4 Submt DOCUI'EHA‘ENOIT Feedback Cnpy rlghl© 201772022 Tex$1nstrumentsmmrpovmed Fruducl Fomeerrs DRV8320 DRvaszoR DRVB323 DRvaszaR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output

4

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

1

24

2

23

3

22

4

21

Thermal

5 Pad 20

6

19

7

18

8

17

1

24

2

23

3

22

4

21

Thermal

5 Pad 20

6

19

7

18

8

17

SLB

GLB

SHB

GHB

GHC

SHC

GLC

SLC

5

Device Comparison Table

DEVICE VARIANT (1) CURRENT SENSE

AMPLIFIERS

BUCK REGULATOR(1) INTERFACE(1)

DRV8320 DRV8320H

0

None Hardware

DRV8320S SPI

DRV8320R

DRV8320RH

600 mA

Hardware

DRV8320RS

SPI

DRV8323

DRV8323H

3

None

Hardware

DRV8323S SPI

DRV8323R

DRV8323RH

600 mA

Hardware

DRV8323RS SPI

(1) For more information on the device name and device options, see the Device Nomenclature section. For additional details, see the

Architecture for Brushless-DC Gate Dri ve Systems application report.

6

Pin Configuration and Functions

DRV8320H RTV Package

32-Pin WQFN With Exposed Thermal Pad

Top View

DRV8320S RTV Package

32-Pin WQFN With Exposed Thermal Pad

Top View

CPH DVDD CPH DVDD

VCP

AGND

VCP

AGND

VM ENABLE VM ENABLE

VDRAIN

NC VDRAIN

nSCS

GHA

VDS

GHA

SCLK

SHA

IDRIVE

SHA

SDI

GLA

MODE

GLA

SDO

SLA

nFAULT

SLA

nFAULT

Not to scale Not to scale

Pin Functions—32-Pin DRV8320 Devices

TYPE(1)

DESCRIPTION

N AM E

NO.

DRV8320H

DRV8320S

AGND

23

PWR

Device analog g r ound. Connect to system g r ound.

CPH

1

PWR Char g e pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.

CPL 32 32 PWR C harg e pump switc hing node. Connect a X5R or X7R, 47-nF, VM-r ated ceramic capacitor between the CPH and CPL pins.

DVDD 24 24 PWR

3.3-V inter nal reg ul ator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins.

This reg ul ator can source up to 30 mA externally.

ENABLE 22 22 I

Gate driver enable. When this pin is logic low the device g oes to a low-power sleep mode. An 8 to 40-µs pulse can be used

to r eset fault conditions.

GHA

5

O

High-side g ate driver output. Connect to the g ate of the hi g h-side power MOSFET.

GHB

12

O

High-side g ate driver output. Connect to the g ate of the hi g h-side power MOSFET.

GHC

13

O

High-side g ate driver output. Connect to the g ate of the hi g h-side power MOSFET.

SLB

9

32

CPL

GLB

10

31

PGND

SHB

11

30

INLC

GHB

12

29

INHC

GHC

13

28

INLB

SHC

14

27

INHB

GLC

15

26

INLA

SLC

16

25

INHA

9

32

CPL

10

31

PGND

11

30

INLC

12

29

INHC

13

28

INLB

14

27

INHB

15

26

INLA

16

25

INHA

I TEXAS INSTRUMENTS www. .com DRV8320, DRV8320R 8323R PIN No. DRvszon DRvums cm 7 7 o Wmegamamwmm Canned lo {hegzlecﬂme wwsmemmosrn cu; m w o Wmegamamwmm Canned lo Khegzlecﬂme wwsmemmosrn cm 15 15 o Wmegamamwmm Canned lo {hegzlecﬂme wwsmemmosrn mmvg 19 7 \ Galedme output currenlseumg m: pm‘s 37mm mpmpmselbyzn exema‘ reswsw WM 25 25 \ ngnsme gzledwei comm mpm rmspmcmuus me outputmmmgwmegammy was 27 27 ngnsme gzledwei comm mpm rmspmcmuus me outputmmmgwmegammy me 29 29 \ ngnsme gzledwei comm mpm rmspmcmuus me outputmmmgwmegammy Wm 25 2s \ Wswdegamdnvev comm maul m: uncomra‘smew‘pm mm \owsme gatedmev \NLB 25 25 \ Wswdegamdnvev comm maul m: mmnmsmemmm mm \owsme gate dmev me an 30 \ Wswdegamdnvev comm maul m: mmnmsmemmm mm \owsme gate dmev MODE m 7 \ PWMmpulrmde senmg TmspmxsaMexe‘ mpulpmse‘byznenemz‘ ymlm mum Fad PWR Must be connemed «a gymnd Copy ngm© 2017720219”: \nstrumenls \nwrpaated Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR Submt Documentation Feedback

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

5

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Pin Functions—32-Pin DRV8320 Devices (continued)

TYPE(1)

DESCRIPTION

N AM E

NO.

DRV8320H

DRV8320S

GLA

7

O Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

GLB 10 10 O Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

GLC

15

O

Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

IDRIVE

19

—

I

Gate dr i ve output current setti ng . This pin is a 7 level input pin set by an external resistor .

INHA

25

I

High-side g ate driver control input. This pin contr ols the output of the hig h-side g ate driver.

INHB 27 27 I High-side g ate driver control input. This pin contr ols the output of the hig h-side g ate driver.

INHC 29 29 I High-side g ate driver contr ol input. This pin controls the output of the hig h-side g ate driver .

INLA 26 26 I Low-side g ate driver contr ol input. This pin controls the output of the low-side g ate driver.

INLB

28

I

Low-side g ate driver control input. This pin contr ols the output of the low-side g ate driver.

INLC

30

I

Low-side g ate driver control input. This pin contr ols the output of the low-side g ate driver.

MODE 18 — I PWM input mode setti ng . This pin is a 4 level input pin set by an exter nal resistor .

NC 21 — NC No internal connection. This pin can be left fl oati ng or connected to system g r ound.

nFAULT 17 17 OD Fault indicator output. This pin is pulled logic low duri ng a fault condition and req uir es an external pullup resistor.

nSCS

—

21

I

Serial chip select. A logic low on this pin enables serial inter face communication.

PGND

31

PWR

Device power g r ound. Connect to system g r ound.

SCLK — 20 I Serial clock input. Serial data is shifted out and captured on the cor r espondi ng rising and falling edge on this pin.

SDI — 19 I Ser ial data input. Data is captured on the falling edge of the SCLK pin.

SDO

—

18

OD

Serial data output. Data is shifted out on the rising edg e of the SCLK pin. This pin r eq uires an external pullup resistor.

SHA

6

I

High-side source sense input. Connect to the hig h-side power MOSFET source.

SHB

11

I

High-side source sense input. Connect to the hig h-side power MOSFET source.

SHC 14 14 I High-side source sense input. Connect to the hig h-side power MOSFET source.

SLA

8

I Low-side source sense input. Connect to the low-side power MOSFET source.

SLB

9

I

Low-side source sense input. Connect to the low-side power MOSFET source.

SLC

16

I

Low-side source sense input. Connect to the low-side power MOSFET source.

VCP

2

PWR

Char g e pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.

VDRAIN

4

I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.

VDS 20 — I VDS monitor trip point setti ng . This pin is a 7 level input pin set by an external r esistor .

VM

3

PWR Gate driver power supply input. Connect to the bri dg e power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and

g r eater then or eq ual to 10-uF local capacitance between the VM and PGND pins.

Ther mal Pad PWR Must be connected to g round

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.n.com “J “J “J “J “J “J “J “J “J “J Pin Functions—40PM DRV8320R DeVIces nRvaImI DRVMZORS AGND 25 26 FWR DeMce anang ground Comm-3:140 mew ground EGN D 34 34 FWR Buck reguIaIm ground Canned Io sys‘em gmund ca 35 35 FWR Buck reguIaIm bomsvap Input Cmmecla XSR or xm 01'“; 16V capacnu between m as and swpms cw 3 3 FWR Charge pumpswﬂcmng node Connedz X5R or xm an: VMrraled ceramIc capamkw Damn Ihe cw and CPL pms cm 2 2 FWR Charge pumpswﬂcmng node Connedz X5R or xm an: VMrraled ceramIc capamkw Damn Ihe cw and CPL pms 3 :w mIemaI regIIIaIm oquIII Connects xsa u m. HI; 5 3V ceramIc capamuw Damn Ihe DVDD and AGND pm: INIIA ze 25 I HIgnsme gaIearwmmI mum m: pmcmvdsihemnpmnnm mgnsmegaledwev INHB 30 an I HIgnsme gaIearwmmI mum m: pmcmvdsihemnpmnnm mgnsmegaledwev INHC 32 32 I HIgnsme gaIearwmmI mum m: pmcmvdsihemnpmnnm mgnsmegaledwev INLA 29 29 I LMSIdegzledvIvercmmu Input m: wncomm‘sﬂmompm mm msmegmemwer INLB m 31 I LMSIdegzledvIvercmmu Input m: wncomm‘sﬂmompm mm msmegmemwer INLC 33 33 I LMSIdegzledvIvercmmu Input m: wncomm‘sﬂmompm mm msmegmemwer MODE zI 7 I PWM mum mode senmg m: meSaAIeIeI Input pmseI manmema‘ resIS‘OV no 24 7 NC No mIemaI connechon m: pm can be Ieﬂﬂualmg m connected to system gvmnd no 31 37 NC No mIemaI connechon m: pm can be Ieﬂﬂualmg m connected to system gvmnd "Run 20 20 on Faun Imam mm m: pm .5 puHed Iogm Iow duvmg a IauII common and reqwes an enema‘ puHupvesIstoi (I) PWR : puwer‘l = InpuI, o : oquuL NC = no connedlon‘ OD: open—dramoutpul 6 Submt Docunentanan Feedbacﬁ capy ngm© 201772022 Tex$ InsIrumenIs Inmrpuatea Fmducl FoIderLIrIls DRV8320 DRV8320R DRV8323 DRvaszsR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output

6

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

1

30

2

29

3

28

4

27

5

26

Thermal

6 Pad 25

7

24

8

23

9

22

10

21

1

30

2

29

3

28

4

27

5

26

Thermal

6 Pad 25

7

24

8

23

9

22

10

21

SLB

GLB

SHB

GHB

GHC

SHC

GLC

SLC

GND

nFAUL

DRV8320RH RHA Package

40-Pin VQFN With Exposed Thermal Pad

Top View

DRV8320RS RHA Package

40-Pin VQFN With Exposed Thermal Pad

Top View

PGND

INHB

PGND

INHB

CPL

INLA

CPL

INLA

CPH

INHA

CPH

INHA

VCP

DVDD

VCP

DVDD

VM AGND VM AGND

VDRAIN

ENABLE

VDRAIN

ENABLE

GHA

NC GHA

nSCS

SHA

VDS

SHA

SCLK

GLA

IDRIVE

GLA

SDI

SLA

MODE

SLA

SDO

Not to scale Not to scale

Pin Functions—40-Pin DRV8320R Devices

TYPE(1)

DESCRIPTION

N AM E NO.

DRV8320RH

DRV8320RS

AGND

26

PWR

Device analog g r ound. Connect to system g r ound.

BGND 34 34 PWR Buck r eg ulator g round. Connect to system g r ound.

CB 35 35 PWR Buck r eg ulator bootstrap input. Connect a X5R or X7R, 0.1-µF, 16-V, capacitor between the CB and SW pins.

CPH

3

PWR

Char g e pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.

CPL

2

PWR

Char g e pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.

DVDD 27 27 PWR

3.3-V inter nal reg ul ator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins.

This reg ul ator can source up to 30 mA externally.

ENABLE 25 25 I Gate driver enable. When this pin is logic low the device g oes to a low-power sleep mode. An 8 to 40-µs low pulse can be

used to reset fault conditions.

FB

40

I

Buck feedback input. A r esistor divider from the buck post inductor output to this pin sets the buck output vol tag e.

GHA

7

O

High-side g ate driver output. Connect to the g ate of the hi g h-side power MOSFET.

GHB 14 14 O High-side g ate driver output. Connect to the g ate of the hi g h-side power MOSFET.

GHC 15 15 O High-side g ate driver output. Connect to the g ate of the hi g h-side power MOSFET.

GLA

9

O Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

GLB

12

O

Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

GLC

17

O

Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

GND 19 19 PWR Device g round. Connect to system g r ound.

IDRIVE 22 — I Gate dr i ve output current setti ng . This pin is a 7 level input pin set by an external r esistor .

INHA

28

I

High-side g ate driver control input. This pin contr ols the output of the hig h-side g ate driver.

INHB

30

I

High-side g ate driver control input. This pin contr ols the output of the hig h-side g ate driver.

INHC 32 32 I High-side g ate driver contr ol input. This pin controls the output of the hig h-side g ate driver .

INLA 29 29 I Low-side g ate driver control input. This pin controls the output of the low-side g ate driver.

INLB

31

I

Low-side g ate driver control input. This pin contr ols the output of the low-side g ate driver.

INLC

33

I

Low-side g ate driver control input. This pin contr ols the output of the low-side g ate driver.

MODE

21

—

I

PWM input mode setti ng . This pin is a 4 level input pin set by an exter nal resistor .

NC 24 — NC No internal connection. This pin can be left fl oati ng or connected to system g r ound.

NC 37 37 NC No internal connection. This pin can be left fl oati ng or connected to system g r ound.

nFAULT

20

OD

Fault indicator output. This pin is pulled logic low duri ng a fault condition and req uir es an external pullup resistor.

SLB

11

40

FB

GLB

12

39

nSHD

SHB

13

38

VIN

GHB

14

37

NC

GHC

15

36

SW

SHC

16

35

CB

GLC

17

34

BGN

SLC

18

33

INLC

GND

19

32

INHC

nFAUL

20

31

INLB

11

40

FB

12

39

nSHD

13

38

VIN

14

37

NC

15

36

SW

16

35

CB

17

34

BGN

18

33

INLC

19

32

INHC

20

31

INLB

I TEXAS INSTRUMENTS www.li.com DRV8320, DRV8320R 8323R PIN No, nRvmnRH DRVMZORS 7 24 mum Pad ;_| L] ;_| L] ;_| L] ;_| L] L] L] sanax END select A mg m m ow {ms pm memes seﬂz‘ mledzce commumcaum Buck Wm WM Ename am msame mpul (hxgh vouage lo‘eianl) lnlema‘ puuup curvenl source PM“ my mam 25v m Must be conneded Kagvound L] L] L] L] ;_| L] ;_| L] ;_| L] Pin Functions—40-Pin DRV8323 DeVIces pm No. :0?me Dumas AGND 32 32 PWR Demos anamg gmum Connecuosyslem gum: CAL 31 31 \ Armhnev czhbrzhon mpm 52‘ \ng my ‘omlemaHyshon ampmer mpuls and pemvm aulo mm cahbiahm 1) P R=puwen mpuLO-ou puL NC = no connedwon‘ OD — open—dramompm SubmtDacumentanon Feedback 7 Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output

Submit Documentation Feedback

7

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

SNB

SPB

GLB

SHB

GHB

GHC

SHC

GLC

SPC

SNC

Pin Functions—40-Pin DRV8320R Devices (continued)

TYPE(1)

DESCRIPTION

N AM E

NO.

DRV8320RH

DRV8320RS

nSCS — 24 I Serial chip select. A logic low on this pin enables ser ial interface communication.

nSHDN 39 39 I Buck shutdown input. Enable and disable input (hig h voltag e toler ant) . Inter nal pullup cur rent sour ce. Pull lower than 1.25 V to

disable. Float to enable. Establish input under vol tag e lockout wi th two r esistor divider .

PGND

1

PWR

Device power g r ound. Connect to system g r ound.

SCLK

—

23

I

Serial clock input. Serial data is shifted out and captur ed on the c orr espondi ng rising and falling edge on this pin.

SDI — 22 I Serial data input. Data is captured on the falling edge of the SCLK pin.

SDO — 21 OD Ser ial data output. Data is shifted out on the rising edg e of the SCLK pin. This pin req ui res an external pullup resistor.

SHA

8

I

High-side source sense input. Connect to the hig h-side power MOSFET source.

SHB

13

I

High-side source sense input. Connect to the hig h-side power MOSFET source.

SHC

16

I

High-side source sense input. Connect to the hig h-side power MOSFET source.

SLA 10 10 I Low-side source sense input. Connect to the low-side power MOSFET source.

SLB 11 11 I Low-side source sense input. Connect to the low-side power MOSFET source.

SLC

18

I

Low-side source sense input. Connect to the low-side power MOSFET source.

SW

36

O

Buck switch node. Connect this pin to an inductor , diode, and the CB bootstrap capacitor .

VCP

4

PWR

Char g e pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.

VDRAIN

6

I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.

VDS 23 — I VDS monitor trip point setti ng . This pin is a 7 level input pin set by an external resistor .

VIN 38 38 PWR Buck reg ulator power supply input. Place an X5R or X7R, VM-r ated ceramic capacitor between the VIN and BGND pins.

VM

5

PWR

Gate driver power supply input. Connect to the bri dg e power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and

g r eater then or eq ual to 10-uF local capacitance between the VM and PGND pins.

Ther mal Pad PWR Must be connected to g round

DRV8323H RTA Package

40-Pin WQFN With Exposed Thermal Pad

Top View

DRV8323S RTA Package

40-Pin WQFN With Exposed Thermal Pad

Top View

CPL ENABLE

CPL

ENABLE

CPH

GAIN

CPH

nSCS

VCP

VDS

VCP

SCLK

VM

VDRAIN

GHA

IDRIVE

MODE

nFAULT

VM

VDRAIN

GHA

SDI

SDO

nFAULT

SHA VREF SHA VREF

GLA

SOA

GLA

SOA

SPA

SOB

SPA

SOB

SNA

SOC

SNA

SOC

Not to scale Not to scale

Pin Functions—40-Pin DRV8323 Devices

TYPE(1)

DESCRIPTION

N AM E

NO.

DRV8323H

DRV8323S

AGND 32 32 PWR Device analog g round. Connect to system g r ound.

CAL 31 31 I Amplifier calibr ation input. Set logic hig h to internally short amplifier inputs and perfor m auto offset calibration.

CPH

2

PWR Char g e pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.

1

30

2

29

3

28

4

27

5

26

Thermal

6

Pad

25

7

24

8

23

9

22

10

21

1

30

2

29

3

28

4

27

5

26

Thermal

6

Pad 25

7

24

8

23

9

22

10

21

SNB

11

40

PGN

SPB

12

39

INLC

GLB

13

38

INHC

SHB

14

37

INLB

GHB

15

36

INHB

GHC

16

35

INLA

SHC

17

34

INHA

GLC

18

33

DVD

SPC

19

32

AGN

SNC

20

31

CAL

11

40

PGN

12

39

INLC

13

38

INHC

14

37

INLB

15

36

INHB

16

35

INLA

17

34

INHA

18

33

DVD

19

32

AGN

20

31

CAL

DRV8320, DRV8320R I TEXAS INSTRUMENTS www. .com pm No. 1:12va Dnvscms CPL 1 1 1mm Chavge pump swuchmg node Canned a xsa u x7R.477np1/M71a1m ceiamm capacnor beiween 1m cw and am pm: R 3 w 1mema1 veg 1113101 mum Canned a xsa u m. 1711: 5 3v cevamm capamk‘l Damn Ihe DVDD and AGND p171: WHC 35 38 1 H1gns1oegaled11vev comm mpm 11.15pmcomm:1mompmmmmwsmegaeumy 111m 35 35 1 Wsmegamdnvevcomm171911113115 mmmmsmewmm mm 1Ws1dega‘edv11ev 1NLB 37 37 1 Wsmegamdnvevcomm171911113115 mmmmsmewmm mm 1Ws1dega‘edv11ev 1NLC 39 39 1 Wsmegamdnvevcomm171911113115 mmmmsmewmm mm 1Ws1dega‘edv11ev MODE 25 7 1 PWMmpmmoae 521W Th1sp1n1saA1eve¢ 1npmp1nse4byanenema1 12515101 "Run 25 25 oD Famhndmalmouwm Th1sp1n1spu11ed1og1c1rmdu1mg alauhcw1uonandvequ1vesanenevm1pu11up1es1su‘l nSCS 7 29 1 5121131 cmpseled A1031: 10:10710115 pmenames se11a1 menacemmumcahon PGND AD 41: 1mm Demos my ground Connect 10 5mm gvound scu< 7="" 25="" 1="" sei1a1c1ock1nput="" sev1a1="" da'a1s="" may:="" cut="" and="" camuvsd="" onihe="" cavesponmng="" 11s1r1gandla111ng="" eogemims="" pm="" 5131="" 7="" 27="" 1="" 5121131="" data="" mpm="" 031315="" captured="" on="" 1m1a11mg="" edgeonhe="" scum="" 500="" 7="" 25="" 01)="" 5121131="" data="" ompm="" data1ssh1l|ed="" om="" on="" 1112="" 115mg="" edgeonhe="" scum="" m;="" pmveqwes="" anenemm="" pu11upyes1s1o1="" sha="" 7="" 1="" 1="" mgnsmesmcesmmpm="" connecummmgrrsmepow="" mosfei'souvce="" she="" 14="" 14="" 1="" mgnsmesmcesmmpm="" connecummmgrrsmepow="" mosfei'souvce="" m="" 17="" 17="" 1="" mgnsmesmcesmmpm="" connecummmgrrsmepow="" mosfei'souvce="" 5m="" 10="" 1a="" 1="" cunenlsense="" ampmev="" mput="" connect="" 10="" the="" 1ws1de="" o1="" ihe="" cunenlshunl="" 1es1s|ov="" sne="" 11="" 11="" 1="" mnemmseamummm="" connschome1ws1deonhecunenlshunl1es1skw="" 5m="" 2:1="" 20="" 1="" cunenl="" sense="" ampmev="" mput="" connect="" 10="" m1ws1de="" o1="" ihe="" cunenl="" 5mm="" 1es1s|ov="" 50a="" 23="" 23="" o="" cunenl="" sense="" ampmev="" cutout="" wsme="" cunenl="" 5mm="" amwmev="" mpm="" conned="" m="" the="" 10ws1de="" my="" m="" osfet="" some="" and="" mg="" mme="" o1="" the="" cunem="" 5mm="" ww="" 3="" 3="" 1mm="" chagepumpmum="" conneclaxsr="" ontr="" 17.1:="" 1&vcevamccapac1mv="" beiweenlhevcp="" and="" w="" ms="" vomw="" 5="" 5="" 1="" h1gns1oe="" mosfet="" dvamsensempul="" connect="" {othecommnwm="" o1="" ihe="" mosfet="" mam;="" them1a1pad="" 1mm="" m1151="" be="" connected="" «0="" gmund="" a="" submtdocu/ygntanan="" 1:951:17“;="" capyngm©="" 201772022="" tex$1muumenls1nmrpuated="" fruducl="" fo1derl1r11s="" drv8320="" drva320r="" drv5323="" drvaszsr="">

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

8

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Pin Functions—40-Pin DRV8323 Devices (continued)

TYPE(1)

DESCRIPTION

N AM E

NO.

DRV8323H

DRV8323S

CPL

1

PWR Char g e pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.

DVDD 33 33 PWR R 3.3-V internal r eg ulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins.

This reg ul ator can source up to 30 mA externally.

ENABLE 30 30 I

Gate driver enable. When this pin is logic low the device g oes to a low-power sleep mode. An 8 to 40-µs low pulse can be

used to reset fault conditions.

GAIN 29 — I Amplifier g ain setti ng . The pin is a 4 level input pin set by an external resistor .

GHA

6

O High-side g ate driver output. Connect to the g ate of the hi g h-side power MOSFET.

GHB 15 15 O High-side g ate driver output. Connect to the g ate of the hi g h-side power MOSFET.

GHC

16

O

High-side g ate driver output. Connect to the g ate of the hi g h-side power MOSFET.

GLA

8

O

Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

GLB 13 13 O Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

GLC 18 18 O Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

IDRIVE

27

—

I

Gate dr i ve output current setti ng . This pin is a 7 level input pin set by an external resistor .

INHA

34

I

High-side g ate driver control input. This pin contr ols the output of the hig h-side g ate driver.

INHB

36

I

High-side g ate driver control input. This pin contr ols the output of the hig h-side g ate driver.

INHC

38

I

High-side g ate driver control input. This pin contr ols the output of the hig h-side g ate driver.

INLA

35

I

Low-side g ate driver control input. This pin contr ols the output of the low-side g ate driver.

INLB

37

I

Low-side g ate driver control input. This pin contr ols the output of the low-side g ate driver.

INLC

39

I

Low-side g ate driver control input. This pin contr ols the output of the low-side g ate driver.

MODE 26 — I PWM input mode setti ng . This pin is a 4 level input pin set by an external r esistor.

nFAULT 25 25 OD Fault indicator output. This pin is pulled logic low duri ng a fault condition and req uir es an external pullup resistor.

nSCS

—

29

I

Serial chip select. A logic low on this pin enables serial inter face communication.

PGND

40

PWR

Device power g r ound. Connect to system g r ound.

SCLK

—

28

I

Serial clock input. Serial data is shifted out and captur ed on the c orr espondi ng rising and falling edge on this pin.

SDI — 27 I Ser ial data input. Data is captured on the falling edge of the SCLK pin.

SDO — 26 OD Serial data output. Data is shifted out on the rising edg e of the SCLK pin. This pin req ui res an external pullup resistor.

SHA

7

I

High-side source sense input. Connect to the hig h-side power MOSFET source.

SHB

14

I

High-side source sense input. Connect to the hig h-side power MOSFET source.

SHC

17

I

High-side source sense input. Connect to the hig h-side power MOSFET source.

SNA 10 10 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.

SNB 11 11 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.

SNC 20 20 I Cur rent sense amplifier input. Connect to the low-side of the current shunt resistor.

SOA

23

O

Current sense amplifier output.

SOB

22

O

Current sense amplifier output.

SOC 21 21 O Current sense amplifier output.

SPA

9

I Low-side cur rent shunt amplifier input. Connect to the low-side power MOSFET source and hi g h-side of the current shunt

resistor .

SPB 12 12 I

Low-side current shunt amplifier input. Connect to the low-side power MOSFET sour ce and hig h-side of the curr ent shunt

resistor .

SPC 19 19 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET sour ce and hig h-side of the curr ent shunt

resistor .

VCP

3

PWR

Char g e pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.

VDRAIN

5

I

High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.

VDS 28 — I VDS monitor trip point setti ng . This pin is a 7 level input pin set by an external resistor .

VM

4

PWR Gate driver power supply input. Connect to the bri dg e power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and

g r eater then or eq ual to 10-uF local capacitance between the VM and PGND pins.

VREF 24 24 PWR

Current sense amplifier power supply input and refer ence. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between

the VREF and AGND pins.

Ther mal Pad

PWR

Must be connected to g round

I TEXAS INSTRUMENTS www.ll. com m DRV8320, DRV8320R 8323R nan m 1m 1m 1m 1m 1m 1m WWW—1717171 WWW—1717171 L— L— WWW—1 WWW—1 Pin Functions—48PM DRV8323R DeVIces pm No. nRvmmH Dumas AGN D 35 35 WVR DeMce anaog ground Connaa 1g swan ground EGN D 43 42 WVR Buck regmelm ground Connect 10 system gmund CAL 34 34 1 m1maneamaw1ma SeHoglc h1gh{a1me¢m11yshonzmphﬁe¢mpulsand paawnamavsa cahbrzuon CE 44 44 mm Buck regmalm bomsvep 1mm annaaa XSR or xm s 17g: 151/ capacnu between ma CE and 5mes CPH 4 4 mm Charge pumpswﬂcmng node Connedz X5R g1 xm 477m VMrraled nerzrmc capamkw gezwaan Ihe CPH and CPL pms CPL 3 3 mm Charge pumpswﬂcmng node Connedz X5R g1 xm 477m VMrraled nerzrmc capamkw gezwaan Ihe CPH and CPL pms re 1 1 1 Buckleedback mpa Are51slard1w3ei ngm 111a buck pea may gaga mas an sacs ma buck (Mom vanage GNN 32 7 1 Armhﬁergzmsemng nag1n.ea41ava 1ngag1neaaa. enema neaagn GHA a a o H1gns1degatedr1xerompul Cwnamguagamm awasa power MOSFET GHB 17 17 o H1gns1degatedr1xerompul Connedmmegalecﬂme awasa power MOSFET GHC 1a 1a 0 H1gns1degatedr1xerompul Connedmmegalecﬂme awasa power MOSFET GLA 11: 1s 0 st1degzledv1veroumm annagugma gamma 1Ws1depowei 1110er GLE 15 15 o st1degzledv1veroumm annagugma gamma 1Ws1depowei 1110er GLC 20 2s 0 st1degzledv1veroumm annagugma gamma 1Ws1depowei 1110er 1DR1VE 30 7 1 Gaesnm Mom cunemselung ms p1n1sa71e1e11npmpmsetkyyan enama neaagn 1qu 37 37 1 H1gns1de gaa smegma man This pmcmvdsihempmonm awasagaagnm was 39 39 1 H1gns1de gaa smegma man This pmcmvdsihempmonm awasagaagnm WHC 41 41 1 H1gns1de gaa smegma man This pmcmvdsihempmonm awasagaagnm (1) PWR : puwergl =1npm,o : mnpuL NC = no connedlon‘ OD: open—dramoutpm SubmtDacumentanon Feedback 5 Fmducl Fo1derL1r1ls DRV8320 DRV8320R DRV8323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output

Submit Documentation Feedback

9

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

1

36

2

35

3

34

4

33

5

32

6

31

Thermal

7 Pad 30

8

29

9

28

10

27

11

26

12

25

1

36

2

35

3

34

4

33

5

32

6

31

Thermal

7 Pad 30

8

29

9

28

10

27

11

26

12

25

S NB

SPB

GLB

S HB

GHB

GHC

S HC

GLC

S PC

S NC

S OC

S OB

DRV8323RH RGZ Package

48-Pin VQFN With Exposed Thermal Pad

Top View

DRV8323RS RGZ Package

48-Pin VQFN With Exposed Thermal Pad

Top View

FB DVDD FB DVDD

PGND

AGND

PGND

AGND

CPL

CAL

CPL

CAL

CPH

ENABLE

CPH

ENABLE

VCP

GAIN

VCP

nSCS

VM VDS VM SCLK

VDRAIN

IDRIVE

VDRAIN

SDI

GHA

MODE

GHA

SDO

SHA

nFAULT

SHA

nFAULT

GLA

DGND

GLA

DGND

SPA

VREF

SPA

VREF

SNA

SOA

SNA

SOA

Not to scale Not to scale

Pin Functions—48-Pin DRV8323R Devices

TYPE(1)

DESCRIPTION

N AM E

NO.

DRV8323RH

DRV8323RS

AGND 35 35 PWR Device analog g round. Connect to system g r ound.

BGND 43 43 PWR Buck r eg ulator g round. Connect to system g r ound.

CAL 34 34 I Amplifier calibration input. Set logic hig h to internally short amplifier inputs and perform auto offset calibration.

CB

44

PWR

Buck r eg ulator bootstr ap input. Connect a X5R or X7R, 0.1-µF, 16-V, capacitor between the CB and SW pins.

CPH

4

PWR

Char g e pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.

CPL

3

PWR Char g e pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.

DGND 27 27 PWR Device g round. Connect to system g r ound.

DVDD 36 36 PWR 3.3-V internal r eg ulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins.

This reg ul ator can source up to 30 mA externally.

ENABLE 33 33 I

Gate driver enable. When this pin is logic low the device g oes to a low-power sleep mode. An 8 to 40-µs low pulse can be

used to reset fault conditions.

FB

1

I

Buck feedback input. A r esistor divider from the buck post inductor output to this pin sets the buck output vol tag e.

GAIN

32

—

I

Amplifier g ain setti ng . The pin is a 4 level input pin set by an external resistor .

GHA

8

O

High-side g ate driver output. Connect to the g ate of the hi g h-side power MOSFET.

GHB 17 17 O High-side g ate driver output. Connect to the g ate of the hi g h-side power MOSFET.

GHC 18 18 O High-side g ate driver output. Connect to the g ate of the hig h-side power MOSFET.

GLA

10

O

Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

GLB

15

O

Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

GLC

20

O

Low-side g ate driver output. Connect to the g ate of the low-side power MOSFET.

IDRIVE 30 — I Gate dr i ve output current setti ng . This pin is a 7 level input pin set by an external resistor .

INHA 37 37 I High-side g ate driver control input. This pin contr ols the output of the hig h-side g ate driver.

INHB

39

I

High-side g ate driver control input. This pin contr ols the output of the hig h-side g ate driver.

INHC

41

I

High-side g ate driver control input. This pin contr ols the output of the hig h-side g ate driver.

INLA

38

I

Low-side g ate driver control input. This pin contr ols the output of the low-side g ate driver.

INLB 40 40 I Low-side g ate driver control input. This pin contr ols the output of the low-side g ate driver.

INLC 42 42 I Low-side g ate driver control input. This pin controls the output of the low-side g ate driver.

MODE

29

—

I

PWM input mode setti ng . This pin is a 4 level input pin set by an exter nal resistor .

NC

46

NC

No internal connection. This pin can be left fl oati ng or connected to system g r ound.

nFAULT

28

OD

Fault indicator output. This pin is pulled logic low duri ng a fault condition and req uir es an external pullup resistor.

S NB

13

48

nSHD

SPB

14

47

V IN

GLB

15

46

NC

S HB

16

45

SW

GHB

17

44

CB

GHC

18

43

BGN

S HC

19

42

IN LC

GLC

20

41

IN HC

S PC

21

40

INLB

S NC

22

39

INHB

S OC

23

38

INLA

S OB

24

37

INHA

13

48

nSHD

14

47

V IN

15

46

NC

16

45

SW

17

44

CB

18

43

BGN

19

42

IN LC

20

41

IN HC

21

40

INLB

22

39

INHB

23

38

INLA

24

37

INHA

I TEXAS DRV8320, DRV8320R INSTRUMENTS www. .mm pm No. nRvmmH nnvmms 7 32 SeHaW mama A‘ogm‘owonlms pmmm smz‘ mwuzcemmmam Buckshumcmn mpul name and dxsamempul(mghvouagelo‘eianl) mm puHupcurvenlsoume FuH \mman" 25v Lemme currenl 5mm zrrunnev mum Canned m me \wsxde power MOSFET source and mgnsme ov me cunem 5mm Lemme currenl 5mm zrrunnev mum Canned m me \wsxde my MOSFET source and mgnsme ov me cunem 5mm mum Pad r—wa Mustbecanneded Kagvound 10 Submt Docunentanon Feedbacﬁ Cnpy ngm© 201772022 Texas \rstrumenls \nmrpualed Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

10

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Pin Functions—48-Pin DRV8323R Devices (continued)

TYPE(1)

DESCRIPTION

N AM E

NO.

DRV8323RH

DRV8323RS

nSCS — 32 I Serial chip select. A logic low on this pin enables serial interface communication.

nSHDN 48 48 I Buck shutdown input. Enable and disable input (hig h voltag e tolerant). Internal pullup current source. Pull lower than 1.25 V

to disable. Float to enable. Establish input undervoltag e lockout wi t h two r esistor divider .

PGND

2

PWR

Device power g r ound. Connect to system g r ound.

SCLK

—

31

I

Serial clock input. Serial data is shifted out and captur ed on the c orr espondi ng rising and falling edge on this pin.

SDI — 30 I Serial data input. Data is captured on the falling edg e of the SCLK pin.

SDO — 29 OD Ser ial data output. Data is shifted out on the rising edg e of the SCLK pin. This pin req ui res an external pullup resistor.

SHA

9

I

High-side source sense input. Connect to the hig h-side power MOSFET source.

SHB

16

I

High-side source sense input. Connect to the hig h-side power MOSFET source.

SHC

19

I

High-side source sense input. Connect to the hig h-side power MOSFET source.

SNA 12 12 I Cur rent sense amplifier input. Connect to the low-side of the cur rent shunt resistor .

SNB 13 13 I Cur rent sense amplifier input. Connect to the low-side of the cur rent shunt resistor .

SNC

22

I

Current sense amplifier input. Connect to the low-side of the current shunt resistor.

SOA

25

O

Current sense amplifier output.

SOB

24

O

Current sense amplifier output.

SOC 23 23 O Current sense amplifier output.

SPA 11 11 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET sour ce and hig h-side of the current shunt

resistor .

SPB 14 14 I

Low-side current shunt amplifier input. Connect to the low-side power MOSFET sour ce and hig h-side of the curr ent shunt

resistor .

SPC 21 21 I Low-side cur rent shunt amplifier input. Connect to the low-side power MOSFET source and hi g h-side of the cur rent shunt

resistor .

SW

45

O

Buck switch node. Connect this pin to an inductor , diode, and the CB bootstrap capacitor .

VCP

5

PWR

Char g e pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.

VDRAIN

7

I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.

VDS 31 — I VDS monitor trip point setti ng . This pin is a 7 level input pin set by an external resistor.

VIN

47

PWR

Buck reg ulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.

VM

6

PWR

Gate driver power supply input. Connect to the bri dg e power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and

g r eater then or eq ual to 10-uF local capacitance between the VM and PGND pins.

VREF 26 26 PWR Current sense amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between

the VREF and AGND pins.

Ther mal Pad

PWR

Must be connected to g round

I TEXAS INSTRU M E NTS www.li.com DRV8320, DRV8320R 8323R Powersupplypmvouage (VM) TransenIZOU-nsmgh-sme gace dnve pm vonage (GHX) Conlmuousmgh-sde source sense pm vollage(SHx) Bootstrap pm vanagewmn respecno swans) Swmcmng nude pmquage‘e§than 30-nstransems(SW) OperalmgJunchonlemperamre‘ T Smrage temperature. T 7.2 ESD Ratings chp + 0.5 V+5 1m Charged-device mode‘ (cam perJEDEC specmcanun JESD22-C1m 11000 copyngmcc) 201772022, Texas \nstrumenls \noorpaated SubmtDocumentatmn Feedback 11 Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D– FEBR UARY 2017 – R E VI SED MAR CH 2022

www.ti.com

Submit Documentation Feedback

11

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

7

Specifications

7.1

Absolute Maximum Ratings

at TA = –40°C to +125°C (unless otherw ise noted)(1)

MIN

MAX

UNIT

G ATE DRIVER

Power supply pin voltage (VM)

–0.3

65

V

Voltage differential between ground pins (AGND, BGND, DGND, PGND)

–0.3

0.3

V

MOSFET drain sense pin voltage (VDRAIN) –0.3 65 V

Charge pump pin voltage (CPH, VCP) –0.3 VVM + 13.5 V

Charge pump negative-switching pin voltage (CPL)

–0.3

VVM

V

Internal logic regulator pin voltage (DVDD) –0.3 3.8 V

Digital pin voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS,

SCLK, SDI, SDO, VDS) –0.3 5.75 V

Continuous high-si d e gate drive pin voltage (GHx)

–5(2)

V

VCP

+ 0.5

V

Transient 200-ns high-si d e gate dri ve pin voltage (GHx)

–7

VVCP + 0.5

V

High-si d e gate drive pin voltage with respect to SHx (GHx) –0.3 13.5 V

Continuous high-si d e source sense pin voltage (SHx)

–5

(2)

V

VM

+ 5

V

Transient 200-ns high-si d e source sense pin voltage (SHx) –7 VVM + 7 V

Continuous low-si d e gate drive pin voltage (GLx) –0.5 13.5 V

Gate dri ve pin source current (GHx, GLx)

Internally limited

A

Gate dri ve pin si n k current (GHx, GLx)

Internally limited

A

Continuous low-si d e source sense pin voltage (SLx) –1

1

V

Transient 200-ns low-si d e source sense pin voltage (SLx) –3

3

V

Continuous input pin voltage (SNx, SPx)

–1

1

V

Transient 200-ns input pin voltage (SNx, SPx) –3

3

V

Reference input pin voltage (VREF) –0.3 5.75 V

output pin voltage (SOx)

–0.3

VVREF + 0.3

V

BUCK REGULATOR

Power supply pin voltage (VIN) –0.3 65 V

Shutdown control pin voltage (nSHDN) –0.3

V

VIN V

Voltage feedback pin voltage (FB)

–0.3

7

V

Bootstrap pin voltage with respect to SW (CB)

–0.3

7

V

Switching node pin voltage (SW) –0.3

V

VIN V

Switching node pin voltage less than 30-ns transients (SW)

–2

V

VIN

V

DRV832x

Operating junction temperature, TJ

–40

150

°C

Storage temperature, Tstg

–65

150

°C

(1)

S tre sse s beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. T h ese are st re ss ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those i ndi cat ed under Recommended

Operating Conditions. Exposure to absolute-m axi mum -rated conditions for extended periods may affect device rel i ability.

(2)

Continuous high-si d e gate pin (GHx) and phase node pin voltage (SHx) should be limited to –2 V minimum for an absolute m aximum of

65 V on VM. At 60 V and lower, the full specification of –5 V continuous on GHx and SHx is allowable.

7.2

ESD Ratings

VALUE

UNIT

V(ESD) Electrostatic

discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000

V

Charged-device model (CDM), per JEDEC specification JE SD22 -C1 01 (2)

±1000

(1)

JEDEC document JEP155 states that 500-V HBM allows sa f e manufacturing with a standard ESD control process. Pins listed as ±2000

V may actually have h i gher performance.

(2)

JEDEC document JEP157 states that 250-V CDM allows sa f e manufacturing with a standard ESD control process. Pins listed as ±500 V

may actually have higher performance.

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.cam a‘ TA = ~40“C to +125°C un‘ess otherwise noted Fowermpp‘yvmtageWM) BUCK REGULATOR V Shumuwn contm‘mputvo‘mgemSHDN) TA Operahng ammennemperamre 7.4 Thermal Information Junchon-Io-case (mum) thermal res stanca 12 Submt Docunentanon Feedbacﬁ Cnpy ngm© 201772022 Texas \rstrumenls \nmrpualed Fruducl Fomeerbs DRV8320 DRV8320R DRV5323 DRV8523R

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

12

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

7.3

Re comme nded Operating Conditions

at TA = –40°C to +125°C (unless otherw ise noted)

MIN

MAX

UNIT

G ATE DRIVER

V

VM

Power supply voltage (VM)

6

60

V

VI Input voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS,

SCLK, SDI, VDS)

0

5.5 V

f

PWM Applied PWM signal (INHx, INLx)

0

200(1)

kHz

I

GATE_HS High-si d e average gate drive current (GHx)

0

25(1)

mA

I

GATE_LS Low-si d e average gate dri ve current (GLx)

0

25

(1)

mA

I

DVDD

External load current (DVDD)

0

30

(1)

mA

V

VREF

Reference voltage input (VREF)

3

5.5

V

I

SO

output current (SOx)

0

5

mA

V

OD Open drain pullup voltage (nFAULT , SDO)

0

5.5 V

I

OD Open drain output current (nFAULT, SDO)

0

5

mA

BUCK REGULATOR

V

VIN

Power supply voltage (VIN)

4

60 V

VnSHDN

Shutdown control input voltage (nSHDN)

0

60

V

DRV832x

TA

Operating ambient temperature

–40

125

°C

(1) Power dissipation and thermal limits m u st be observed

7.4

The rmal Information

THERMAL M E TR I C(1)

DRV832x

UNIT

RTV

(WQFN)

RHA

(VQFN)

RTA

(WQFN)

RGZ

(VQFN)

32 PINS

40 PINS

48 PINS

RθJA Junction-to-ambient thermal resistance 32.9 30.1 32.1 26.6 °C/W

RθJC(t op) Junction-to-ca se (top) thermal resistance 15.8 16.7 11 13.9 °C/W

R

θJB

Junction-to-board thermal resistance

6.8

9.9

7.1

9.2

°C/W

ψJT Junction-to-top characterization parameter 0.2 0.5 0.1 0.3 °C/W

ψJB Junction-to-board characterization parameter 6.8 9.9 7.1 9.1 °C/W

R

θJC(bot)

Junction-to-ca se (bottom) thermal resistance

2.1

2.2

2.1

2

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

INSTRU M E NTS DRV8320, DRV8320R 8323R a‘ TA = ~40“C to +1Z5°C, VVM = 6 m 60 V unless omerw \se noled VM opemnng mpp‘y current v = 24 v‘ ENABLE : 3.3 v, INHx/INLx = u v ENABLE = uV‘ V : 24 V‘TA :12?!) Tumun Mme v > V , ENABLE : 3 3 V m outputs ready VCF opemnng voltage mm respecuu VM V =EV‘I/CV =Um10mA Puudown reestance Inlemalpquownlu AGND Inputmode 1 voHage TxedloAGND Inputmode 3voHage 75 m 1 5%uedmAGND Oulpmmgmmpedance‘eakage v =5v Copy ngm© 201772022, Texas \nstrumenls moorpaated Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR SubmtDocumentanon Feedback 13

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D– FEBR UARY 2017 – R E VI SED MAR CH 2022

www.ti.com

Submit Documentation Feedback

13

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

7.5

Electrical Characteristics

at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLIES (DVDD, VCP, VM)

I

VM

VM operating supply current

VVM = 24 V, ENABLE = 3.3 V, INHx/INLx = 0 V

10.5 14

mA

IVMQ

VM sleep mode supply current

ENABLE = 0 V, V

VM

= 24 V, T

A

= 25°C

12

20

µA

ENABLE = 0 V, VVM = 24 V, TA = 125°C

(1)

50

tRST

(1)

Reset pulse time ENABLE = 0 V period to reset faults

8

40

µs

tWAKE

Turnon time

VVM > VUVLO , ENABLE = 3.3 V to outputs ready

1

ms

t

SLEEP

Turnoff time ENABLE = 0 V to device sleep mode

1

ms

V

DVDD

DVDD regulator voltage IDVDD = 0 to 30 mA

3

3.3 3.6

V

VVM = 13 V, IVCP = 0 to 25 mA 8.4 11 12.5

V

VCP operating voltage

V

VM

= 10 V, I

VCP

= 0 to 20 mA

6.3

9

10

VVM = 8 V, IVCP = 0 to 15 mA 5.4

7

8

VCP

with respect to VM

VVM = 6 V, IVCP = 0 to 10 mA

4

5

6

LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)

V

IL

Input logic l ow voltage

0

0.8

V

IH Input logic high voltage

1.5

5.5

V

VHYS

Input logic hysteresis

100

mV

I

IL

Input logic l ow current VVIN = 0 V –5

5

µA

I

IH

Input logic high current VVIN = 5 V

50 70

µA

R

PD

Pulldown resistance

To AGND

100

kΩ

t

PD

Propagation delay

INHx/INLx transition to GHx/GLx transition

150

ns

FOUR-LEVEL H/W INPUTS (GAIN, MODE)

V

I1 Input mode 1 voltage Tied to AGND

0

V

I2

Input mode 2 voltage

45 kΩ ± 5% to tied AGND

1.2

V

I3

Input mode 3 voltage Hi -Z

2

V

I4 Input mode 4 voltage Tied to DVDD 3.3 V

R

PU Pullup resistance Internal pullup to DVDD 50 kΩ

RPD

Pulldown resistance

Internal pulldown to AGND

84

kΩ

SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)

V

I1

Input mode 1 voltage

Tied to AGND

0

V

I2

Input mode 2 voltage

18 kΩ ± 5% tied to AGND

0.5

V

VI3

Input mode 3 voltage

75 kΩ ± 5% tied to AGND

1.1

V

I4 Input mode 4 voltage Hi-Z 1.65 V

V

I5 Input mode 5 voltage 75 kΩ ± 5% tied to DVDD 2.2 V

V

I6

Input mode 6 voltage

18 k

Ω

± 5% tied to DVDD

2.8

V

I7

Input mode 7 voltage Tied to DVDD 3.3 V

R

PU

Pullup resistance

Internal pullup to DVDD

73

kΩ

R

PD

Pulldown resistance

Internal pulldown to AGND

73

kΩ

OPEN DRAIN OUTPUTS (nFAULT, SDO)

V

OL Output logic low voltage IO = 5 mA 0.1

V

I

OZ

Output high impedance leakage

V

O

= 5 V

–2

2

µA

(1) Specified by design and characterization data

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com V =10‘|\'<:p:0|dzuma v="EV‘I/CV" =um10ma="" v="" :10v,|="" ls="UszmA" idrivefihs="" orldrivepils="0010b" idrivefihs="" orldrivepils="0100b" idrivefihs="" orldrivepils="0110b" idrive="Hw-Z" idrive="18" m="" 1="" 5%uedm="" dvdd="" submt="" docunentanon="" feedbacﬁ="" cnpy="" ngm©="" 201772022="" texas="" \rstrumenls="" \nmrpualed="" fruducl="" fomeerbs="" drv8320="" drvbszdr="" drvb323="" drvaszsr="">

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

14

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Electrical Characteristics (continued)

at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

G ATE DRIVERS (GHx, GLx)

VVM = 13 V, IVCP = 0 to 25 mA

8.4

11

12.5

V VGSH (1) High-side gate drive voltage

with respect to SHx

VVM = 10 , IVCP = 0 to 20 mA

6.3

9

10

VVM = 8 V, IVCP = 0 to 15 mA 5.4

7

8

VVM = 6 V, IVCP = 0 to 10 mA

4

5

6

V

VM

= 12 V, I

VGLS

= 0 to 25 mA

9

11

12

V VGSL

(1) Low-side gate drive voltage

with respect to PGND

VVM = 10 V, IVGLS = 0 to 20 mA

7.5

9

10

VVM = 8 V, IVGLS = 0 to 15 mA 5.5

7

8

VVM = 6 V, IVGLS = 0 to 10 mA

4

5

6

tDEAD

Gate drive

dead time

SPI Device

DEAD_TIME = 00b 50

ns

DEAD_TIME = 01b 100

DEAD_TIME = 10b 200

DEAD_TIME = 11b

400

H/W Device

100

tDRIVE

Peak current

gate dri ve time

SPI Device

TDRIVE = 00b 500

ns

TDRIVE = 01b

1000

TDRIVE = 10b 2000

TDRIVE = 11b 4000

H/W Device

4000

IDRIVEP

Peak source

gate current

SPI Device

IDRIVEP_HS or IDRIVEP_LS = 0000b 10

mA

IDRIVEP_HS or IDRIVEP_LS = 0001b 30

IDRIVEP_HS or IDRIVEP_LS = 0010b

60

IDRIVEP_HS or IDRIVEP_LS = 0011b

80

IDRIVEP_HS or IDRIVEP_LS = 0100b

120

IDRIVEP_HS or IDRIVEP_LS = 0101b 140

IDRIVEP_HS or IDRIVEP_LS = 0110b

170

IDRIVEP_HS or IDRIVEP_LS = 0111b 190

IDRIVEP_HS or IDRIVEP_LS = 1000b 260

IDRIVEP_HS or IDRIVEP_LS = 1001b 330

IDRIVEP_HS or IDRIVEP_LS = 1010b

370

IDRIVEP_HS or IDRIVEP_LS = 1011b 440

IDRIVEP_HS or IDRIVEP_LS = 1100b 570

IDRIVEP_HS or IDRIVEP_LS = 1101b

680

IDRIVEP_HS or IDRIVEP_LS = 1110b

820

IDRIVEP_HS or IDRIVEP_LS = 1111b 1000

H/W Device

IDRIVE = Tied to AGND 10

IDRIVE = 18 k

Ω

± 5% tied to AGND

30

IDRIVE = 75 kΩ ± 5% tied to AGND 60

IDRIVE = Hi-Z

120

IDRIVE = 75 kΩ ± 5% tied to DVDD

260

IDRIVE = 18 kΩ ± 5% tied to DVDD

570

IDRIVE = Tied to DVDD 1000

I TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.li.com IDRIVENiHS orlDRIVENiLS = 0010b IDRIVENiHS orlDRIVENiLS = 0100b IDRIVENiHS orlDRIVENiLS = 0110b IDRIVE=18 m 1 5%uedm DVDD Source currem aﬂen Gale strong pquuwn current GHx m SHx and GLxm PGND V ; =U.5V,G A=20V/V Common mudempmrange Inputoﬂse‘error VV:Vn=0V,CAL=3.3V,VREF=3.3V copyngmcc) 201772022, Texas \nstrumenls \noorpaated SubmtDocumentatmn Feedback 15 Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D– FEBR UARY 2017 – R E VI SED MAR CH 2022

www.ti.com

Submit Documentation Feedback

15

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Electrical Characteristics (continued)

at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IDRIVEN

Peak si n k

gate current

SPI Device

IDRIVEN_HS or IDRIVEN_LS = 0000b 20

mA

IDRIVEN_HS or IDRIVEN_LS = 0001b

60

IDRIVEN_HS or IDRIVEN_LS = 0010b

120

IDRIVEN_HS or IDRIVEN_LS = 0011b 160

IDRIVEN_HS or IDRIVEN_LS = 0100b

240

IDRIVEN_HS or IDRIVEN_LS = 0101b

280

IDRIVEN_HS or IDRIVEN_LS = 0110b

340

IDRIVEN_HS or IDRIVEN_LS = 0111b 380

IDRIVEN_HS or IDRIVEN_LS = 1000b

520

IDRIVEN_HS or IDRIVEN_LS = 1001b 660

IDRIVEN_HS or IDRIVEN_LS = 1010b 740

IDRIVEN_HS or IDRIVEN_LS = 1011b 880

IDRIVEN_HS or IDRIVEN_LS = 1100b

1140

IDRIVEN_HS or IDRIVEN_LS = 1101b 1360

IDRIVEN_HS or IDRIVEN_LS = 1110b 1640

IDRIVEN_HS or IDRIVEN_LS = 1111b

2000

H/W Device

IDRIVE = Tied to AGND 20

IDRIVE = 18 kΩ ± 5% tied to AGND 60

IDRIVE = 75 kΩ ± 5% tied to AGND 120

IDRIVE = Hi-Z 240

IDRIVE = 75 kΩ ± 5% tied to DVDD 520

IDRIVE = 18 kΩ ± 5% tied to DVDD

1140

IDRIVE = Tied to DVDD

2000

IHOLD

Gate holding current

Source current after tDRIVE

10

mA

Sink current after tDRI VE 50

ISTRONG

Gate strong pulldown current

GHx to SHx and GLx to PGND

2

A

R

OFF

Gate hold off re si st o r GHx to SHx and GLx to PGND 150 kΩ

CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)

GCSA

Amplifier gain

SPI Device

CSA_GAIN = 00b 4.85

5

5.15

V/V

CSA_GAIN = 01b

9.7

10

10.3

CSA_GAIN = 10b 19.4 20 20.6

CSA_GAIN = 11b 38.8 40 41.2

H/W Device

GAIN = Tied to AGND

4.85

5

5.15

GAIN = 47 k

Ω

± 5% tied to AGND

9.7

10

10.3

GAIN = Hi-Z 19.4 20 20.6

GAIN = Tied to DVDD 38.8 40 41.2

tSET

(1)

Settling time to ±1%

V

O_STEP

= 0.5 V, G

CSA

= 5 V/V

150

ns

VO_STEP = 0.5 V, GCSA = 10 V/V 300

VO_STEP = 0.5 V, GVSA = 20 V/V

600

V

O_STEP

= 0.5 V, G

CSA

= 40 V/V

1200

VCOM

Common mode input range

–0.15

0.15

V

DIFF Differential m ode input range

–0.3

0.3

V

VOFF

Input offset error

VSP = VSN = 0 V, CAL = 3.3 V, VREF = 3.3 V

–4

4

mV

V

DRIFT

(1)

Drift offset

V

SP

= V

SN

= 0 V

10

µV/°C

VLINEAR SOx output voltage l i ne ar range

0.25 VVREF

– 0.25

V

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com HIWDevme v y:v h =ov‘ CAL=3,3V SOxumpmslewlate 60-pF‘oad Umtygam bandwuﬂh 60-pF‘oad Negauve dampmg voltage VDsiLVL : 0001b VDS: Twedlu AGND VDS : 75 m t 5% had to AGND VDS : 75 m t 5% had to DVDD HIW Dew Ce 15 Submt Docunentanon Feedbacﬁ Cnpy ngm© 201772022 Texas \rstrumenls \nmrpualed Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

16

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Electrical Characteristics (continued)

at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VBIAS

SOx output voltage

bias

SPI Device VSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 0b VVREF – 0.3

V

VSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 1b

VVREF / 2

H/W Device

VSP = VSN = 0 V, CAL = 3.3 V

VVREF / 2

I

BIAS

SPx/SNx input bias current VREF_DIV = 1b 100

µA

V

SLEW

(1)

SOx output sl e w rate

60-pF load

10

V/µs

I

VREF

VREF input current

V

VREF

= 5 V

2

3

mA

UGB

(1)

Unity gain bandwidth

60-pF load

1

MHz

PROTECTION CIRCUITS

VUVLO

VM undervoltage lockout

VM falling, UVLO report

5.4

5.6

5.8

V

VM rising, UVLO recovery 5.6 5.8

6

V

UVLO_HYS

VM undervoltage hysteresis Rising to falling threshold 200 mV

t

UVLO_DEG VM undervoltage deglitch ti me VM falling, UVLO report 10 µs

VCPUV Charge pump undervoltage

lockout VCP falling, CPUV report VVM + 2.8 V

VGS_CLAMP

High-si d e gate clamp Positive clamping voltage 15 16.5 18

V

Negative clamping voltage

–0.7

VVDS_OCP

VDS overcurrent

tri p voltage

SPI Device

VDS_LVL = 0000b 0.06

V

VDS_LVL = 0001b

0.13

VDS_LVL = 0010b

0.2

VDS_LVL = 0011b

0.26

VDS_LVL = 0100b 0.31

VDS_LVL = 0101b 0.45

VDS_LVL = 0110b

0.53

VDS_LVL = 0111b 0.6

VDS_LVL = 1000b 0.68

VDS_LVL = 1001b 0.75

VDS_LVL = 1010b 0.94

VDS_LVL = 1011b 1.13

VDS_LVL = 1100b

1.3

VDS_LVL = 1101b

1.5

VDS_LVL = 1110b 1.7

VDS_LVL = 1111b 1.88

H/W Device

VDS = Tied to AGND

0.06

VDS = 18 k

Ω

± 5% tied to AGND

0.13

VDS = 75 kΩ ± 5% tied to AGND

0.26

VDS = Hi-Z

0.6

VDS = 75 kΩ ± 5% tied to DVDD

1.13

VDS = 18 kΩ ± 5% tied to DVDD 1.88

VDS = Tied to DVDD Disabled

tOCP_DEG

VDS and VSENSE

overcurrent

deglitch time

SPI Device

OCP_DEG = 00b

2

µs

OCP_DEG = 01b

4

OCP_DEG = 10b

6

OCP_DEG = 11b

8

H/W Device

4

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D– FEBR UARY 2017 – R E VI SED MAR CH 2022

www.ti.com

Submit Documentation Feedback

17

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Electrical Characteristics (continued)

at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VSEN_OCP

VSENSE overcurrent

tri p voltage

SPI Device

SEN_LVL = 00b 0.25

V

SEN_LVL = 01b

0.5

SEN_LVL = 10b

0.75

SEN_LVL = 11b

1

H/W Device

1

tRETRY

Overcurrent retry

time

SPI Device

TRETRY = 0b

4

ms

TRETRY = 1b

50

μs

H/W Device

4

ms

TOTW

(1)

Thermal warning temperature

Die temperature, TJ

130

150

165

°C

T

OTSD

(1)

Thermal shutdown temperature Die temperature, TJ 150 170 185

°C

T

HYS

(1)

Thermal hysteresis Die temperature, TJ 20 °C

BUCK REGULATOR SUPPLY (VIN)

InSHDN

Shutdown supply current

VnSHDN = 0 V

1

3

µA

IQ Operating quiescent current VVIN = 12 V, no load; not switching 28 µA

VVIN_UVLO VIN undervoltage lockout

threshold

VIN Rising

4

V

VIN Falling

3

BUCK REGULATOR SHUTDOWN (nSHDN)

VnSHDN_TH Rising nSHDN threshold

1.05 1.25 1.38

V

InSHDN

Input current VnSHDN = 2.3 V –4.2

µA

VnSHDN = 0.9 V –1

I

nSHDN_HYS

Hyst e re si s current

–3 µA

BUCK REGULATOR HIGH-SIDE MOSFET

R

DS_ON

MOSFET on resistance

V

VIN

= 12 V, V

CB

to V

SW

= 5.8 V, T

A

= 25°C

900

mΩ

BUCK REGULATOR VOLTAGE REFERENCE (FB)

VFB Feedback voltage

0.747 0.765 0.782

V

BUCK REGULATOR CURRENT LIMIT

ILIMIT Peak current limit VVIN = 12 V, TA = 25°C 1200

mA

1700

BUCK REGULATOR SWITCHING (SW)

f

SW

Switching frequency

595

700

805

kHz

D

MAX

Maximum duty cycle

96%

BUCK REGULATOR THERMAL SHUTDOWN

T

SHDN

(1) Thermal shutdown threshold

170

°C

T

HYS

(1)

Thermal shutdown hysteresis

10

°C

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com a‘ TA = ~40“C to +1Z5°C, VVM = 6 m 60 V unless omerw \se noled SPI readyaﬂerename VM > UVLO‘ ENABLE: SCLKmImmum mghhme SDI mpul data seluphme ta Submt DoCuIVEm‘aIran Feedbacﬁ Cnpy ngm© 201772022 Texas \rstrumenls \nmrpualed Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

18

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

tCLK

tCLKH

tCLKL

X

MSB

LSB

X

t

SU_SDI

tH _ S DI

Z

MSB

LSB

Z

t

D_SDO

tDIS_nSCS

7.6

SPI Timing Re quirements(1)

at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

MIN NOM MAX

UNIT

SPI (nSCS, SCLK, SDI, SDO)

t

READY

SPI ready after enable

VM > UVLO, ENABLE = 3.3 V

1

ms

tCLK

SCLK minimum period

100

ns

tCLKH

SCLK minimum high ti me

50

ns

t

CLKL SCLK minimum l ow time 50 ns

tSU_SDI

SDI input data setup ti me

20

ns

t

H_SDI

SDI input data hold time 30 ns

t

D_SDO

SDO output data delay time SCLK high to SDO valid 30

ns

t

SU_nSCS nSCS input setup time 50 ns

tH_nSCS

nSCS input hold time

50

ns

t

HI_nSCS

nSCS minimum high time before active l ow 400 ns

t

DIS_nSCS nSCS disable time nSCS high to SDO high impedance 10 ns

(1) Specified by design and characterization data

tHI_nSCS tSU_nSCS

tH_nSCS

nSCS

SCLK

SDI

SDO

Figure 1. SPI S l a ve Mode Timing Diagram

I TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.li.com g E o 5 :2 xi ” 2‘ E 5 m E 5 § § ‘5 ‘5 a a a a > > a a copyngmcc) 201772022, Texas \nstrumenls \nwrpaated SubmtDacumentatmn Feedback 19 Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D– FEBR UARY 2017 – R E VI SED MAR CH 2022

www.ti.com

Submit Documentation Feedback

19

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

DVDD Voltage (V)

Supply Current (mA)

7.7

Typical Characteristics

16 15

14 14

13

12

10 11

8 10

6 9

8

4

TA = -40°C 7

2 TA = 25°C 6

TA = 125°C

0 5

VVM = 6 V

VVM = 24 V

VVM = 60 V

0 10 20 30 40 50 60 -40 -20 0 20 40 60 80

100

120

140

Supply Voltage ( V) D001 Ambient Temperature (°C) D002

Figure 2. Supply Current Ov er VM

24

22

20

18

16

14

12

10

8

6

4 TA = -40°C

TA = 25°C

2 TA = 125°C

0

Figure 3. Supply Current Ov er Temperature

24

22

20

18

16

14

12

10

8

6

4 VVM = 6 V

VVM = 24 V

2 VVM = 60 V

0

0 10 20 30 40 50 60 -40 -20 0 20 40 60 80

100

120

140

Supply Voltage (V) D003 Ambient Temperature (°C) D004

4

3.75

3.5

Figure 4. Sleep Current Ov er VM

TA = -40°C

TA = 25°C

TA = 125°C

4

3.75

3.5

Figure 5. Sleep Current Ov er Temperature

TA = -40°C

TA = 25°C

TA = 125°C

3.25 3.25

3 3

2.75 2.75

2.5 2.5

2.25 2.25

2

0 10 20 30 40 50 60

2

0 10 20 30 40 50 60

0-mA l o ad

Supply Voltage (V) D005

30-mA l oad

Supply Voltage (V) D006

Figure 6. DVDD Voltage Ov er VM Figure 7. DVDD Voltage Ov er VM

DVDD Voltage (V)

Sleep Current ( A)

Supply Current (mA)

Sleep Current ( A)

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.n.com 12 \\\\ m \ \\\ z a 5 5\\\\ 5 E E > > B. \ B. U \\\ U > > _ v by Z — VVM: 8V WM: luv — V M: 13V D D 25 5 7 5 10 12 5 15 17 5 20 225 25 740 720 0 2U 4U 50 80 ‘OD 120 140 Lead Current (mA) AmblentTemperamre (“0) 20 Submt Docunentanan Feedbacﬁ capy ngm© 201772022 Tex$ \rslruments \nmrpuated Fmducl Fomeerls DRV8320 DRV8320R DRV8323 DRV8523R

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

20

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

VCP Voltage (V)

Typical Characteristics (continued)

12

14

10

12

8

10

8

6

4

V

VM

= 6 V

V

VM

= 6 V

2

VVM = 8 V

2 VVM = 8 V

VVM = 10 V

VVM = 13 V

0

2.5

5 7.5 10 12.5 15 17.5 20 22.5 25

-40 -20 0 20 40 60 80

100

120

140

Load Current (mA) D007

Ambient Temperature (°C ) D008

0-mA load

Figure 8. VCP Voltage Ov er Load Figure 9. VCP Voltage Ov er Temperature

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R wwaLcom copyngmcc) 201772022, Texas Inslrumenls \nmrpaated SubmtDacumentanon Feedback 21 Fmducl Fo‘deerls DRV8320 DRV83217R DRV8323 DRVBSZSR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D– FEBR UARY 2017 – R E VI SED MAR CH 2022

www.ti.com

Submit Documentation Feedback

21

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8

Detailed Description

8.1

Overview

The DRV832x family of devices is an integrated 6 to 60-V gate driver for three-phase motor drive applications.

These devices decrease system component count, cost, and complexity by integrating three independent half-

bridge gate drivers, charge pump, and linear regulator for the supply voltages of the high-side and low-side gate

drivers.The device also integrates optional triple current shunt (or current sense) amplifiers and an optional

600-mA buck regulator. A standard serial peripheral interface (SPI) provides a simple method for configuring t he

various device settings and reading fault diagnostic information through an external controller. Alternatively, a

hardware interface (H/W) option allows for configuring the most common settings through fixed external resistors.

The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A

source, 2-A sink peak currents with a 25-mA average output current. A doubler charge pump generates the

supply voltage of the high-side gate drive. This charge pump architecture regulates the VCP output to VVM +

11 V. The supply voltage of the low-side gate driver is generated using a linear regulator from the VM power

supply that regulates to 11 V. A Smart Gate Drive architecture provides the ability to dynamically adjust the

strength of the gate drive output current which lets the gate driver control the VDS switching speed of the power

MOSFET. This feature lets the user remove the external gate drive resistors and diodes, reducing the component

count in the bill of materials (BOM), cost, and area of the printed circuit board (PCB). The architecture also us es

an internal state machine to protect against short-circuit events in the gate driver, control the half-bridge dead

time, and protect against dV/dt parasitic turnon of the external power MOSFET.

The DRV8323 and DRV8323R devices integrate three bidirectional current sense amplifiers for monitoring the

current level through each of the external half-bridges using a low-side shunt resistor. The gain setting of the

current sense amplifier can be adjusted through the SPI or hardware interface. The SPI method provides

additional flexibility to adjust the output bias point.

The DRV8320R and DRV8323R devices integrate a 600-mA buck regulator that can be used to power an

external controller or other logic circuits. The buck regulator is implemented as a separate internal die that can

use either the same or a different power supply than the gate driver.

In addition to the high level of device integration, the DRV832x family of devices provides a wide range of

integrated protection features. These features include power supply undervoltage lockout (UVLO), charge pum p

undervoltage lockout (CPUV), VDS overcurrent monitoring (OCP), gate driver short-circuit detection (GDF), and

overtemperature shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with detailed

information available in the SPI registers on the SPI device version.

The DRV832x family of devices are available in 0.5-mm pin pitch, QFN surface-mount packages. The QFN siz es

are 5 × 5 mm for the 32-pin package, 6 × 6 mm for the 40-pin package, and 7 × 7 mm for the 48-pin package.

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

22

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.2

Functional Block Diagram

VM

>10 µF

0.1 µF

47 nF

1 µF

VM

VCP

CPH

CPL

VCP

Charge

Pump

VCP

HS

VGLS

LS

VM

VDRAIN

GHA

SHA

GLA

30 mA

1 µF

DVDD

AGND

PGND

VGLS

Linear

Regulator

DVDD

Linear

Regulator

Power

Gate Driv er

VCP

HS

VGLS

SLA

VM

GHB

SHB

ENABLE

INHA

INLA

INHB

INLB

INHC

INLC

MOD E

Control

Inputs

Digital

Core

LS

Gate Driv er

VCP

HS

VGLS

LS

Gate Driv er

Fault O ut put

GLB

SLB

GHC

SHC

GLC

SLC

nFAULT

VM

VCC

RPU

IDRIVE

VDS

Figure 10. Block Diagram for DRV8320H

Protection

Smart Gate

Driv e

I TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.li.com Functional Block Diagram (continued) VDRAW GHA SHA VGLS Lmear Regmaw an mA DVDD DVDD 1 F V a mum Core LS Gme Drive RPU Faun Oulpm nFAULT copyngmcc) 201772022, Texas \nstrumenls \nwrpaated SubmtDacumentatmn Feedback 23 Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Functional Block Diagram (continued)

Submit Documentation Feedback

23

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Figure 11. Block Diagram for DRV8320S

VM

VDRAIN

VM

VCP

GHA

HS

1 µF

>10 µF 0.1 µF

CPH

VCP

Charge

Pump

SHA

VGLS

47 nF

CPL GLA

LS

SLA

VGLS

Linear

Regulator

Gate Driv er

VM

30 mA

DVDD

1 µF

AGND

DVDD

Linear

Regulator

Power

VCP

GHB

HS

SHB

PGND

VGLS

ENABLE

Digital

Core

GLB

LS

INHA

SLB

Gate Driv er

INLA

VM

VCP

INHB

Control

Inputs

GHC

HS

INLB SHC

VGLS

INHC

GLC

LS

INLC

SLC

Gate Driv er

VCC

SDI

SPI

Fault Output

nFAULT

RPU

SDO

SCLK

nSCS

Protection

Smart Gate

Driv e

TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com Functional Block Diagram (continued) I; 24 Submt Docunentanon Feedbacﬁ Cnpy ngm© 201772022 Texas \rstrumenls \nmrpualed Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVI S ED MARCH 2022

www.ti.com

Functional Block Diagram (continued)

24

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

VM

>10 µF

0.1 µF

47 nF

1 µF

VM

VCP

CPH

CPL

VCP

Charge

Pump

VCP

HS

VGLS

LS

VDRAIN VM

GHA

SHA

GLA

30 mA

1 µF

DVDD

AGND

PGND

ENABLE

INHA

INLA

INHB

INLB

INHC

INLC

MODE

IDRIVE

VGLS

Linear

Regulator

DVDD

Linear

Regulator

Power

Control

Inputs

Digital

Core

Gate Driv er

VCP

HS

VGLS

LS

Gate Driv er

VCP

HS

VGLS

LS

Gate Driv er

Fault O ut put

SLA

GHB

SHB

GLB

SLB

GHC

SHC

GLC

SLC

nFAULT

VM

VCC

RPU

CIN

VIN

VDS

VIN

nSHDN

CB

0.1 µF

SW

LOUT

600 mA

BGND FB DOUT RFB1

COUT

RFB2

Figure 12. Block Diagram for DRV8320RH

Buck Regulator

(LMR16006X)

Protection

Smart Gate

Driv e

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www om Functional Block Diagram (continued) I; copyngmcc) 201772022, Texas \nstrumenls \noorpaated SubmtDocumentatmn Feedback 25 Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Functional Block Diagram (continued)

Submit Documentation Feedback

25

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

VM

>10 µF

0.1 µF

47 nF

1 µF

VM

VCP

CPH

CPL

VGLS

VCP

Charge

Pump

VGLS

Linear

VCP

HS

VGLS

LS

Gate Driv er

VM

VDRAIN

GHA

SHA

GLA

SLA

30 mA

1 µF

DVDD

AGND

PGND

Regulator

DVDD

Linear

Regulator

Power

VCP

HS

VM

GHB

SHB

ENABLE

INHA

INLA

INHB

INLB

Control

Inputs

Digital

Core

VGLS

LS

Gate Driver

VCP

HS

GLB

SLB

VM

GHC

VCC

RPU

INHC

INLC

SDI

SDO

SCLK

SPI

VGLS

LS

Gate Driv er

Fault O ut put

SHC

GLC

SLC

nFAULT

VCC

RPU

VIN

nSCS

VIN

nSHDN

CB

0.1 µF

SW

LOUT

600 mA

CIN

BGND

DOUT

FB RFB1

COUT

RFB2

Figure 13. Block Diagram for DRV8320RS

Buck Regulator

(LMR16006X)

Protection

Smart Gate

Driv e

TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com Functional Block Diagram (continued) I; 25 Submt Docunentanon Feedbacﬁ Cnpy ngm© 201772022 Texas \rstrumenls \nmrpualed Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVI S ED MARCH 2022

www.ti.com

Functional Block Diagram (continued)

26

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

VM

>10 µF

0.1 µF

47 nF

30 mA

1 µF

VM

VCP

CPH

CPL

DVDD

AGND

PGND

VGLS

VCP

Char g e

Pump

VGLS

Linear

Reg ulator

DVDD

Linear

Reg ulator

Power

VCP

HS

VGLS

LS

Gate Driver

VCP

HS

VGLS

VDRAIN VM

GHA

SHA

GLA

VM

GHB

SHB

ENABLE Digital

Core LS

GLB

INHA

INLA

INHB

INLB

INHC

Contr ol

Inputs

Gate Driver

VCP

HS

VGLS

LS

VM

GHC

SHC

GLC

0.1 µF

VCC

INLC

MODE

IDRIVE

VDS

GAIN

VREF

SOC

SOB

SOA

CAL

Gate Driver

Fault Output

AV

VCC

RPU

nFAULT

SPC

SNC

SPB

SNB

SPA

SNA

RSEN

Figure 14. Block Diagram for DRV8323H

Output

Offset

Bias

Protection

Smart Gate

Drive

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.li.com Functional Block Diagram (continued) I; copyngmcc) 201772022, Texas \nstrumenls \noorpaated SubmtDocumentatmn Feedback 27 Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Functional Block Diagram (continued)

Submit Documentation Feedback

27

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

VM

>10 µF

0.1 µF

47 nF

1 µF

VM

VCP

CPH

CPL

VCP

Char g e

Pump

VCP

HS

VGLS

LS

VDRAIN VM

GHA

SHA

GLA

30 mA

1 µF

DVDD

AGND

PGND

ENABLE

INHA

INLA

INHB

INLB

INHC

VGLS VGLS

Linear

Reg ulator

DVDD

Linear

Reg ulator

Power

Contr ol

Inputs

Digital

Core

Gate Driver

VCP

HS

VGLS

LS

Gate Driver

VCP

HS

VGLS

LS

VM

GHB

SHB

GLB

VM

GHC

SHC

GLC

VCC

RPU

INLC

SDI

SDO

SCLK

SPI

Gate Driver

Fault Output

VCC

RPU

nFAULT

0.1 µF

VCC

nSCS

VREF

SOC

SOB

SOA

CAL

SPC

AV SNC

SPB

AV SNB

SPA

AV SNA

RSEN

Figure 15. Block Diagram for DRV 8 323S

Output

Offset

Bias

Protection

Smart Gate

Drive

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

28

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Functional Block Diagram (continued)

VM

>10 µF 0.1 µF

47 nF

1 µF

VM

VCP

CPH

CPL

DGND

VGLS

VCP

Char g e

Pump

VGLS

Linear

Reg ulator

VCP

HS

VGLS

LS

Gate Driver

VDRAIN VM

GHA

SHA

GLA

VM

30 mA

1 µF

DVDD

AGND

PGND

ENABLE

DVDD

Linear

Reg ulator

Power

Digital

Core

VCP

HS

VGLS

LS

GHB

SHB

GLB

INHA

INLA

INHB

INLB

INHC

Contr ol

Inputs

Gate Driver

VCP

HS

VGLS

LS

Gate Driver

GHC

SHC

GLC

VM

VCC

0.1 µF

CIN

VCC

VIN

INLC

MODE

IDRIVE

VDS

GAIN

VREF

SOC

SOB

SOA

CAL

VIN

nSHDN

BGND

Output

Offset

Bias

Fault Output

AV

RPU

nFAULT

SPC

SNC

SPB

SNB

SPA

SNA

CB

SW

FB

RSEN

0.1 µ F

DOUT

RSEN

LOUT

RFB1

RFB2

RSEN

600 mA

COUT

Figure 16. Block Diagram for DRV8323RH

Buc k Reg ul ator

(LMR16006X)

Protection

Smar t Gate

Drive

TEXAS INSTRUMENTS DRV8320, DRV832DR 8323R www.u.:om Functional Block Diagram (continued) I; L Copyngm© 201772022, Texa Inslrumems \nmrpo‘ated SubmtDocumentation Feedback 29 Pmducl Foldeerls DRV8320 DRV8320R DRV6323 DRV8323R

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Functional Block Diagram (continued)

Submit Documentation Feedback

29

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

VM

>10 µF 0.1 µF

47 nF

30 mA

1 µF

VM

VCP

CPH

CPL

DGND

DVDD

AGND

PGND

VGLS

VCP

Char g e

Pump

VGLS

Linear

Reg ulator

DVDD

Linear

Reg ulator

Power

VCP

HS

VGLS

LS

Gate Driver

VCP

HS

VDRAIN VM

GHA

SHA

GLA

VM

GHB

SHB

ENABLE

INHA

Digital

Core

VGLS

LS

GLB

VCC

INLA

INHB

INLB

INHC

INLC

Contr ol

Inputs

Gate Driver

VCP

HS

VGLS

LS

Gate Driver

GHC

SHC

GLC

VM

VCC

RPU

SDI

SDO

SCLK

SPI

Fault Output

RPU

nFAULT

0.1 µF

VCC

VIN

nSCS

VREF

SOC

SOB

SOA

CAL

SPC

AV SNC

SPB

AV SNB

SPA

AV SNA

RSEN

CIN

VIN

BGND

CB

0.1 µF

SW

DOUT

FB

LOUT

RFB1

RFB2

600 mA

COUT

Figure 17. Block Diagram for DRV8323RS

nSHDN

Buck Reg ulator

(LMR16006X)

Output

Offset

Bias

Protection

Smart Gate

Drive

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com SNAand FGND Sense shunt resstor SNC and PGND Sense shunt resstor BGND X5RurX7R‘1 m 10 uF,VM-ramdcapacnur 30 Submt Docunentanon Fesdbact Cnpy ngm© 201772022 Texas \rstrumenls \nmrpualed Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

30

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.3

Feature Description

Table 1 lists the recommended values of the external components for the gate driver and the buck regulator.

Table 1. DRV832x External Components

COMPONENTS PIN 1 PIN 2 RECOMMENDED

G ATE DRIVER AND SENSE AMPLIFIER

C

VM1

VM PGND X5R or X7R, 0.1-µF, VM-rated capacitor

C

VM2 VM PGND ≥ 10 µF, VM-rated capacitor

CVCP

VCP

VM

X5R or X7R, 16-V, 1-µF capacitor

C

SW

CPH CPL X5R or X7R, 47-nF, VM-rated capacitor

C

DVDD DVDD AGND X5R or X7R, 1-µF, 6.3-V capacitor

R

nFAULT

VCC

(1)

nFAULT Pullup re si st o r

R

SDO VCC

(1)

SDO Pullup re si st o r

R

IDRIVE

IDRIVE AGND or DVDD DRV832x hardware interface

R

VDS

AGND or DVDD

DRV832x hardware interface

R

MODE

AGND or DVDD

DRV832x hardware interface

R

GAIN GAIN AGND or DVDD DRV832x hardware interface

C

VREF VREF AGND or DGND X5R or X7R, 0.1-μF, VREF-rated capacitor

RASENSE

SPA

SNA and PGND

Sense shunt re si st o r

R

BSENSE

SPB SNB and PGND Sense shunt re si st o r

RCSENSE

SPC

SNC and PGND

Sense shunt re si st o r

BUCK REGULATOR

CVIN

VIN

BGND

X5R or X7R, 1 to 10 µF, VM-rated capacitor

C

BOOT

SW CB X5R or X7R, 0.1-µF, 16-V capacitor

D

SW SW BGND Schottky diode

LSW

SW

OUT(2)

Output inductor

C

OUT

(2)

BGND X5R or X7R, OUT rated capacitor

R

FB1

OUT(2)

FB

Re si st o r divider to se t buck output voltage

R

FB2 FB BGND

(1)

The VCC pin is not a pin on the DRV832x family of devices, but a VCC supply voltage pullup is required for the open-drain outputs,

nFAULT and SDO. These pins can a l so be pulled up to DVDD.

(2)

The OUT pin is not a pin on the DRV8320R and DRV8323R devices, but is the regulated output voltage of the buck regulator after the

output inductor.

8.3.1

Three Phase Smart Gate Drivers

The DRV832x family of devices integrates three, half-bridge gate drivers, each capable of driving high-side and

low-side N-channel power MOSFETs. A doubler charge pump provides the correct gate bias voltage to the high-

side MOSFET across a wide operating voltage range in addition to providing 100% support of the duty cycle. An

internal linear regulator provides the gate bias voltage for the low-side MOSFETs. The half-bridge gate drivers

can be used in combination to drive a three-phase motor or separately to dri ve other types of loads.

The DRV832x family of devices implements a Smart Gate Drive architecture which allows the user to

dynamically adjust the gate drive current without requiring external resistors to limit the gate current. Additionally,

this architecture provides a variety of protection features for the external MOSFETs incl u di ng automatic dead

time insertion, prevent of parasitic dV/dt gate turnon, and gate fault detection.

8.3.1.1

PWM Control Modes

The DRV832x family of devices provides four different PWM control modes to support various commutat ion and

control methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register

during operation of the power MOSFETs. Set all INHx and INLx pins to logic low before changing the MODE pin

or PWM_MODE register.

I TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.li.com INLA INHE INLB INLA INHE INLB Slop n a n u n u PWM 'PWM copyngmcc) 201772022, Texas \nstrumenls \noorpaated SubmtDocumentatmn Feedback 31 Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

31

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.3.1.1.1

6x PWM Mode (PWM_MODE = 00b or M ODE Pin Tied to A GND)

In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The

corresponding INHx and INLx signals control the output state as listed in Table 2.

Table 2. 6x PWM Mode Truth Table

INLx

INHx

GLx

GHx

SHx

0

L

Hi-Z

0

1

L

H

1

0

H

L

1

L

Hi-Z

8.3.1.1.2

3x PWM Mode (PWM_MODE = 01b or M ODE Pin = 47 kΩ to A GND)

In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx

pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins t o logi c high.

The corresponding INHx and INLx signals control the output state as listed in Table 3.

Table 3. 3x PWM Mode Truth Table

INLx

INHx

GLx

GHx

SHx

0

X

L

Hi-Z

1

0

H

L

1

L

H

8.3.1.1.3

1x PWM Mode (PWM_MODE = 10b or M ODE Pin = Hi-Z)

In 1x PWM mode, the DRV832x family of devices uses 6-step block commutation tables that are stored

internally. This feature allows for a three-phase BLDC motor to be controlled using one PWM sourced from a

simple controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of

the half-bridges.

The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic

inputs. The state inputs can be controlled by an external controller or connected directly to the digit al out put s of

the Hall effect sensor from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode

usually operates with synchronous rectification (low-side MOSFET recirculation); however, the mode can be

configured to use asynchronous rectification (MOSFET body diode freewheeling) on SPI devices. This

configuration is set using the 1PWM_COM bit in the SPI registers.

The INHC input controls the direction through the 6-step commutation table which is used to change the direction

of the motor when Hall effect sensors are directly controlling the state of the INLA, INHB, and INLB inputs. Tie

the INHC pin low if this feature is not required.

The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs

when the INLC pin is pulled low. This brake is independent of the state of the other input pins. Tie the INLC pin

high if this feature is not required.

Table 4. Synchronous 1x PWM Mode

LOGIC AND HALL IN PUTS G AT E DRIVE OU TPUTS

(1)

STATE

INHC = 0

INHC = 1

PHASE A

PHASE B

PHASE C

DESCRIPTION

INLA INHB INLB INLA INHB INLB GHA GLA GHB GLB GHC GLC

Stop

0

L

Stop

Align

1

PWM

!PWM

L

H

L

H

Align

1

0

1

L

PWM

!PWM

L

H

B → C

2

1

0

1

PWM !PWM

L

H

A → C

3

1

0

1

0

1

0

PWM !PWM

L

H

L

A → B

4

0

1

0

L

H

PWM !PWM C → B

5

0

1

0

L

H

L

PWM !PWM C → A

6

0

1

0

1

0

1

L

H

PWM !PWM

L

B → A

(1) !PWM is the inverse of the PWM signal.

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com INLA INHB INLB INLA Slop n a n u \NHA PwM mm $7 5mm PwM \NLA smrsn was 5mm an): Nmev mac mer \NLE HERAKE smrsz l smrsz w "BRAKE 32 Submt Docunentanon Feedbacﬁ Cnpy ngm© 201772022 Texas \rstrumenls \nmrpualed Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

32

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Table 5. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)

LOGIC AND HALL IN PUTS

G ATE DRIVE OU TPUTS

STATE INHC = 0 INHC = 1 PHASE A PHASE B PHASE C

DESCRIPTION

INLA INHB INLB INLA INHB INLB GHA GLA GHB GLB GHC GLC

Stop

0

L

Stop

Align

1

PWM

L

H

L

H

Align

1

0

1

L

PWM

L

H

B → C

2

1

0

1

PWM

L

H

A → C

3

1

0

1

0

1

0

PWM

L

H

L

A → B

4

0

1

0

L

H

PWM

L

C → B

5

0

1

0

L

H

L

PWM

L

C → A

6

0

1

0

1

0

1

L

H

PWM

L

B → A

Figure 18 and Figure 19 show the different possible configurations in 1x PWM mode.

Figure 18. 1x PWM—Simple Controller Figure 19. 1x PWM—Hall Effect S enso r

8.3.1.1.4

Independent PWM Mode (PWM_MODE = 11b or M ODE Pin Tied to DV DD)

In independent PWM mode, the corresponding input pin independently controls each high-side and low-side gat e

driver. This control mode lets the DRV832x family of devices drive separate high-side and low-side loads with

each half-bridge. These types of loads include unidirectional brushed DC motors, solenoids, and low-side and

high-side switches. In this mode, if the system is configured in a half-bridge configuration, turning on both the

high-side and low-side MOSFETs at the same time causes shoot-through.

Table 6. Independent PWM Mode Truth Table

INLx

INHx

GLx

GHx

0

L

0

1

L

H

1

0

H

L

1

H

INHA

PWM

INLA

STATE0

H

INHB

STATE1

H

INLB

BLDC Motor

STATE2

INHC

H

DIR

INLC

nBRAKE

MCU_GPIO

MCU_PWM

INHA

PWM

INLA

STATE0

INHB

STATE1

BLDC Motor

INLB

STATE2

INHC

DIR

INLC

nBRAKE

MCU_GPIO

MCU_PWM

I TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R wwaLcom Dusame VM VDRA‘N ch ,_ INHx :g‘ 1%} “‘3“ ,_ I st INu I” :53 Ga|e Dnva SLx/SPX Dusame VM VM VDRA‘N VDRA‘N vcp vcp 2d \NHx ﬁg 3 \NHx ”5 > ‘NLX VGLS ‘NLX VGLS GLx | H _ Ls L In} _ j I— Gale Drwa SLx/SPX Gale Drwa SLx/SPX copyngmcc) 201772022, Taxes \nslrumenls \noorpaated SubmtDacumentatmn Feedback 33 Fmducl Fomeerls DRV8320 DRV8320R DRV8323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

33

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Disable

V

DS

-

+

VM

VDRAIN

VCP

GHx

INHx

HS

Load

SHx

INLx

VGLS

GLx

LS

Load

Gate Driv er

SLx/SPx

Disable

V

DS

-

+

VDS +

VM

VDRAIN

VCP

GHx

INHx

HS

SHx

INLx

VGLS

GLx

LS

Load

Gate Driv er

SLx/SPx

V +

DS

VDS +

VM

VDRAIN

VCP

GHx

Load

INHx

HS

SHx

INLx

VGLS

GLx

LS

Gate Driv er

SLx/SPx

V +

DS

Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using the monitors when

both the high-side and low-side gate drivers of one half-bridge are split and being used is not possible. In this

case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in

Figure 20.

Figure 20. Independent PWM High-Side a nd Low-Si de Drivers

If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors is

still possible. Connect the SHx pin as shown in Figure 21 or Figure 22. The unused gate driver and the

corresponding input can stay disconnected.

Figure 21. One High-Side Driver Figure 22. One Low-Side Dri ver

8.3.1.2

Device Interface Modes

The DRV832x family of devices supports two different interface modes (SPI and hardware) to let the end

application design for either flexibility or simplicity. The two interface modes share the same four pins, allowing

the different versions to be pin-to-pin compatible. This compatibility lets application designers evaluat e wit h one

interface version and potentially switch to another with minimal modifications to their design.

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.n.com 5w H ardware Inleﬂaoa Inlenaoa 34 SubmtDocunemanan Feedbacﬁ capyngm© 201772022 Tex$ \rslruments \nmrpuated Fmducl Fomeerls DRV8320 DRV8320R DRV8323 DRV8323R

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

34

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

SCLK

SPI

Interface

SDI

VCC

R

PU

SDO

nSCS

DVDD

RGAIN

GAIN

DVDD

Hardware

Interf ace

DVDD

IDRIVE

DVDD

MOD E

DVDD

VDS

R

VDS

8.3.1.2.1

Ser ial Peripheral Interface (SPI)

The SPI devices support a serial communication bus that lets an external controller send and receive data with

the DRV832x. This support lets the external controller configure device settings and read detailed fault

information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are described

as follows:

•

The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagat ed on

the SDI and SDO pins.

•

The SDI pin is the data input.

•

The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup

resistor.

•

The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the

DRV832x.

For more information on the SPI, see the SPI Communication section.

8.3.1.2.2

Hardw are Interface

Hardware interface devices convert the four SPI pins into four resistor-configurable inputs which are GAIN,

IDRIVE, MODE, and VDS. This conversion lets the application designer configure the most common device

settings by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the

requirement for an SPI bus from the external controller. General fault information can still be obtained through

the nFAULT pin.

•

The GAIN pin configures the gain of the current sense amplifier.

•

The IDRIVE pin configures the gate dri ve current strength.

•

The MODE pin configures the PWM control mode.

•

The VDS pin configures the voltage threshold of the VDS overcurrent monitors.

For more information on the hardware interface, see the Pin Diagrams section.

Figure 23. SPI Figure 24. Hardware Interface

8.3.1.3

Gate Driver Voltage Supplies

The voltage supply for the high-side gate driver is created using a doubler charge pump that operates from the

VM voltage supply input. The charge pump lets the gate driver correctly bias the high-side MOSFET gate with

respect to the source across a wide input supply voltage range. The charge pump is regulated to keep a fixed

output voltage of VVM + 11 V and supports an average output current of 25 mA. When VVM is less than 12 V, the

charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5 V when unloaded. The charge

pump is continuously monitored for undervoltage events to prevent under-driven MOSFET conditions. The

charge pump requires a X5R or X7R, 1 -µF, 16-V ceramic capacitor between the VM and VCP pins to ac t as t he

storage capacitor. Additionally, a X5R or X7R, 47-nF, VM-rated ceramic capacitor is required bet ween t he CPH

and CPL pins to act as the flying capacitor.

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R wwaLcom VM VM VCP CPH VM CPL FF“ ”mg”; copyngmcc) 201772022, Taxes \nslmmenls \noorpaated SubmtDacumentanon Feedback 35 Fmducl Fomeerls DRV8320 DRV8320R DRV8323 DRV8523R

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

35

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Figure 25. Charge Pump Architecture

The voltage supply of the low-side gate driver is created using a linear regulator that operates from the VM

voltage supply input. The linear regulator lets the gate driver correctly bias the low-side MOSFET gate with

respect to ground. The linear regulator output is fixed at 11 V and supports an output current of 25 mA.

8.3.1.4

Smart Gate Drive Architecture

The DRV832x gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and low-

side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.

Additionally, the gate drivers use a Smart Gate Drive architecture to provide additional control of the external

power MOSFETs, additional steps to protect the MOSFETs, and optimal tradeoffs between efficiency and

robustness. This architecture is implemented through two components called IDRIVE and TDRIVE which are

described in the IDRIVE: MOSFET Slew-Rate Control section and TDRIVE: MOSFET Gate Drive Control

section. Figure 26 shows the high-level functional block diagram of the gate driver.

The IDRIVE gate dri ve current and TDRIVE gate dri ve time should be initially selected based on the parameters

of the external power MOSFET used in the system and the desired rise and fall times (see the Application and

Implementation section).

The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gat e from

overvoltage conditions in the case of external short-circuit events on the MOSFET.

VM

1 µF

VCP

CPH

VM

47 nF

CPL

Charge

Pump

Control

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com \NHx ch VM < comm="" j="" $="" mm="" ‘nlx="" my="" ghx="">7 4'3}? 5mm I7 H] * >— ; J 150m I... st LJ .7 7 VGLS Dwgue‘ J Core Leve‘ r GLx >7 smnevs J7 N ,_ J .4 150 kD ,_ r1 su/sw LJ : ﬂ PGND LJ 35 SubmtDocunemanan Feedbacﬁ capyngm© 201772022 Tex$ \rstruments mmrpumea Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

36

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Figure 26. Gate Driver Block Diagram

8.3.1.4.1

IDRIV E: M OSFET Sle w -Rate Control

The IDRIVE component implements adjustable gate drive current to control the MOSFET VDS slew rates. The

MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy, and duration of diode

recovery spikes, dV/dt gate turnon resulting in shoot-through, and switching voltage transients related to

parasitics in the external half-bridge. The IDRIVE component operates on the principal that the MOSFET VDS

slew rates are predominately determined by the rate of gate charge (or gate current) delivered during the

MOSFET QGD or Miller charging region. By letting the gate driver adjust the gate current, the gate driver can

effectively control the slew rate of the external power MOSFETs.

The IDRIVE component lets the DRV832x family of devices dynamically switch between gate dri ve currents

either through a register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI

devices provide 16 IDRIVE settings ranging from 10-mA to 1-A source and 20-mA to 2-A sink. Hardware interface

devices provide 7 IDRIVE settings within the same ranges. The setting of the gate drive current is delivered t o t he

gate during the turnon and turnoff of the external power MOSFET for the tDRIVE duration. After the MOSFET

turnon or turnoff, the gate driver switches to a smaller hold IHOLD current to improve the gate driver efficienc y . For

additional details on the IDRIVE settings, see the Register Maps section for the SPI devices and the Pin

Diagrams section for the hardware interface devices.

8.3.1.4.2

TDRIV E: M OSFET Gate Dr ive Control

The TDRIVE component is an integrated gate drive state machine that provides automatic dead t ime insert ion

through handshaking between the high-side and low-side gate drivers, parasitic dV/dt gate turnon prevention,

and MOSFET gate fault detection.

The first component of the TDRIVE state machine is automatic dead time insertion. Dead time is period of t im e

between the switching of the external high-side and low-side MOSFETs to make sure that they do not cross

conduct and cause shoot-through. The DRV832x family of devices uses VGS voltage monitors to measure the

MOSFET gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time value.

This feature lets the dead time of the gate driver adjust for variation in the system such as temperature drift and

variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is adjustable

through the registers on SPI devices.

INHx

VCP

VM

INLx

Control

Inputs

Level

Shifter s

GHx

150 kO

SHx

VGS +

VGLS

Digital

Core

Level

Shifter s

GLx

150 kO

SLx/SPx

V

GS

+

PGND

I TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.li.com | "I lDam/E I“ "I lDam/E F— | copyngmcc) 201772022, Texas \nstrumenls \nwrpaated SubmtDacumentatmn Feedback 37 Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

37

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

The second component of the TDRIVE state machine is parasitic dV/dt gate turnon prevention. To implement this

component, the TDRIVE state machine enables a strong pulldown current (ISTRONG) on the opposite MOSFET

gate whenever a MOSFET is switching. The strong pulldown occurs for the TDRIVE duration. This feature helps

remove parasitic charge that couples into the MOSFET gate when the voltage half-bridge switch node slews

rapidly.

The third component of the TDRIVE state machine implements a scheme for gate fault detection to detect pin-to-

pin solder defects, a MOSFET gate failure, or stuck-high or stuck-low voltage condition on a MOSFET gate. This

implementation occurs with a pair of VGS gate-to-source voltage monitors for each half-bridge gate driver. W hen

the gate driver receives a command to change the state of the half-bridge, it starts to monitor the gate voltage of

the external MOSFET. If the VGS voltage has not reached the correct threshold at t he end of the tDR IV E period,,

the gate driver reports a fault. To make sure that a false fault is not detected, a tDRIVE time should be selected

that is longer than the time required to charge or discharge the MOSFET gate. The tDRIVE time does not inc rease

the PWM time and will terminate if another PWM command is received while active. For additional details on t he

TDRIVE settings, see the Register Maps section for SPI devices. The hardware interface devices have a fixed

tDRIVE of 4 µs.

Figure 27 shows an example of the TDRIVE state machine in operation.

VINHx

VINLx

VGHx

IGHx

VGLx

IGLx

Figure 27. TDRIVE State Machine

8.3.1.4.3

Propagation De lay

The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output

change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay,

and the delay through the analog gate drivers.

The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate

drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input

command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to

the overall propagation delay of the device.

8.3.1.4.4

M OSFET VDS Monitors

The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on

the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for

longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the

device VDS fault mode.

IHOLD

tDRIVE

IDRIVE

ISTRONG

IDRIVE

ISTRONG

t

DEAD

IHOLD

t

DEAD

IHOLD

t

DRIVE

t

DRIVE

IDRIVE

ISTRONG

IDRIVE

t

DEAD

IHOLD

t

DEAD

IHOLD

DRV8320, DRV8320R VDRAIN vVDspcp Vus VDS' vVDspcp I TEXAS INSTRUMENTS www.n.com VDRAIN 38 SubmtDocunemanan Feedbacﬁ capyngm© 201772022 Tex$ \rslruments \nmrpuated Fmducl Fomeerls DRV8320 DRV8320R DRV8323 DRV8523R

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

38

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

VM

VDRAIN

V

DS

-

+

V

DS

+

-

VVDS_OCP

GHx

SHx

VDS

+

-

V +

DS

-

VVDS_OCP

GLx

SLx

PGND

The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins. In devices with three

current sense amplifiers (DRV8323 and DRV8323R), the low-s i de VDS monitors measure the voltage between

the SHx and SPx pins. If the current sense amplifier is unused, tie the SP pins to the common ground point of

the external half-bridges. On device options without the current sense amplifiers (DRV8320 and DRV8320R) t he

low-side VDS monitor measures between the SHx and SLx pins.

For the SPI devices, the reference point of the low-side VDS monitor can be changed between the SPx and S Nx

pins if desired with the LS_REF register setting.

The VVDS_OCP threshold is programmable from 0.06 V to 1.88 V. For additional information on the VDS monitor

levels, see the Register Maps section for SPI devices and in the Pin Diagrams section hardware interface device.

Figure 28. DRV8320 and DRV8320R VDS Monitors

Figure 29. DRV8323 and DRV8323R VDS Monitors

8.3.1.4.5

V DRAIN Se ns e Pin

The DRV832x family of devices provides a separate sense pin for the common point of the high-side MOSFET

drain. This pin is called VDRAIN. This pin lets the sense line for the overcurrent monitors (VDRAIN) and the

power supply (VM) stay separate and prevent noise on the VDRAIN sense line. This separation also lets

implementation of a small filter on the gate driver supply (VM) or insertion of a boost converter t o s upport lower

voltage operation if desired. Care must still be used when designing the filter or separate supply becaus e VM is

still the reference point for the VCP charge pump that supplies the high-side gate drive volt age (V GSH). The VM

supply must not drift too far from the VDRAIN supply to avoid violating the VGS voltage specification of the

external power MOSFETs.

8.3.2

DVDD Linear Voltage Regulator

A 3.3-V, 30-mA linear regulator is integrated into the DRV832x family of devices and is available for use by

external circuitry. This regulator can provide the supply voltage for a low-power MCU or other circuitry support ing

low current. The output of the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1-µF,

6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin.

The DVDD nominal, no-load output voltage is 3.3 V. When the DVDD load current exceeds 30 mA, the regulat or

functions like a constant-current source. The output voltage drops significantly with a current load greater than 30

mA.

VM

VDRAIN

V

DS

-

+

V

DS

+

VVDS_OCP

-

GHx

SHx

V

DS

-

+

V +

DS -

VVDS_OCP

GLx

SPx

0

RSENSE

1

SNx

PGND

LS_REF

(SPI Only )

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R wwaLcom DVDD 3 av‘ 30 mA P = (VVM VDVDD) X IDVDD P:(24V73.3 V)x20 mA:414mW DVDD copyngmcc) 201772022, Taxes \nslmmenls \nmrpaated SubmtDacumentanon Feedback 39 Fmducl Fomeerls DRV8320 DRV832UR DRV8323 DRV8323R

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

39

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

STATE RESISTANCE

VIH Tied to DVDD

VIL Tied to AGND

DVDD

100 kO

Logic Low

Logic High

INPUT

REF

Figure 30. DVDD Linear Regulator Block Diagram

Use Equation 1 to calculate the power dissipated in the device by the DVDD linear regulator.

P VVM VDVDD IDVDD

(1)

For example, at a VVM of 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in

Equation 2.

P 24 V 3.3 V 20 m A 414 mW

8.3.3

Pin Diagrams

(2)

Figure 31 shows the input structure for the logic level pins, INHx, INLx, CAL, ENABLE, nSCS, SCLK, and SDI.

The input can be driven with a voltage or external resistor.

Figure 31. Logic-Level Input Pin Structure

VM

+

DVDD 3.3 V, 30 mA

0.1 µF

AGND

TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com DVDD \ ”<6 e4ko="" ‘="" x="" c="" 4="" \="" c="" 4="" \=""><6 a="" dvdd="" dvdd="" ‘="" y="" a="" l="" :‘73k0="" ‘="" i="" x*="" r="" ‘="" 1="" °_,="" \="" lj\="" \="" 4="" a="" l="" 73ko="" .3=""><9 “4="" \="" 47/="" \="" 4="" 40="" submtdocll/veha‘enoit="" feedback="" cnpyrlghl©201772022="" tex$="" \rstrumentsmmrpovamd="" fruducl="" fomeerbs="" drv8320="" drva320r="" drv5323="" drvaszsr="">

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

40

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

STATE RESISTANCE

VI4 Tied to DVDD

VI3

Hi-Z (>500 kO to

AGND)

VI2

47 kO ±5%

to AGND

VI1 Tied to AGND

MOD E GAIN

Independent

40 V/V

1x PWM

20V/V

3x PWM

10 V/V

6x PWM

5 V/V

STATE RESISTANCE

VI7 Tied to DVDD

VI6

18 kO ± 5%

to DVDD

VI5

75 kO ± 5%

to DVDD

VI4

Hi-Z (>500 kO

to AGND)

VI3

75 kO ± 5%

to AGND

VI2

18 kO ±5%

to AGND

VI1 Tied to AGND

IDRIVE VDS

1/2 A

Disabled

570/1140

mA

1.88 V

260/520 mA

1.13 V

120/240 mA

0.60 V

60/120 mA

0.26 V

30/60 mA

0.13 V

10/20 mA

0.06 V

Figure 32 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices. The

input can be set with an external resistor.

Figure 32. Four Level Input Pin Structure

Figure 33 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices.

The input can be set with an external resistor.

Figure 33. Seven Level Input Pin Structure

+

DVDD

+

73 kO

+

73 kO

+

DVDD

+

50 kO

84 kO

+

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.u.com SOX pin on the DRV8 SNx pins multiplied by V, 10 WV, 20 V/V, an VVREF 7 7 v I_ 2 sex csn X RSENSE copyngmcc) 201772022, Taxes inslrumenls inmrpaated SubmiDacumentaimn Feedback 41 Pmduct Foideeris DRV8320 DRV832UR DRV8323 DRvaszaR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

41

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

STATE STATU S

No Fault Inactive

Fault Activ e

DVDD

RPU

Inactive

Activ e

OUTPUT

Figure 34 shows the structure of the open-drain output pins, nFAULT and SDO. The open-drain output requires

an external pullup resistor to function correctly.

Figure 34. Open-Drain Output Pin Structure

8.3.4

Low-Side Current S en se Amplifiers (DRV8323 and DRV8323R Only)

The DRV8323 and DRV8323R integrate three, high-performance low-side current sense amplifiers for current

measurements using low-side shunt resistors in the external half-bridges. Low-side current measurements are

commonly used to implement overcurrent protection, external torque control, or brushless DC commutat ion with

the external controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or one

amplifier can be used to sense the sum of the half-bridge legs. The current sense amplifiers include features

such as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference

pin (VREF). If any of the three current sense amplifiers are not being used, they can be tied off by s hort ing t he

SNx pin to the SPx pin and leaving the SOx pin unconnected. Remember to connect the SPx or S Nx pin t o t he

low-side FET source, so that the overcurrent VDS monitor is still functional

8.3.4.1

Bidirectional Current Sense Operation

The SOx pin on the DRV8323 and DRV8323R outputs an analog voltage equal to the voltage across the SPx

and SNx pins multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels

(5 V/V, 10 V/V, 20 V/V, and 40 V/V). Use Equation 3 to calculate the current through the shunt resistor.

VVREF - V

I = 2 SOx

GCSA x RSENSE (3)

I

SPx

SNx

RSENSE

Figure 35. Bidirectional Current S en se Configuration

R2

R3

R4

R5

SOx

R6

VCC

R1

VREF

0.1 µF

R1

+

R2

½

+

R3

R4

R5

DRV8320, DRV8320R I TEXAS INSTRUMENTS www.n.com 42 Submf Docunentanan Feedbacﬁ capyngnm 201772022 Tex$ \rslruments \nmrpuated Fmducl Fomeerls DRV8320 DRV8320R DRV8323 DRV8323R

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

42

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

VOFF,

V

DRIFT

VREF

VVREF / 2

VLINEAR

SO (V)

SP - SN (V)

Figure 36. Bidirectional Current S en se Output

I

SP

SO AV R

SN

SO

VREF

VVREF - 0.25 V

SP - SN

-0.3 V

-I × R

VSO( rang e-)

VSO(off)max

VVREF / 2 0 V

VSO(off)min

VSO( rang e+ )

I × R

0.25 V 0.3 V

0 V

Figure 37. Bidirectional Current S en se Re gi ons

TEXAS INSTRUMENTS DRV8320, DRV832DR 8323R www.u.com On the DRV8323 and DRV832 the current sense ampliﬁer 0 voltage across the SPx and urrent through the shunt res I: VVREF ’ Vsox GCSA X RSENSE Wu—o ; >—3 * ’ ngm #3 / ’ b~xm VVREF , 0 3V Copyngm© 201772022, Texas Inslrumenls \nmrpaated SubmtDacumentanon Feedback 43 Pmducl Fo‘deerls DRV8320 DRV83217R DRV6323 DRV8323R

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

43

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

VREF

VVREF - 0.3 V

VLINEAR

8.3.4.2

Unidirectional Current Sense Operation (SPI only)

On the DRV8323 and DRV8323R SPI devices, use the VREF_DIV bit to remove the VREF divider. In this case

the current sense amplifier operates unidirectionally and the SOx pin outputs an analog voltage equal to the

voltage across the SPx and SNx pins multiplied by the gain setting (GCSA). Use Equation 4 to calculate the

current through the shunt resistor.

I = VVREF - VSOx

GCSA x RSENSE

(4)

R2

R3

R4

R5

SOx R6 I

VCC

VREF

+

0.1 µF

R1 SPx

R1

+

SNx

R2

R3

R4

RSENSE

R5

Figure 38. Unidirectional Current-S ense Configuration

SO (V)

SP - SN (V)

Figure 39. Unidirectional Current-Sen se Output

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

44

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

I

SP

SO AV R

SN

SO

VREF

VVREF - 0.25 V

VSO(off)max

VVREF - 0.3 V

VSO(off)min

VOFF,

VDRIFT

SP - SN

0 V

VSO( rang e)

I × R

0.3 V

0.25 V

0 V

Figure 40. Unidirectional Current-S ense Re gi ons

8.3.4.3

Auto Offset Calibration

To minimize DC offset, the DRV8323 and DRV8323R devices can perform an automatic offset calibration

through the SPI registers (CSA_CAL_X) or CAL pin. When the calibration is enabled, the inputs to t he amplifier

are shorted, the load is disconnected, and the gain (GCSA) of the amplifier is changed to the 40 V/ V s et ting. The

amplifier then goes through an automatic trim routine to minimize the input offset. The automatic trim routine

requires 100 µs to complete after the calibration is enabled. After this time, the inputs of the amplifier s t ay

shorted, the load stays disconnected, and the gain stays at 40 V/V if further offset calibration is desired to be

done by the external controller. To complete the offset calibration, the CSA_CAL_X registers or CAL pin should

be taken back low. The gain is returned to the original gain setting after the device completes calibration. For the

best results, perform offset calibration when the external MOSFETS are not switching to decrease the pot ent ial

noise impact to the amplifier. When the current sense amplifiers go into a calibration mode, the VREF pin is s et

to bidirectional mode if the device is configured in unidirectional mode. The setting of the VRE F pin affec t s t he

channels all three current sense amplifier, even if the CSA_CAL_X register is not set for the all channels.

8.3.4.4

M OSFET VDS S en se M ode (SPI Only)

The current sense amplifiers on the DRV8323 and DRV8323R SPI devices can be configured to amplify the

voltage across the external low-side MOSFET VDS. This configuration lets the external controller measure the

voltage drop across the MOSFET RDS(on) without the shunt resistor and then calculate the half-bridge current

level.

To enable this mode set the CSA_FET bit to 1. The positive input of the amplifier is then internally c onnected t o

the SHx pin with an internal clamp to prevent high voltage on the SHx pin from damaging the sense amplifier

inputs. During this mode of operation, the SPx pins should stay disconnected. When the CSA_FET bit is set to 1,

the negative reference for the low-side VDS monitor is automatically set to the SNx pin, regardless of the s t at e of

the state of the LS_REF bit. This setting is implemented to prevent disabling of the low-side VDS monitor.

If the system operates in MOSFET VDS current sense mode, route the SHx and SNx pins with Kelvin connections

across the drain and source of the external low-side MOSFETs .

I TEXAS INSTRUMENTS www.li.com v05 Mommy cm TIT st (SF-I mm ~‘ _| LJ TIT mm I L ~<[: i="" m="" j—="" t="" l'="" 50x="" 50x="" hignsme="" vdrnn="" v05="" momuw="" (spi="" mm="" i="" l="" i="" i="" i.="" was="" mmiioi="" drv8320,="" drv8320r="" 8323r="" tit="" lhj="" ie="" tit="" lhj="" st="" r1="" copy="" ngm©="" 2017720219”:="" instruments="" anrpaated="" fruducl="" fonerlins="" drv8320="" drva320r="" drv5323="" drvaszsr="" sumedacumentaimn="" feedback="" 45="">

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

45

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

VM VM

Figure 41. Re si sto r S e n se Configuration Figure 42. VDS Current S en se Mode

When operating in MOSFET VDS current sense mode, the amplifier is enabled at the end of the tDRIVE time. At

this time, the amplifier input is connected to the SHx pin, and the SOx output is valid. When the low-side

MOSFET receives a signal to turn off, the amplifier inputs, SPx and SNx, are shorted together internally.

8.3.5

Step-Dow n Buck Re gul ator

The DRV8320R and DRV8323R have an integrated buck regulator (LMR16006) to supply power for an ex t ernal

controller or system voltage rail. The LMR16006 device is a 60-V, 600-mA, buck (step-down) regulator.

The buck regulator has a very-low quiescent current during light loads to prolong battery life. The LMR16006

device improves performance during line and load transients by implementing a constant-frequency current-mode

control scheme which requires less output capacitance and simplifies frequency compensation design. The

LMR16006 is the LMR16006X device version that uses a 0.7-MHz switching frequency.

The LMR16006 device decreases the external component count by integrating the bootstrap recharge diode. The

bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the CB to SW pin. The boot s trap

capacitor voltage is monitored by a UVLO circuit and turns off the high-side MOSFET when the boot voltage falls

lower than a preset threshold.

The LMR16006 device can operate at high duty cycles because of the boot UVLO and then refreshes t he wimp

MOSFET. The output voltage can be stepped down to as low as the 0.8-V reference. The internal soft-s t art

feature minimizes inrush currents.

For additional details, a block diagram showing the wimp MOSFET, and design information refer to the

LMR16006 SIMPLE SWITCHER® 60 V 0.6 A Buck Regulators With High Efficiency Eco-mode data sheet.

High-Side

VDS Monitor

VDRAIN

V

DS

+

GHx

(SPI only)

SHx

Low-Side

VDS Monitor

V

DS

+

GLx

0

1

10 kO

SPx

SOx

A

V

10 kO

SNx

GND

LS_REF = X

CSA_FET = 1

High-Side

VDS Monitor

VDRAIN

V

DS

+

GHx

(SPI only)

SHx

Low-Side

VDS Monitor

V

DS

+

GLx

0

1

10 kO

SPx

SOx

A

V

10 kO

RSENSE

SNx

GND

LS_REF = 0

CSA_FET = 0

DRV8320, DRVBSZDR I TEXAS INSTRUMENTS www.n.:om The output vo‘tage is set using the gure 53. The voltage of the fee age according to Equaﬂnﬁl 5- v0 :0765 v x 1+ E R2 picaHy the stagingmalue of R2 is fro R1=R2x V70 71 0.765V 46 SubmtDocunentauon Feedbact Capy ngm© 201772022. Tex§ \rslrumenls mmrpaatea Pmducl Foldeerls DRVSSZU DRV8320R DRV6323 DRV8323R

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

46

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

)

8.3.5.1

Fixed Frequency PWM Control

The LMR16006 device has a fixed switching frequency and implements peak current-mode control. The output

voltage is compared through external resistors on the FB pin to an internal voltage reference by an error amplifi er

which drives the internal COMP node. An internal oscillator initiates the turnon of the high-side power switch. The

error amplifier output is compared to the high-side power switch current. When the power switch current reac hes

the level set by the internal COMP voltage, the power switch turns off. The internal COMP node volt age

increases and decreases as the output current increases and decreases. The device implements a current limit

by clamping the COMP node voltage to a maximum level.

8.3.5.2

Bootstrap Voltage (CB)

The LMR16006 device has an integrated bootstrap regulator, and requires a small ceramic capacitor bet ween

the CB and SW pins to provide the gate drive voltage for the high-side MOSFET. The CB capacitor is refres hed

when the high-side MOSFET is off and the low-side diode conducts. To improve dropout, the LMR16006 device

is designed to operate at 100% duty cycle as long as the CB to SW pin voltage is great er t han 3 V . When t he

voltage from the CB to SW pin drops to less than 3 V, the high-side MOSFET turns off using a UVLO circuit

which lets the low-side diode conduct and refresh the charge on the CB capacitor. Because t he s upply c urrent

sourced from the CB capacitor is low, the high-side MOSFET can stay on for more switching cycles than are

required to refresh the capacitor. Therefore, the effective duty cycle of the switching regulator is hi gh. A ttention

must be given in maximum duty-cycle applications with a light load. To make sure the SW pin c an be pulled t o

ground to refresh the CB capacitor, an internal circuit charges the CB capacitor when the load is light or the

device is working in dropout condition.

8.3.5.3

Output Voltage Setting

The output voltage is set using the feedback pin (FB) and a resistor divider connected to the output as s hown in

Figure 53. The voltage of the feedback pin is 0.765 V, so the ratio of the feedback resistors sets the output

voltage according to Equation 5.

V = 0.765 V x (1+ r R1l 1

O

I

L

R2

I

J

I

)

Typically the starting value of R2 is from 1 kΩ to 100 kΩ. Use Equation 6 to calculate the value of R1.

(5)

R1 = R2 x f

f VO

l

'\

1

10.765 V I 1I

(6)

8.3.5.4

Enable nSHDN and VIN Undervoltage Lockout

The nSHDN pin of the LMR16006 device is an input that is tolerant of high voltages with an internal pullup circuit.

The device can be enabled even if the nSHDN pin is floating. The regulator can also be turned on using 1.23-V

or higher logic signals. If the use of a higher voltage is desired because of system or other constraints, a 100-kΩ

or larger value resistor is recommended between the applied voltage and the nSHDN pin to help protect the

device. When the nSHDN pin is pulled down to 0 V, the device turns off and goes to the lowest shutdown current

mode. In shutdown mode the supply current decreases to approximately 1 µA. If the shutdown function is

unused, the nSHDN pin can be tied to the VIN pin with a 100-kΩ resistor. The maximum voltage to the nSHDN

pin should not exceed 60 V. The LMR16006 device has an internal UVLO circuit to shut down t he out put if t he

input voltage falls lower than an UVLO threshold level that is internally fixed. Shutting down the output in this way

makes sure the regulator is not latched into an unknown state during low input voltage conditions. The regulat or

powers up when the input voltage exceeds the voltage level. If the UVLO voltage must be higher, use the

nSHDN pin to adjust the system UVLO by using external resistors.

8.3.5.5

Current Limit

The LMR16006 device implements current-mode control which uses the internal COMP voltage to turn off the

high-side MOSFET on a cycle-by-cycle basis. Each cycle, the switch current and internal COMP voltage are

compared. When the peak switch current intersects the COMP voltage, the high-side switch turns off. During

overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP node

high, increasing the switch current. The error amplifier output is clamped internally causing it to function as a

switch current limit.

I TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.li.com Chzvge pump sticpuv = Ob nFAU LT OCPiMODE=1Ub "FAULT Naachon Lalched 05qu = 1n No achon OTWjEP = m, No achon Aulomahc copyngmcc) 201772022, Texas \nstrumenls moorpaated SubmtDocumentatmn Feedback 47 Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

47

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.3.5.6

Overvoltage Transient Protection

The LMR16006 device incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage

overshoot when recovering from output fault conditions or strong unloaded transients on power s upply desi gns

with low-value output capacitance. For example, when the power supply output is overloaded, the error amplifier

compares the actual output voltage to the internal reference voltage. If the voltage of the FB pin is lower than t he

internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the error

amplifier output to a high voltage, therefore requesting the maximum output current. When the condit ion clears,

the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some

applications, the output voltage of the power supply can respond faster than the error amplifier output can

respond which can result in output overshoot. The OVTP feature minimizes the output overshoot when us ing a

low-value output capacitor by implementing a circuit to compare the FB pin voltage to the OVTP threshold which

is 108% of the internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the high-side

MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot . When the

FB voltage drops lower than the OVTP threshold, the high-side MOSFET can turn on at the next clock cycle.

8.3.5.7

Thermal Shutdown

The device implements an internal thermal shutdown to help protect the device if the junction temperature

exceeds 170°C (typical). The thermal shutdown forces the device to stop switching when the junction

temperature exceeds the thermal trip threshold. When the junction temperature decreases t o les s t han 160°C

(typical), the device reinitiates the power-up sequence.

8.3.6

Gate Driver Protective Circuits

The DRV832x family of devices is protected against VM undervoltage, charge pump undervoltage, MOSFET V DS

overcurrent, gate driver shorts, and overtemperature events.

Table 7. Fault Action and Response (SPI De vi ces)

FAULT CONDITION CONFIGURATION REPORT GATE DRIVER LOGIC RECOVERY

VM

under voltag e

(UVLO)

VVM < VU VL O

—

nFAULT

Hi-Z

Disabled Automatic:

VVM > VU VL O

Charg e pump

under voltag e

(CPUV)

VVC P < VCPUV

DIS_CPUV = 0b nFAULT Hi-Z Ac t i ve Automatic:

VVC P > VCPUV

DIS_CPUV = 1b None Ac t i ve A c ti ve

VDS

overcurr ent

(VDS_OCP)

VDS > VVD S_O C P

OCP_MODE = 00b

nFAULT

Hi-Z

Ac t i ve

Latched:

CLR_FLT, ENABLE Pulse

OCP_MODE = 01b

nFAULT

Hi-Z

Ac t i ve R etr y:

tRETRY

OCP_MODE = 10b nFAULT A c ti ve Ac t i ve No action

OCP_MODE = 11b

None

Ac t i ve

No action

VSEN SE

overcurrent

(SEN_OCP)

VSP > VSEN _O C P

OCP_MODE = 00b

nFAULT

Hi-Z

Ac t i ve

Latched:

CLR_FLT, ENABLE Pulse

OCP_MODE = 01b nFAULT Hi-Z Ac t i ve

R et r y:

tRETRY

OCP_MODE = 10b

nFAULT

Ac t i ve

No action

OCP_MODE = 11b or

DIS_SEN = 1b None A c ti ve A c ti ve No action

Gate driver fault

(GDF)

Gate vol tag e stuck > tDRIVE

DIS_GDF = 0b

nFAULT

Hi-Z

Ac t i ve Latched:

CLR_FLT, ENABLE Pulse

DIS_GDF = 1b None A c ti ve A c t i ve No action

Ther mal

war ning

(OTW)

TJ > TOTW

OTW_REP = 0b

None

Ac t i ve

No action

OTW_REP = 1b

nFAULT

Ac t i ve

Automatic:

TJ < TOTW – TH YS

Ther mal

shutdown

(OTSD)

TJ > TOTSD

—

nFAULT

Hi-Z

Ac t i ve Automatic:

TJ < TOTSD – TH YS

TEXAS DRV8320, DRV8320R INSTRUMENTS www.ﬂ.com 48 SubmeocunentaUan Feedbacﬁ Capyrlghté) 201772022 Tex§ \rslruments \nmrporated Fmducl Fo‘deerls DRV8320 DRV83217R DRV8323 DRVBSZSR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

48

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.3.6.1

VM Supply Undervoltage Lockout (UVLO)

If at any time the input supply voltage on the VM pin falls lower than the VUVLO threshold, all of the external

MOSFETs are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The FAULT and

VM_UVLO bits are also latched high in the registers on SPI devices. Normal operation starts again (gate driver

operation and the nFAULT pin is released) when the VM undervoltage condition clears. The VM_UVLO bit s t ays

set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST).

8.3.6.2

VCP Charge Pump Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin (charge pump) falls lower than the VCPUV threshold voltage of the

charge pump, all of the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT and

CPUV bits are also latched high in the registers on SPI devices. Normal operation starts again (gate driver

operation and the nFAULT pin is released) when the VCP undervoltage condition clears. The CPUV bit stays s et

until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). Setting the DIS_CPUV bit high on

the SPI devices disables this protection feature. On hardware interface devices, the CPUV protect ion is al ways

enabled.

8.3.6.3

M OSFET VDS Overcurrent Protection (VDS_OCP)

A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET RDS(on).

If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG deglitch

time, a VDS_OCP event is recognized and action is done according to the OCP_MODE bit. On hardware

interface devices, the VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at 4 µs, and the

OCP_MODE bit is configured for 4-ms automatic retry but can be disabled by tying the VDS pin to DVDD. On

SPI devices, the VVDS_OCP threshold is set through the VDS_LVL SPI register, the tOCP_DEG is set through the

OCP_DEG SPI register, and the OCP_MODE bit can operate in four different modes: VDS latched shutdown, V DS

automatic retry, VDS report only, and VDS disabled.

8.3.6.3.1

VDS Latched Shutdown ( OCP_M ODE = 00b)

After a VDS_OCP event in this mode, all external MOSFETs are disabled and the nFAULT pin is driven low.

When the external MOSFETs are disabled in this way, the driver automatically uses a lower setting for t he gat e

dri ve current instead of the programmed IDRIVE setting. This setting lets any large current that may be present

to be switched off slowly to minimize any inductive kickback caused by parasitic capacitance in the s yst em. The

FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal

operation starts again (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition

clears and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).

8.3.6.3.2

VDS Automatic Re t r y ( OCP_M ODE = 01b)

After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.

When the external MOSFETs are disabled in this way, the driver automatically uses a lower setting for t he gate

dri ve current instead of the programmed IDRIVE setting. This setting lets any large current that may be present

to be switched off slowly to minimize any inductive kickback caused by parasitic capacitance in the s yst em. The

FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal

operation starts again automatically (gate driver operation and the nFAULT pin is released) after the t RETRY time

elapses. The FAULT, VDS_OCP, and MOSFET OCP bits s t ay latched until the tRETRY period expires.

8.3.6.3.3

VDS Report Only ( OCP_M ODE = 10b)

No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving

the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in t he S PI

registers. The gate drivers continue to operate as usual. The external controller manages the overcurrent

condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP c ondition

clears and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).

8.3.6.3.4

VDS Disabled (OCP_M ODE = 11b)

No action occurs after a VDS_OCP event in this mode.

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R wwaLcom copyngmcc) 201772022, Texas Inslrumenls \nmrpaaled Submmacumentanon Feedback 49 Fmducl Fo‘deerls DRV8320 DRV83217R DRV8323 DRVBSZSR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

49

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.3.6.4

VSENSE Overcurrent Protection (SEN_OCP)

Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current sense res ist or

with the SP pin. If at any time the voltage on the SP input of the CSA exceeds the VSEN_OCP threshold for longer

than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done according to the

OCP_MODE bit. On hardware interface devices, the VSENSE threshold is fixed at 1 V, tOCP_DEG is fixed at 4 µs,

and the OCP_MODE for VSENSE is fixed for 4-ms automatic retry. On SPI devices, the VSENSE threshold is set

through the SEN_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI register, and the OCP_M ODE

bit can operate in four different modes: VSENSE latched shutdown, VSENSE automatic retry, VSENSE report only, and

VSENSE disabled.

8.3.6.4.1

VSENSE Latched Shutdown (OCP_MODE = 00b)

After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.

The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation starts again (gat e driver

operation and the nFAULT pin is released) when the SEN_OCP condition clears and a clear fault s c ommand is

issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).

8.3.6.4.2

VSENSE Automatic Re t r y (OCP_M ODE = 01b)

After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.

The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal

operation starts again automatically (gate driver operation and the nFAULT pin is released) after the t RETRY time

elapses. The FAULT , SEN_OCP, and sense OCP bits stay latched until the tRETRY period expires.

8.3.6.4.3

VSENSE Report Only (OCP_M ODE = 10b)

No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving

the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers

continue to operate. The external controller manages the overcurrent condition by acting appropriately. The

reporting clears (nFAULT released) when the SEN_OCP condition clears and a clear faults command is is sued

either through the CLR_FLT bit or an ENABLE reset pulse (tRST).

8.3.6.4.4

VSENSE Disabled ( OCP_M ODE = 11b or DIS_SEN = 1b)

No action occurs after a SEN_OCP event in this mode. The SEN_OCP bit can be disabled independent ly of t he

VDS_OCP bit by using the DIS_SEN SPI register.

8.3.6.5

Gate Driver Fault (GDF)

The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or

decrease after the tDRIVE time, a gate driver fault is detected. This fault may be encountered if t he GHx or GLx

pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault may be encountered if the

selected IDRIVE setting is not sufficient to turn on the external MOSFET within the tD RI VE period. After a gate drive

fault is detected, all external MOSFETs are disabled and the nFAULT pin driven low. In addition, the FAULT,

GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation starts again (gate

driver operation and the nFAULT pin is released) when the gate driver fault condition clears and a clear faults

command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). On SPI devices, setting the

DIS_GDF bit high disables this protection feature.

Gate driver faults can indicate that the selected IDRIVE or tDRIVE settings are too low to slew the external MOSFET

in the desired time. Increasing either the IDRIVE or tDRIVE setting can resolve gate driver faults in these cases.

Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported bec aus e of

the MOSFET gate not turning on.

8.3.6.6

Thermal W arni ng (OTW)

If the die temperature exceeds the trip point of the thermal warning (TOTW), the OTW bit is set in the registers of

SPI devices. The device performs no additional action and continues to function. When the die temperature falls

lower than the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also

be configured to report on the nFAULT pin by setting the OTW _RE P bit to 1 through the SPI registers.

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

50

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.3.6.7

Thermal Shutdown (OTSD)

If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), all the external MOSFETs are

disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and TS D bit s

are latched high. Normal operation starts again (gate driver operation and the nFAULT pin is released) when t he

overtemperature condition clears. The TSD bit stays latched high indicating that a thermal event occurred until a

clear fault command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). This protection

feature cannot be disabled.

8.4

Device Functional Modes

8.4.1

Gate Driver Functional Modes

8.4.1.1

Sleep M ode

The ENABLE pin manages the state of the DRV832x family of devices. When the ENABLE pin is low, the devic e

goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, sense amplifiers (if pres ent) are

disabled, all external MOSFETs are disabled, the charge pump is disabled, the DVDD regulator is disabled, and

the SPI bus is disabled. The LMR16006X buck regulator (if present) is not controlled by the ENABLE pin and can

be operated independently of the gate driver. The tSLEEP time must elapse after a falling edge on the ENABLE pin

before the device goes into sleep mode.

NOTE

The INHx and INLx pins should be low before tRST (max 40 μs) after ENABLE goes low to

prevent the GHx and GLx outputs from entering into Hi-Z state while any of the gat es are

high.

Figure 43 shows the behavior of the device after ENABLE goes low when the INHx and INLx pins are low prior t o

the time when the driver outputs ignore the inputs 50 μs after ENABLE goes low. The GHx and GLx pins will

remain low as the device begins the process to enter sleep mode. Figure 44 shows the behavior of t he devic e if

the input PWMs are not pulled low prior to the driver outputs ignoring the inputs. The GHx and GLx pins will follow

the inputs for 50 μs after ENABLE goes low, then will become Hi-Z until nFAULT goes low up to 400 μs after

ENABLE is low. To avoid this behavior, the INHx and INLx pins should be low before tRST (max 40 μs) after

ENABLE goes low as shown in Figure 43 to avoid the GHx and GLx outputs going into Hi-Z state while any of the

gate outputs are high.

Time

INHx

INLx

ENABLE

VGSH

VGSL

50 μs

Up to 400 μs

Ignore PWM inputs

Gate driver outputs in Hi-Z state

Follow PWM

inputs

nFAULT

Time

INHx

INLx

ENABLE

VGSH

VGSL

50 μs

Up to 400 μs

Ignore PWM inputs

Gate driver

shut of f

Gate driver outputs in Hi-Z state

Follow PWM

inputs

nFAULT

Figure 43. ENABLE Low Timing Diagram: Figure 44. ENABLE Low Timing Diagram:

Inputs Low Before PWM Inputs Ignored Inputs Continue to Toggle 50 μs After

ENABLE Goes Low

The device comes out of sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time must elapse

before the device is ready for inputs.

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R wwaLcom copyngmcc) 201772022, Texas \nslrumenls \nmrpaaled Sunmmacumentanon Feedback 51 Fmducl Fomeerls DRV8320 DRV8320R DRV8323 DRV8323R

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

51

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are

pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to t he PGND pin by an

internal resistor.

NOTE

During power up and power down of the device through the ENABLE pin, the nFAULT pi n

is held low as the internal regulators enable or disable. After the regulators have enabled

or disabled, the nFAULT pin is automatically released. The duration that the nFAULT pin

is low does not exceed the tSLEEP or tWAKE time.

8.4.1.2

Operating M ode

When the ENABLE pin is high and the VVM voltage is greater than the VUVLO voltage, the device goes to

operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the charge pump,

low-side gate regulator, DVDD regulator, and SPI bus are ac t i ve

8.4.1.3

Fault Reset (CLR_FLT or ENABLE Reset Pu l se)

In the case of device latched faults, the DRV832x family of devices goes to a partial shutdown state to help

protect the external power MOSFETs and system.

When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT S PI

bit on SPI devices or issuing a reset pulse to the ENABLE pin on either interface variant. The ENABLE res et

pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the sequence

should fall with the tRST time window or else the device will start the complete shutdown sequence. The reset

pulse has no effect on any of the regulators, device settings, or other functional blocks

TEXAS DRV8320, DRV8320R INSTRUMENTS www.ﬂ.com 52 SubmeocunentaUan Feedbacﬁ Capyrlghté) 201772022 Tex§ \rslruments \nmrporated Fmducl Fo‘deerls DRV8320 DRV83217R DRV8323 DRVBSZSR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

52

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Device Functional Modes (continued)

8.4.2

Buck Regulator Functional Modes

8.4.2.1

Continuous Conduction Mode (CCM)

conduction mode (when the inductor current never reaches zero at CCM), the buck regulator operates in two

cycles. The power switch is connected between the VIN and SW pins. During the first cycle of operation, the

transistor is closed and the diode is reverse biased. Energy is collected in the inductor and t he load c urrent i s

supplied by the COUT capacitor and the rising current through the inductor. During the second cycle of operation,

the transistor is open and the diode is forward biased because the inductor current cannot instantaneously

change direction. The energy stored in the inductor is transferred to the load and output capaci tor. The rat io of

these two cycles determines the output voltage. Equation 7 and Equation 8 define the approximate output

voltage.

D = VO

VVIN

where

•

D is the duty cycle of the sw itch (7)

D'

=

(

1

-

D

)

The value of D and D' is required for design calculations.

8.4.2.2

Eco-mode™ Control Scheme

(8)

The LMR16006 device operates with the Eco-mode control scheme at light-load currents to improve efficiency by

reducing switching and gate drive losses. The LMR16006 device is designed so that if the output voltage is

within regulation and the peak switch current at the end of any switching cycle is less than the sleep-current

threshold, IINDUCTOR ≤ 80 mA, the device goes to Eco-mode. For Eco-mode operation, the LMR16006 device

senses peak current, not average or load current, so the load current when the device goes to Eco-mode is

dependent on the input voltage, the output voltage, and the value of the output inductor. When the load current i s

low and the output voltage is within regulation, the device goes to Eco-mode and draws only 28-µA input

quiescent current.

8.5

Programming

This section applies only to the DRV832x SPI devices.

8.5.1

SPI Communication

8.5.1.1

SPI

On DRV832x SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out

diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input dat a

(SDI) word consists of a 16-bit word, with a 5-bit command and 11 bits of data. The SPI output data (SDO) word

consists of 11-bit register data. The first 5 bits are don’t care bits.

A valid frame must meet the following conditions:

•

The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.

•

The nSCS pin should be pulled high for at least 400 ns between words.

•

When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is

placed in the Hi-Z state.

•

Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK

pin.

•

The most significant bit (MSB) is shifted in and out first.

•

A full 16 SCLK cycles must occur for transaction to be valid.

•

If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word

is ignored.

•

For a write command, the existing data in the register being written to is shifted out on the SDO pin following

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.ll.mm WD A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I I I I I I I I I I | | I x MS“ I X I I X X I I I I I I I I I I I I I I I 2 M55 I X I ‘ X z I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Cnpy rIghl© 20177203, Texa InsImmenls Inmrpcraled Submt Documentation Feedback 53 Product FolderLInIx DRV8320 DRI/a320R DRV5323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

53

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Programming (continued)

the 5-bit command data.

The SPI registers are reset to the default settings on power up, when the device is enters sleep mode, and when

a UVLO fault occurs.

8.5.1.1.1

SPI Fo r m at

The SDI input data word is 16 bits long and consists of the following format:

•

1 read or write bit, W (bit B15)

•

4 address bits, A (bits B14 through B11)

•

11 data bits, D (bits B11 through B0)

The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The data word is the content of

the register being accessed.

For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being

written to.

For a read command (W0 = 1), the response word is the data currently in the register being read.

Table 8. SDI Input Data Word Format

R/W ADDRESS DATA

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

W0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 9. SDO Output Data W ord Format

DON'T CARE BI TS

DATA

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

X X X X X D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

nSCS

SCLK

SDI

SDO

Capture

Point

Propagate

Point

Figure 45. SPI Slave Timing Diagram

X

MSB

LSB

X

Z

MSB

LSB

Z

TEXAS INSTRUMENTS DRV8320, DRV8320R DRV8323, DRV8323R www.li.cnm SLVSDJSD rFEBRUARYZOWrREV‘SEDMARCH 2022 5 J DRvsms and DRVHSZHRS

DRV8320, DRV8320R

DRV8323,

DRV8323R

www.ti.com SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

8.6

Register Maps

This section applies only to the DRV832x SPI devices.

NOTE

Do not modify reserved registers or addresses not listed in the register map (Table 10). Writing to these registers may have

unintended effects. For all reserved bits, the default value is 0. To help prevent erroneous SPI writes from the master controller,

set the LOCK bits to lock the SPI registers.

Table 10. DRV832xS a nd DRV832xRS Register Map

Name 10

9

8

7

6

5

4

3

2

1

0

Type Address

DRV8320S and DR V8320RS

Fault Status 1

FAULT

VDS_OCP

GDF

UVLO

OTSD

VDS_HA

VDS_LA

VDS_HB

VDS_LB

VDS_HC

VDS_LC

R

0h

VGS Status 2

SA_OC

SB_OC

SC_OC

OTW

CPUV

VGS_HA

VGS_LA

VGS_HB

VGS_LB

VGS_HC

VGS_LC

R

1h

Driver Control Reserved DIS_CPUV DIS_GDF OTW_REP PWM_MODE 1PWM_COM 1PWM_DIR COAST BRAKE CLR_FLT RW 2h

Gate Drive HS LOCK IDRIVEP_HS IDRIVEN_HS RW 3h

Gate Drive LS CBC TDRIVE IDRIVEP_LS IDRIVEN_LS RW 4h

OCP Control

TRETRY

DEAD_TIME

OCP_MODE

OCP_DEG

VDS_LVL

RW

5h

Reserved

RW

6h

Reserved Reserved RW 7h

DRV8323S and DR V8323RS

Fault Status 1

FAULT

VDS_OCP

GDF

UVLO

OTSD

VDS_HA

VDS_LA

VDS_HB

VDS_LB

VDS_HC

VDS_LC

R

0h

VGS Status 2

SA_OC

SB_OC

SC_OC

OTW

CPUV

VGS_HA

VGS_LA

VGS_HB

VGS_LB

VGS_HC

VGS_LC

R

1h

Driver Control

Reserved

DIS_CPUV

DIS_GDF

OTW_REP

PWM_MODE

1PWM_COM

1PWM_DIR

COAST

BRAKE

CLR_FLT

RW

2h

Gate Drive HS LOCK IDRIVEP_HS IDRIVEN_HS RW 3h

Gate Drive LS CBC TDRIVE IDRIVEP_LS IDRIVEN_LS RW 4h

OCP Control

TRETRY

DEAD_TIME

OCP_MODE

OCP_DEG

VDS_LVL

RW

5h

CSA Contr ol

CSA_FET

VREF_DIV

LS_REF

CSA_GAIN

DIS_SEN

CSA_CAL_A

CSA_CAL_B

CSA_CAL_C

SEN_LVL

RW

6h

Reserved

RW

7h

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Submit Documentation Feedback 53

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

54

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.6.1

Status Registers

The status registers are used to reporting warning and fault conditions. The status registers are read-only

registers

Complex bit access types are encoded to fit into small table cells. Table 11 shows the codes that are used for

access types in this section.

Table 11. Status Registers Access Type Codes

Access Typ e

Code

Description

Read Type

R

Read

Reset or Default Value

-n

Value after reset or the default va l ue

8.6.1.1

Fault Status Register 1 (address = 0x00)

The fault status register 1 is shown in Figure 46 and described in Table 12.

Register access t y pe: Read only

Figure 46. Fault Status Register 1

10

9

8

7

6

5

4

3

2

1

0

FAULT

VDS_OCP

GDF

UVLO

OTSD

VDS_HA

VDS_LA

VDS_HB

VDS_LB

VDS_HC

VDS_LC

R-0b

Table 12. Faul t Status Register 1 Fie ld Descriptions

Bit

Field

Typ e

Default

Description

10 FAULT

R

0b Logic OR of FAULT status registers. Mirrors nFAULT pin.

9

VDS_OCP

R

0b Indicates VDS monitor overcurrent fault condition

8

GDF

R

0b

Indicates gate drive fault condition

7

UVLO

R

0b Indicates undervoltage lockout fault co ndi ti on

6

OTSD

R

0b Indicates overtemperature shutdown

5

VDS_HA

R

0b

Indicates VDS overcurrent fault on the A high-si d e MOSFET

4

VDS_LA

R

0b

Indicates VDS overcurrent fault on the A low-si d e MOSFET

3

VDS_HB

R

0b

Indicates VDS overcurrent fault on the B high-si d e MOSFET

2

VDS_LB

R

0b

Indicates VDS overcurrent fault on the B low-si d e MOSFET

1

VDS_HC

R

0b

Indicates VDS overcurrent fault on the C high-si d e M O SFET

0

VDS_LC

R

0b

Indicates VDS overcurrent fault on the C low-si d e MOSFET

I TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.li.com copyngmcc) 201772022, Texas \nstrumenls \noorpaated SubmtDocumentatmn Feedback 55 Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

55

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.6.1.2

Fault Status Register 2 (address = 0x01)

The fault status register 2 is shown in Figure 47 and described in Table 13.

Register access t y pe: Read only

Figure 47. Fault Status Register 2

10

9

8

7

6

5

4

3

2

1

0

SA_OC

SB_OC

SC_OC

OTW

CPUV

VGS_HA

VGS_LA

VGS_HB

VGS_LB

VGS_HC

VGS_LC

R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b

Table 13. Faul t Status Register 2 Fie ld Descriptions

Bit

Field

Typ e

Default

Description

10 SA_OC

R

0b

Indicates overcurrent on phase A sense amplifier (DRV8323xS)

9

SB_OC

R

0b

Indicates overcurrent on phase B sense amplifier (DRV8323xS)

8

SC_OC

R

0b Indicates overcurrent on phase C sense amplifier (DRV8323xS)

7

OTW

R

0b Indicates

overtemperature warning

6

CPUV

R

0b Indicates charge pump undervoltage fault condition

5

VGS_HA

R

0b Indicates gate drive fault on the A high-si d e MOSFET

4

VGS_LA

R

0b Indicates gate drive fault on the A low-si d e MOSFET

3

VGS_HB

R

0b Indicates gate drive fault on the B high-si d e MOSFET

2

VGS_LB

R

0b Indicates gate drive fault on the B low-si d e MOSFET

1

VGS_HC

R

0b Indicates gate drive fault on the C high-si d e M O SFET

0

VGS_LC

R

0b Indicates gate drive fault on the C low-si d e MOSFET

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com Access Typw Code Dwscriplion Wme 31tulhlsmttopmaHMOSFETslnIhe Hl-Z 51am Wme a 1 to this mno clearlamhedtauu bus THIS bll autumancauy reamsaner hex ng wnllen 55 Submt Docunentanon Feedbacﬁ Cnpy ngm© 201772022 Texas \rstrumenls \nmrpualed Fruducl Fomeerbs DRV8320 DRva320R DRV5323 DRvaszsR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

56

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.6.2

Control Registers

The control registers are used to configure the device. The control registers are read and write capable

Complex bit access types are encoded to fit into small table cells. Table 14 shows the codes that are used for

access types in this section.

Table 14. Control Registe rs Access Type Codes

Access Typ e

Code

Description

Read Type

R

Read

Write Type

W W Wri te

Reset or Default Value

-n

Value after reset or the default va l ue

8.6.2.1

Driver Control Register (address = 0x02)

The driver control register is shown in Figure 48 and described in Table 15.

Register access t y pe: Read/Write

Figure 48. Driver Control Registe r

10

9

8

7

6

5

4

3

2

1

0

Reserved

DIS

_CPUV

DIS

_GDF

OTW

_REP PWM_MODE

1PWM

_COM

1PWM

_DIR COAST BRAKE

CLR

_FLT

R/W-0b R/W-0b R/W-0b R/W-0b R/W-00b

R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 15. Driver Control Field Descriptions

Bit

Field

Typ e

Default

Description

10 Reserved R/W 0b Reserved

9

DIS_CPUV R/W 0b 0b = Charge pump UVLO fault is enabled

1b = Charge pump UVLO fault is disabled

8

DIS_GDF R/W 0b 0b = Gate driv e fault is enabled

1b = Gate dri ve fault is disabled

7

OT W_REP R/W 0b 0b = O TW is not reported on nFAULT or the FAULT bit

1b = OTW is reported on nFAULT and the FAULT bit

6-5 PWM_MODE R/W 00b 00b = 6x PWM Mode

01b = 3x PWM mode

10b = 1x PWM mode

11b = Independent PWM m ode

4

1PWM_COM R/W 0b 0b = 1x PWM mode uses synchronous rectification

1b = 1x PWM mode uses asynchronous rectification (diode

freewheeling)

3

1PWM_DIR R/W 0b

In 1x PWM mode this bit is ORed with the INHC (DIR) input

2

COAST R/W 0b

Wri te a 1 to this bit to put all MOSFETs in the Hi-Z state

1

BRAKE R/W 0b Wri te a 1 to this bit to turn on all three low-si d e MOSFETs in

1x

PWM mode.

This bit is ORed with the INLC (BRAKE) input.

0

CLR_FLT R/W 0b Wri te a 1 to this bit to clear latched fault b i t s.

This bit automatically resets after being written.

I TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.li.com copyngmcc) 201772022, Texas \nstrumenls moorpaated SubmtDocumentatmn Feedback 57 Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

57

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.6.2.2

Gate Drive HS Register (address = 0x03)

The gate dri ve HS register is shown in Figure 49 and described in Table 16.

Register access t y pe: Read/Write

Figure 49. Gate Drive HS Register

10

9

8

7

6

5

4

3

2

1

0

LOCK

IDRIVEP_HS

IDRIVEN_HS

R/W-011b

R/W-1111b

Table 16. Gate Drive HS Field Descriptions

Bit

Field

Typ e

Default

Description

10-8 LOCK R/W 011b Wri te 110b to l ock the settings by ignoring further register wri tes

except to these bits and address 0x02 bits 0-2.

Writing any sequence other than 110b has no effect when

unlocked.

Wri te 011b to this register to unlock all registers.

Writing any sequence other than 011b has no effect when

locked.

7-4 IDRIVEP_HS R/W 1111b 0000b = 10 mA

0001b = 30 mA

0010b = 60 mA

0011b = 80 mA

0100b = 120 mA

0101b = 140 mA

0110b = 170 mA

0111b = 190 mA

1000b = 260 mA

1001b = 330 mA

1010b = 370 mA

1011b = 440 mA

1100b = 570 mA

1101b = 680 mA

1110b = 820 mA

1111b = 1000 mA

3-0 IDRIVEN_HS R/W 1111b 0000b = 20 mA

0001b = 60 mA

0010b = 120 mA

0011b = 160 mA

0100b = 240 mA

0101b = 280 mA

0110b = 340 mA

0111b = 380 mA

1000b = 520 mA

1001b = 660 mA

1010b = 740 mA

1011b = 880 mA

1100b = 1140 mA

1101b = 1360 mA

1110b = 1640 mA

1111b = 2000 mA

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

58

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.6.2.3

Gate Drive LS Register (address = 0x04)

The gate dri ve LS register is shown in Figure 50 and described in Table 17.

Register access t y pe: Read/Write

Figure 50. Gate Drive LS Registe r

10

9

8

7

6

5

4

3

2

1

0

CBC

TDRIVE

IDRIVEP_LS

IDRIVEN_LS

R/W-1b R/W-11b

R/W-1111b

Table 17. Gate Drive LS Registe r Field De scri ptions

Bit

Field

Typ e

Default

Description

10 CBC R/W 1b Cycle-by cycle operation. In retry OCP_MODE, for both

VDS_OCP and SEN_OCP, the fault is automatically cleared

when a PWM input is given

9-8 TDRIVE R/W 11b 00b = 500-ns peak gate-current drive time

01b = 1000-ns peak gate-current drive time

10b = 2000-ns peak gate-current drive time

11b = 4000-ns peak gate-current driv e time

7-4 IDRIVEP_LS R/W 1111b 0000b = 10 mA

0001b = 30 mA

0010b = 60 mA

0011b = 80 mA

0100b = 120 mA

0101b = 140 mA

0110b = 170 mA

0111b = 190 mA

1000b = 260 mA

1001b = 330 mA

1010b = 370 mA

1011b = 440 mA

1100b = 570 mA

1101b = 680 mA

1110b = 820 mA

1111b = 1000 mA

3-0 IDRIVEN_LS R/W 1111b 0000b = 20 mA

0001b = 60 mA

0010b = 120 mA

0011b = 160 mA

0100b = 240 mA

0101b = 280 mA

0110b = 340 mA

0111b = 380 mA

1000b = 520 mA

1001b = 660 mA

1010b = 740 mA

1011b = 880 mA

1100b = 1140 mA

1101b = 1360 mA

1110b = 1640 mA

1111b = 2000 mA

I TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.li.com copyngmcc) 201772022, Texas \nstrumenls moorpaated SubmtDocumentatmn Feedback 59 Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

59

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.6.2.4

OCP Control Register (address = 0x05)

The OCP control register is shown in Figure 51 and described in Table 18.

Register access t y pe: Read/Write

Figure 51. OCP Control Register

10

9

8

7

6

5

4

3

2

1

0

TRETRY

DEAD_TIME

OCP_MODE

OCP_DEG

VDS_LVL

R/W-0b R/W-01b

R/W-01b

R/W-1001b

Table 18. OCP Control Field Descriptions

Bit

Field

Typ e

Default

Description

10 TRETRY R/W 0b 0b = VDS_OCP and SEN_OCP retry time is 4 ms

1b = VDS_OCP and SEN_OCP retry time is 50 µs

9-8 DEAD_TIME R/W 01b 00b = 50-ns dead time

01b = 100-ns dead time

10b = 200-ns dead time

11b = 400-ns dead time

7-6 OCP_MODE R/W 01b 00b = Overcurrent causes a latched fault

01b = Ov ercurrent causes an automatic retrying fault

10b = Overcurrent is report only but no action is taken

11b = Overcurrent is not reported and no action is taken

5-4 OCP_DEG R/W 01b 00b = Overcurrent deglitch time of 2 µs

01b = Ov ercurrent deglitch time of 4 µs

10b = Overcurrent deglitch time of 6 µs

11b = Overcurrent deglitch time of 8 µs

3-0 VDS_LVL R/W 1001b 0000b = 0.06 V

0001b = 0.13 V

0010b = 0.2 V

0011b = 0.26 V

0100b = 0.31 V

0101b = 0.45 V

0110b = 0.53 V

0111b = 0.6 V

1000b = 0.68 V

1001b = 0.75 V

1010b = 0.94 V

1011b = 1.13 V

1100b = 1.3 V

1101b = 1.5 V

1110b = 1.7 V

1111b = 1.88 V

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

60

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

8.6.2.5

CSA Control Register (DRV8323x Only) (address = 0x06)

The CSA control register is shown in Figure 52 and described in Table 19.

Register access t y pe: Read/Write

This register is only available with the DRV8323x family of devices.

Figure 52. CSA Control Register

10

9

8

7

6

5

4

3

2

1

0

CSA

_FET

VREF

_DIV

LS

_REF

CSA

_GAIN

DIS

_SEN

CSA

_CAL_A

CSA

_CAL_B

CSA

_CAL_C

SEN

_LVL

R/W-0b R/W-1b R/W-0b R/W-10b

R/W-0b R/W-0b R/W-0b R/W-0b R/W-11b

Table 19. CSA Control Field Descriptions

Bit

Field

Typ e

Default

Description

10 CSA_FET R/W 0b 0b = Current sense amplifier positiv e input is SPx

1b = Current sense amplifier positive input is SHx (a l so

automatically se t s the LS_REF bit to 1)

9

VREF_DIV R/W 1b 0b = Current sense amplifier reference voltage is VREF

(unidirectional mode)

1b = Current sense amplifier reference voltage is VREF

div ided by 2

8

LS_REF R/W 0b 0b = VDS_OCP for the low -side MOSFET is measured

across SHx to SPx

1b = VDS_OCP for the low-si d e MOSFET is measured across

SHx to SNx

7-6 CSA_GAIN R/W 10b 00b = 5-V/V current sense amplifier gain

01b = 10-V/V current sense amplifier gain

10b = 20-V/V current sense amplifier gain

11b = 40-V/V current sense amplifier gain

5

DIS_SEN R/W 0b 0b = Sense ov ercurrent fault is enabled

1b = Sense overcurrent fault is disabled

4

CSA_CAL_A R/W 0b 0b = Normal current sense amplifier A operation

1b = Short inputs to current sense amplifier A for offset

calibration

3

CSA_CAL_B R/W 0b 0b = Normal current sense amplifier B operation

1b = Short inputs to current sense amplifier B for offset

calibration

2

CSA_CAL_C R/W 0b 0b = Normal current sense amplifier C operation

1b = Short inputs to current sense amplifier C for offset

calibration

1-0 SEN_LVL R/W 11b 00b = Sense OCP 0.25 V

01b = Sense OCP 0.5 V

10b = Sense OCP 0.75 V

11b = Sense OCP 1 V

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R wwaLcom copyngmcc) 201772022, Texas \nslrumenls \nmrpaaled Sunmmacumentanon Feedback 61 Fmducl Fomeerls DRV8320 DRV8320R DRV8323 DRV8323R

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

61

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

9

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s c ust omers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1

Application Information

The DRV832x family of devices is primarily used in applications for three-phase brushless DC motor control. The

design procedures in the Typical Application section highlight how to use and configure the DRV 832x family of

devices.

9.2

Typical Application

9.2.1

Primary Appl icati on

The DRV8323R SPI device is used in this application example.

DRV8320, DRV8320R GEIoGGV eaamA I TEXAS INSTRUMENTS www.ﬂ.com INLC — m u o o o 3 E 3 % I z I 3 E z o “6 In m w (I) o w m o m In (/7 (I) m w m (a N N m a e N r: v f v e v e N v N N N N N A) A) z D. I I z I J A. z In m w (I) o o m o m In VM M M '1 N g :5 g I q} w—¢ -—> A a ,_ I‘G_FA‘F% a} ,_ SPA Rams SNA v 62 SubmtDocunenIaIIan Feedbact capyngnm 201772022 Tex§ IrsIIIImenIs InmrpaaIea Fmducl FoIderLInls DRV8320 DRV83217R DRV8323 DRVBSZSR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

62

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Typical Application (continued)

VCC 0.8 to 60 V, 600 mA LOUT

0.1

VM VM VM VM VM

Figure 53. Primary Appl icati on Schematic

COUT

VM

CIN

100 kO

RFB1

1

36

FB DVDD

3.3 V, 30 mA

1 µF

RFB2

2

35

PGND AGND

3

34

CPL CAL

47 nF

4

33

CPH ENABLE

VM

5

32

VCP nSCS

1 µF

6

31

VCC

VM SCLK

µF

7

30

VDRAIN VDRAIN SDI

10 kO

VCC

8

29

GHA

SDO

10 kO

9 28

SHA

nFAULT

10 27

VCC

GLA

DGND

11

26

1 µF

SPA

VREF

12 25

SNA

SOA

GND

(PAD)

GHA

SHA

A

GLA

SPA

RSENSE

SNA

VDRAIN

GHB

SHB

B

GLB

SPB

RSENSE

SNB

GHC

SHC

C

GLC

SPC

RSENSE

SNC

+

13

48

SNB

nSHDN

14

47

SPB

VIN

15

46

GLB

NC

16

45

SHB

SW

17

44

0.1 µF

GHB

CB

18

43

GHC

BGND

19

42

SHC

INLC

20

41

GLC

INHC

21

40

SPC

INLB

22

39

SNC

INHB

23

38

SOC

INLA

24

37

SOB

INHA

I TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R www.li.com System ammennemperamre rzn°mo+1us°c copyngmcc) 201772022, Texas \nstrumenls \noorpaated SubmtDocumentatmn Feedback 63 Pmduct Fo‘deerbs DRV8320 DRV8320R DRVB323 DRvaszsR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

63

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Typical Application (continued)

9.2.1.1

Desi g n Requirements

Table 20 lists the example input parameters for the system design.

Table 20. De si gn Parameters

EXAMPLE DESIGN PARAMETER

REFERENCE

EXAMPLE VALUE

Nominal supply voltage VVM

24 V

Supply voltage range

8 V to 45 V

MOSFET part number

CSD18536KCS

MOSFET total gate charge Qg 83 nC (typical) at VVGS = 10 V

MOSFET gate to drain charge

Q

gd 14 nC (typical)

Target output ri se time

t

r

100 to 300 ns

Target output fall time tf 50 to 150 ns

PWM Frequency

ƒ

PWM 45 kHz

Buck regulator output voltage

V

VCC

3.3 V

Maximum m otor current I

max

100 A

ADC reference voltage

V

VREF 3.3 V

Winding sense current range

ISENSE

–40 A to +40 A

Motor RMS current

I

RMS 28.3 A

Sense re si st o r power rating P

SENSE

2 W

S yst e m ambient temperature

TA

–20°C to +105°C

9.2.1.2

Detailed Desi g n Procedure

9.2.1.2.1

External M OSFET Support

The DRV832x MOSFET support is based on the capacity of the charge pump and PWM switching frequenc y of

the output. For a quick calculation of MOSFET driving capacity, use Equation 9 and Equation 10 for three phase

BLDC motor applications.

Trapezoidal 120° Commutation: IVCP > Qg × ƒPWM

where

•

ƒPWM is the max imum desired PWM sw itching frequency.

•

IVCP is the charge pump capacity, w hich depends on the VM pin voltage.

•

The multiplier based on the commutation control method, may vary based on implementation. (9)

Sinusoidal 180° Commutation: IVCP > 3 × Qg × ƒPWM (10)

9.2.1.2.1.1 Exa m p l e

If a system with a VVM voltage of 8 V (IVCP = 15 mA) uses a maximum PWM switching frequency of 45 k Hz , t hen

the charge pump can support MOSFETs using trapezoidal commutation with a Qg less than 333 nC, and

MOSFETs using sinusoidal commutation with a Qg less than 111 nC.

9.2.1.2.2

IDRIV E Configuration

The strength of the gate drive current, IDRIVE, is selected based on the gate-to-drain charge of the external

MOSFETs and the target rise and fall times at the outputs. If IDRIVE is selected to be too low for a given

MOSFET, then the MOSFET may not turn on completely within the tDRIVE time and a gate drive fault may be

asserted. Additionally, slow rise and fall times result in higher switching power losses. TI recommends adjust ing

these values in the system with the required external MOSFETs and motor to determine the best possible setting

for any application.

The IDRIVEP and IDRIVEN current for both the low-side and high-side MOSFETs are independently adjustable on

SPI devices through the SPI registers. On hardware interface devices, both source and sink settings are selected

at the same time on the IDRIVE pin.

I TEXAS DRV8320, DRVBSZDR INSTRUMENTS www.n.:om OSFETS w on 11 and Q a 'DRIVEP > I; r 0 a IDRIVEN > T 1 on 13 and E nC and a 14 M) IDRIVEW : m :140 mA 14nC 7 IDRIVEP2 = 300 "S 47 mA Use Equation 15 and Equation 16 to harge of 14 n0 and a faH time from 14 n0 I : : 280 mA DRIVEN1 50 ns 14 nC IDRNEN2 : = 93 mA 150 ns 64 Submf Docunemauon Fee-mac; Copy ngm© 201772022, Tex§ 1mlruments1nmrporated Pmducl Foldeerls DRV8320 DRV8320R DRV6323 DRV8323R

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

64

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

For MOSFETs with a known gate-to-drain charge Qgd

, desired rise time (tr), and a desired fall time (tf), use

Equation 11 and Equation 12 to calculate the value of IDRIVEP and IDRIVEN (respectively).

IDRIVEP

IDRIVEN

>

Qgd

tr

>

Qgd

tf

(11)

(12)

9.2.1.2.2.1 Exa m p l e

Use Equation 13 and Equation 14 to calculate the value of IDRIVEP1 and IDRIVEP2 (respectively) for a gate-to-drain

charge of 14 nC and a rise time from 100 to 300 ns.

IDRIVEP1

IDRIVEP2

= 14 nC

100 ns

= 14 nC

300 ns

= 140 m

= 47 mA

(13)

(14)

Select a value for IDRIVEP that is between 47 mA and 140 mA. For this example, the value of IDRIVEP was selected

as 120-mA source.

Use Equation 15 and Equation 16 to calculate the value of IDRIVEN1 and IDRIVEN2 (respectively) for a gate-to-drain

charge of 14 nC and a fall time from 50 to 150 ns.

IDRIVEN1

==

14 nC

==

280 mA

50 ns

(15)

IDRIVEN2 = 14 nC

150 ns = 93 mA

(16)

Select a value for IDRIVEN that is between 93 mA and 280 mA. For this example, the value of IDRIVEN was selected

as 240-mA sink.

9.2.1.2.3

VDS Overcurrent Monitor Configuration

The VDS monitors are configured based on the worst-case motor current and the RDS(on) of the external

MOSFETs as shown in Equation 17.

VDS _ OCP > Imax x RDS(on)max (17)

9.2.1.2.3.1

Exa m p l e

The goal of this example is to set the VDS monitor to trip at a current greater than 100 A. According to the

CSD18536KCS 60 V N-Channel NexFET™ Power MOSFET data sheet, the RDS( on) value is 1.8 times higher at

175°C, and the maximum RDS(on) value at a VGS of 10 V is 1.6 mΩ. From these values, the approximate worst-

case value of RDS(on) is 1.8 × 1.6 mΩ = 2.88 mΩ.

Using Equation 17 with a value of 2.88 mΩ for RDS(on) and a worst-case motor current of 100 A, Equation 18

shows the calculated the value of the VDS monitors.

VDS _ OCP > 100 A x 2.88 mΩ

VDS _ OCP > 0.288 V

For this example, the value of VDS_OCP was selected as 0.31 V.

(18)

The SPI devices allow for adjustment of the deglitch time for the VDS overcurrent monitor. The deglitch time can

be set to 2 µs, 4 µs, 6 µs, or 8 µs.

9.2.1.2.4

Sense Am plifier Bidirectional Configuration (DRV8323 and DRV8323R)

The sense amplifier gain on the DRV8323, DRV8323R devices and sense resistor value are selec t ed based on

the target current range, VREF voltage supply, power rating of the sense resistor, and operating temperature

range. In bidirectional operation of the sense amplifier, the dynamic range at the output is approximately

calculated as shown in Equation 19.

I TEXAS INSTRUMENTS www.u.:om V V0 : (VVREF ’0-25 ‘0’? Use Equation 20 to calculate the app quation 18, V0 AV xl rom Equation 19 and Equation 20, se R = PSENSE > |RMS2 X R hemlueo putiso. 5413 vo=(33v70,25v)7%:1,4v 7 14v 2 Rim 2W>28.3 xRaR<2.5mq 2.5mﬂ="">i~>Av>14 AVX4OA DRV8320, DRV832DR 8323R -wmwmw_-7 VEE Figure 54. Gale Drivea(20% Duty Cycle Figure 55. cam Driveatan% Duty Cycle Copy Hgm© 201772022, Texas Inslrumenls inocrpa’ated SubmtDDcumntation Feedback 65 Pmducl Foldeerlﬁ DRV8320 DRV8320RDRV8323 DRV8323R

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

65

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

O

Figure 55. Gate Driv e at 80% Duty Cyc le

Figure 54. Gate Driv e at 20% Duty Cyc le

V

=

0

V

-

0.25 V

)

-

VVREF

O VREF 2 (19)

Use Equation 20 to calculate the approximate value of the selected sense resistor with VO calculated using

Equation 19.

R = VO P

I 2 x R

AV x I SENSE R MS

(20)

From Equation 19 and Equation 20, select a target gain setting based on the power rating of the target sense

resistor.

9.2.1.2.4.1

Exa m p l e

In this system example, the value of the VREF voltage is 3.3 V with a sense current from –40 to +40 A. The

linear range of the SOx output is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential range

of the sense amplifier input is –0.3 to +0.3 V (VDIFF).

V = (3.3 V - 0.25 V)

- 3.3 V = 1.4 V

2

(21)

R = 1.4 V

AV x 40 A 2 W > 28.32 x R ➔ R < 2.5 mn

(22)

2.5 mn > 1.4 V

AV x 40 A

➔ AV

>

14

(23)

Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be

less than 2.5 mΩ to meet the power rating for the sense resistor. For this example, the gain setting was s elec ted

as 20 V/V. The value of the resistor and worst case current can be verified that R < 2.5 mΩ and Imax = 40 A does

not violate the differential range specification of the sense amplifier input (VSPxD).

9.2.1.2.5 Bu ck Regulator Configuration (DRV8320R and DRV8323R)

For a detailed design procedure and information on selecting the correct buck regulator external components,

refer to the LMR16006 SIMPLE SWITCHER® 60 V 0.6 A Buck Regulators With High Efficiency Eco-mode data

sheet.

9.2.1.3 Application Curves

i TEXAS DRV8320, DRV8320R INSTRUM ENTS www.n.:om Cm ‘ WIT mm 11117111? IT If u ‘ ' ”W ' :';'”'.“uiji"v”f*:"¢m5 66 Subml Documentahan Feedback Copy ngm© 201772022, Texas \rslrumenls Inmrpnrated Pmducl Folder Lmlﬁ DRV8320 DRV8320RDRV8323 DRV8323R

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

66

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Figure 56. BLDC Motor Commutation 1000 RPM

Figure 57. BLDC Motor Commutation 2000 RPM

Figure 58. IDRIVE Maximum Setting Positiv e Current

Figure 59. IDRIVE Maximum Setting Negativ e Current

Figure 61. IDRIVE Minimum Setting Negativ e Current

Figure 60. IDRIVE Minimum Setting Positiv e Current

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

67

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Figure 63. IDRIVE 260 to 520-mA Setting Positiv e Current

Figure 62. IDRIVE 260 to 520-mA Setting Negative Current

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.n.com 35 33V,30mA 2 35 1MP _ <5— .="" .="" ,="" i="" i="" _|__="" cph="" .="" :="" enable="" vm="" 5="" von="" :="" i="" so:="" i="" n="" “if:="" i="" :="" i="" “f="" 7="" vm="" i="" i="" sclk="" i="" q;="" vdrain="" :="" :="" sdi="" a="" i="" i="" gha="" :="" :="" sdo="" a="" i="" i="" i="" m="" sha="" i="" i="" hfault="" e—="" gla="" :="" $7="" i="" dgnd="" ii="" l="" -'="" spa="" spa="" vref="" 12="" sna="" sna="" 50a="" m="" m="" b="" iii="" iii:="" 2="" u="" u="" u="" 0="" $="" %="" w="" %="" (9="" w="" i%="" o="" i%="" %="" 13="" m="" m="" 15="" m="" 16="" m="" 17="" m="" 18="" m="" ‘9="" m="" 20="" m="" 21="" m="" 22="" 23=""><37 soc="" 24=""><37 sob="" g="" g="" vm="" vm="" 4-)%2="">

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

68

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

9.2.2

Alternative Application

In this application, one sense amplifier is used in unidirectional mode for a summing current sense scheme often

used in trapezoidal or hall-based BLDC commutation control.

0.8 to 60 V, 600 mA LOUT

VCC

0.1

VM VM VM VM VM

Figure 64. Alternative Application Schematic

COUT

VM

CIN

100 kO

RFB1

1

36

FB DVDD

3.3 V, 30 mA

1 µF

RFB2

2

35

PGND AGND

3

34

CPL CAL

47 nF

4

33

CPH ENABLE

VM

5

32

VCP nSCS

1 µF

6

31

VCC

VM SCLK

µF

7

30

VDRAIN VDRAIN SDI

10 kO

VCC

8

29

GHA

SDO

10 kO

9 28

SHA

nFAULT

10 27

VCC

GLA

DGND

11

26

1 µF

SPA

VREF

12 25

SNA

SOA

GND

(PAD)

VDRAIN

GHA

GHB

GHC

SHA

SHB

A

B

SHC

C

GLA

GLB

GLC

SPA

SPB

SPC

RSENSE

SNA

+

13

48

SNB

nSHDN

14

47

SPB

VIN

15

46

GLB

NC

16

45

SHB

SW

17

44

0.1 µF

GHB

CB

18

43

GHC

BGND

19

42

SHC

INLC

20

41

GLC

INHC

21

40

SPC

INLB

22

39

SNC

INHB

23

38

SOC

INLA

24

37

SOB

INHA

I TEXAS INSTRUMENTS wwaLcom Sense-reasor power rating DRV8320, DRV8320R 8323R e Equatign 25 to calcu‘ate the appro V A O PSENSE > IRMS2 X R V XI where . vO : v‘,REF 70.5 v rorn Equation 24 and Equation 25, s R; V0 :3.3V70.5V:2.8V 3W>28.32 xRaR<3.75m§) ~=""> AV >18.7 Copy ngm© 2017720219”: \nslmmenls \nmrpaaled Subrm‘ Documentation Feedback Fmducl Fomeerls DRV8320 DRV8320R DRV8323 DRV8323R 69

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

69

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

9.2.2.1

Desi g n Requirements

Table 21 lists the example design input parameters for system design.

Table 21. De si gn Parameters

EXAMPLE DESIGN PARAMETER

REFERENCE

EXAMPLE VALUE

ADC reference voltage

V

VREF 3.3 V

Sensed current

I

SENSE 0 to 40 A

Motor RMS current I

RMS

28.3 A

Sense-resistor power rating

P

SENSE

3 W

S yst e m ambient temperature

T

A

–20°C to +105°C

9.2.2.2

Detailed Desi g n Procedure

9.2.2.2.1

Sense Am plifier Unidirectional Configuration

The sense amplifiers are configured to be unidirectional through the registers on SPI devices by writing a 0 to t he

VREF_DIV bit.

The sense amplifier gain and sense resistor values are selected based on the target current range, VREF, power

rating of the sense resistor, and operating temperature range. In unidirectional operation of the sens e am plifier,

use Equation 24 to calculate the approximate value of the dynamic range at the output.

VO = (VVREF - 0.25 V) - 0.25 V = VVREF - 0.5 V

Use Equation 25 to calculate the approximate value of the selected sense resistor.

(24)

R = VO P

>

I 2 x R

AV x I

where

SENSE R MS

•

VO = VVREF - 0.5 V (25)

From Equation 24 and Equation 25, select a target gain setting based on the power rating of a target sense

resistor.

9.2.2.2.1.1

Exa m p l e

In this system example, the value of the VREF voltage is 3.3 V with a sense current from 0 t o 40 A . The linear

range of the SOx output for the DRV8323x device is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification).

The differential range of the sense-amplifier input is –0.3 to +0.3 V (VDIFF).

VO = 3.3 V - 0.5 V = 2.8 (26)

R = 2.8 V

AV x 40 A 3 W > 28.32 x R ➔ R < 3.75

mΩ

(27)

3.75 mΩ

>

2.8 V

AV x 40 A

➔ AV

>

18.7

(28)

Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be

less than 3.75 mΩ to meet the power rating for the sense resistor. For this example, the gain setting was

selected as 20 V/V. The value of the resistor and worst-case current can be verified that R < 3.75 mΩ and Imax =

40 A does not violate the differential range specification of the sense amplifier input (VSPxD).

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.li.com iner SuppIy Mater DrIve System r ———————— 1 ¢ I ——————————————————— I l I M | . . | | | | | | . | | | Motor DIM: | | | | | | | I : GND | I I I \ I I | LocaI Ic B ymss I <7 i="" |="" bulk="" capamk‘l="" capaciior="" l_="" ________="" |="" i_="" __________________="" 7u="" submt="" documemanan="" feedback="" cnpy="" ngm©="" 201772022="" texas="" irstruments="" inmrpuaied="" fruducl="" foiderlins="" drv8320="" dri/a320r="" drv5323="" drvaszsr="">

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

70

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

Power Supply

Motor Driv e Sy stem

VM

+

Motor D r i ver

GND

Local

Bulk Capacitor

I C B y pass

Capacitor

Parasitic Wire

Inductance

10

Power Supply Recommendations

The DRV832x family of devices is designed to operate from an input voltage supply (VM) range from 6 V to 60 V .

A 0.1-µF ceramic capacitor rated for VM must be placed as close to the device as possible. In addition, a bulk

capacitor must be included on the VM pin but can be shared with the bulk bypass capacitance for t he ex t ernal

power MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs and

should be sized according to the application requirements.

10.1

Bulk Capacitance Sizing

Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The

amount of local capacitance depends on a variety of factors including:

•

The highest current required by the motor system

•

The power supply's type, capacitance, and ability to source current

•

The amount of parasitic inductance between the power supply and motor system

•

The acceptable supply voltage ripple

•

Type of motor (brushed DC, brushless DC, stepper)

•

The motor startup and braking methods

The inductance between the power supply and motor drive system will limit the rate current can change from t he

power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or

dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage

remains stable and high current can be quickly supplied.

The data sheet provides a recommended minimum value, but system level testing is required t o det ermine t he

appropriate sized bulk capacitor.

Figure 65. Motor Drive Supply Parasitics Example

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R wwaLcom copyngmcc) 201772022, Texas Inslrumenls \nmrpaated SubmtDacumentanon Feedback 71 Fmducl Fo‘deerls DRV8320 DRV83217R DRV8323 DRVBSZSR

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

71

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

11

Layout

11.1

Layout Guidelines

Bypass the VM pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of

0.1 µF. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane connected to

the PGND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be

electrolytic. This capacitance must be at least 10 µF.

Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk

capacitance should be placed such that it minimizes the length of any high current paths through the external

MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB

layers. These practices minimize inductance and let the bulk capacitor deliver high current.

Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for

VM, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VM pins.

This capacitor should be 1 µF, rated for 16 V, and be of type X5R or X7R.

Bypass the DVDD pin to the AGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R

or X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the

AGND pin.

The VDRAIN pin can be shorted directly to the VM pin. However, if a significant distance is bet ween t he devic e

and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side

external MOSFETs. Do not connect the SLx pins directly to PGND. Instead, use dedicated traces to connect

these pins to the sources of the low-side external MOSFETs. These recommendations offer more ac c urat e V DS

sensing of the external MOSFETs for overcurrent detection.

Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of

the device to the high-side power MOSFET gate, then follows the high-side MOSFET sourc e back to the SHx

pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the low-

side MOSFET source back to the PGND pin.

For additional layout guidelines and examples see the Layout Guide for the DRV832x Family of Three-Phase

Smart Gate Drivers application report.

11.1.1

Buck-Regulator Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines help users design a PCB with

the best power conversion performance, thermal performance, and minimized generation of unwanted

electromagnetic interference (EMI):

•

Place the feedback network resistors close to the FB pin and away from the inductor to minimize coupling

noise into the feedback pin.

•

Place the input bypass capacitor close to the VIN pin to decrease copper trace resistance which effects the

input voltage ripple of the device.

•

Place the inductor close to the SW pin to decrease magnetic and electrostatic noise.

•

Place the output capacitor close to the junction of the inductor and the diode. The inductor, di ode, and COUT

trace should be as short as possible to decrease conducted and radiated noise and increase overall

efficiency.

•

Make the ground connection for the diode, CVIN, and COUT as small as possible and tie it to the system

ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the

system ground plane.

For more detail on switching power supply layout considerations refer to the AN-1149 Layout Guidelines for

Switching Power Supplies application report.

I TEXAS DRV8320, DRV8320R INSTRUMENTS www.mcnm Vittfi 4 ourc _, om ouu 72 SubmtDocunentanon Fee-dime; CopyrlgmLf/ 201772022 Texas \rstrumenls mmrpuatea FmductFo‘deerbs DRV8320 DRVBSZURDRV5323 DRVBSZSR

DRV8320, DRV8320R

DRV8323, DRV8323R

SLVSDJ3D – FEBRUARY 2017 – R EVI SED MARCH 2022

www.ti.com

72

Submit Documentation Feedback

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

11.2

Layout Example

S D

G D

D G

D S

INHA 37

INLA 38

INHB 39

INLB 40

INHC 41

INLC 42

BGND 43

CB 44

SW 45

NC 46

VIN 47

nSHDN 48

Thermal Pad

24 SOB

23 SOC

22 SNC

21 SPC D G

20 GLC

19 SHC

18 GHC D S

17 GHB

16 SHB

15 GLB D S

14 SPB

13 SNB D S

S D

G D

S D

G D

D G

D S

Figure 66. Layout Ex am ple

VO

INLC

INH

C

INLB

INH

B

INLA

INH

FB

1

PGND

2

CPL 3

36 DVDD

35 AGND

34 CAL

33

ENABLE

32

nSCS

31 SCLK

30 SDI

29 SDO

28

nFAULT

27 DGND

26 VREF

25 SOA

CAL

ENABLE

nSCS

SCLK

SDI

SO

nFAULT

CPH

4

VCP

5

VM

6

VDRAIN

7

GHA 8

SHA

9

GLA

10

SPA

11

SNA 12

VREF

SOA

SOB

SOC

OUTA

OUTB

OUTC

TEXAS INSTRUMENTS DRV8320, DRV8320R 8323R TECHNICAL TOOLS a. suPPoRTa. DRVESZOR Clmkhere Clmkhere ouch here such here such here Copy thl© 201772022, Taxes \nstrumenls \nwrpaated Submr‘ Documentanon Feedback Fruducl Fo‘deerbs DRV8320 DRva320R DRV5323 DRvaszsR 73

DRV8320, DRV 8320R

DRV8323,

DRV8323R

SLVSDJ3D – FEBRUARY 2017 – REVISED MAR CH 2022

www.ti.com

Submit Documentation Feedback

73

Product Folder L i n ks: DRV8320 DRV8320R DRV8323 DRV8323R

12

Device and Documentation Support

12.1

Device Support

12.1.1

Device Nomenclature

The following figure shows a legend for interpreting the complete device name:

DRV83

Prefix

DRV83 - Three Phase Brushless DC

Series

2 - 60 V dev ice

5 - 100 V dev ice

Sense amplifiers

0 - No sense amplif iers

3 - 3x sense amplif iers

(2) (3) (R) (S) (RGZ) (R)

Tap e and Reel

R - Tape and Reel

T - Small Tape and Reel

Package

RTV - 5 × 5 × 0.75 mm QFN

RTA - 6 x 6 × 0.75 mm QFN

RHA - 6 x 6 × 0.9 mm QFN

RGZ - 7 × 7 × 0.9 mm QFN

Interface

S - SPI interf ace

H - Hardware interf ace

Buck Regulator

[blank] - No buck regulator

R - Buck regulator

12.2

Documentation Support

12.2.1

DRV8320(R), DRV8323(R) Datasheet by Texas Instruments

INFORMATION

HELP

CONTACT US

FOLLOW US