STM32L462 Datasheet by STMicroelectronics

Datasheet Feedback/Errors

This is information on a product in full production.

October 2020 DS11913 Rev 5 1/210

STM32L462CE STM32L462RE

STM32L462VE

Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,

512KB Flash, 160KB SRAM, analog, audio, AES

Datasheet - production data

Features

•Ultra-low-power with FlexPowerControl

– 1.71 V to 3.6 V power supply

– -40 °C to 85/125 °C temperature range

– 145 nA in VBAT mode: supply for RTC and

32x32-bit backup registers

– 22 nA Shutdown mode (5 wakeup pins)

– 106 nA Standby mode (5 wakeup pins)

– 375 nA Standby mode with RTC

– 2.05 µA Stop 2 mode, 2.40 µA with RTC

– 84 µA/MHz run mode

– Batch acquisition mode (BAM)

– 4 µs wakeup from Stop mode

– Brown out reset (BOR)

– Interconnect matrix

•Core: Arm® 32-bit Cortex®-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait-state execution

from Flash memory, frequency up to 80 MHz,

MPU, 100DMIPS and DSP instructions

•Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

– 273.55 CoreMark® (3.42 CoreMark/MHz @

80 MHz)

•Energy benchmark

– 335 ULPMark™ CP score

– 104 ULPMark™ PP score

•Clock Sources

– 4 to 48 MHz crystal oscillator

– 32 kHz crystal oscillator for RTC (LSE)

– Internal 16 MHz factory-trimmed RC (±1%)

– Internal low-power 32 kHz RC (±5%)

– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25 % accuracy)

– Internal 48 MHz with clock recovery

– 2 PLLs for system clock, audio, ADC

•Up to 83 fast I/Os, most 5 V-tolerant

•RTC with HW calendar, alarms and calibration

•Up to 21 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

•12x timers: 1x 16-bit advanced motor-control,

1x 32-bit and 3x 16-bit general purpose, 2x 16-

bit basic, 2x low-power 16-bit timers (available

in Stop mode), 2x watchdogs, SysTick timer

•Memories

– 512 KB single bank Flash, proprietary code

readout protection

– 160 KB of SRAM including 32 KB with

hardware parity check

– Quad SPI memory interface

•Rich analog peripherals (independent supply)

– 1x 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

– 1x 12-bit DAC output channels, low-power

sample and hold

– 1x operational amplifier with built-in PGA

– 2x ultra-low-power comparators

– Accurate 2.5 V or 2.048 V reference

voltage buffered output

•AES: 128/256-bit key encryption hardware

accelerator

•17x communication interfaces

– USB 2.0 full-speed crystal less solution

with LPM and BCD

– 1x SAI (serial audio interface)

– 4x I2C FM+(1 Mbit/s), SMBus/PMBus

– 3x USARTs (ISO 7816, LIN, IrDA, modem)

– 1x UART (LIN, IrDA, modem)

– 1x LPUART (Stop 2 wake-up)

UFBGA100 (7×7)

LQFP64 (10×10) UFBGA64 (5×5)

LQFP100 (14×14) WLCSP64 UFQFPN48 (7×7)

(3.36×3.66)

LQFP48 (7×7)

www.st.com

STM32L462CE STM32L462RE STM32L462VE

2/210 DS11913 Rev 5

– 3x SPIs (and 1x Quad SPI)

– CAN (2.0B Active) and SDMMC interface

– IRTIM (Infrared interface)

•14-channel DMA controller

•True random number generator

•CRC calculation unit, 96-bit unique ID

•Development support: serial wire debug

(SWD), JTAG, Embedded Trace Macrocell™

•All packages are ECOPACK2® compliant

DS11913 Rev 5 3/210

STM32L462CE STM32L462RE STM32L462VE Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 17

3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 20

3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 38

3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 38

3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.16 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Contents STM32L462CE STM32L462RE STM32L462VE

4/210 DS11913 Rev 5

3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.21 Digital filter for Sigma-Delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 43

3.22 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.23 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 45

3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.24.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.24.2 General-purpose timers (TIM2, TIM3, TIM15, TIM16) . . . . . . . . . . . . . . 47

3.24.3 Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.24.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 47

3.24.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.24.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.24.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.24.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 49

3.26 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.27 Universal synchronous/asynchronous receiver transmitter (USART) . . . 51

3.28 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 52

3.29 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.30 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.31 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.32 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 54

3.33 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.34 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.35 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.36 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.36.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.36.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

DS11913 Rev 5 5/210

STM32L462CE STM32L462RE STM32L462VE Contents

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 95

6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 95

6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.3.6 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 143

6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 144

6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 157

6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 162

6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 165

6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

6.3.25 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Contents STM32L462CE STM32L462RE STM32L462VE

6/210 DS11913 Rev 5

6.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 170

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

7.2 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.4 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

7.5 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

7.6 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

7.7 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 204

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

DS11913 Rev 5 7/210

STM32L462CE STM32L462RE STM32L462VE List of tables

List of tables

Table 1. STM32L462xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 14

Table 2. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 18

Table 3. STM32L462xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 4. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 5. STM32L462xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 6. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 7. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 8. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 9. DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 10. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 11. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 12. STM32L462xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 13. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 14. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 15. STM32L462xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 16. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 17. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 18. STM32L462xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 86

Table 19. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 20. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 21. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 22. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 23. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 24. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 25. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 26. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 101

Table 27. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 28. Current consumption in Run and Low-power run modes, code with data processing

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 29. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 104

Table 30. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 31. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 32. Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . 106

Table 33. Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 107

Table 34. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 35. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 36. Current consumption in Stop 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 37. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 38. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 39. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 40. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 41. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 42. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

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Table 43. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 44. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 45. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 46. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 47. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 48. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 49. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 50. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 51. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 52. PLL, PLLSAI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 53. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 54. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 55. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 56. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 57. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 58. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 59. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 60. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 61. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 62. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 63. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 64. EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 65. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 66. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 67. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 68. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 69. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 70. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 71. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 72. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 73. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 74. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 75. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 76. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 77. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 78. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 79. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 80. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 81. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 82. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 83. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 84. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 85. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 86. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 87. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 88. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 89. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 90. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 91. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 92. UFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 93. UFBGA100 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 187

Table 94. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

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Table 95. UFBGA64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 96. UFBGA64 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . 193

Table 97. WLCSP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 98. WLCSP64 - Recommended PCB design rules (0.4 mm pitch). . . . . . . . . . . . . . . . . . . . . 197

Table 99. LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 100. UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 101. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 102. STM32L462xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 103. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

List of figures STM32L462CE STM32L462RE STM32L462VE

10/210 DS11913 Rev 5

List of figures

Figure 1. STM32L462xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 4. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 5. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 6. STM32L462Vx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 7. STM32L462Vx UFBGA100 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 8. STM32L462Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 9. STM32L462Rx UFBGA64 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 10. STM32L462Rx WLCSP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 11. STM32L462Cx LQFP48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 12. STM32L462Cx UFQFPN48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 13. STM32L462xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 14. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 15. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 16. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 17. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 18. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 19. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 20. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 21. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 23. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 24. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 25. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 26. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 27. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 28. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 29. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 30. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 31. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 32. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 33. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 34. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 35. Quad SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 36. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 37. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 38. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 39. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 40. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 41. LQFP100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 42. LQFP100 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 43. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 44. UFBGA100 -Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 45. UFBGA100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 46. UFBGA100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 47. LQFP64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 48. LQFP64 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

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Figure 49. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 50. UFBGA64 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 51. UFBGA64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 52. UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Figure 53. WLCSP64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 54. WLCSP64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 55. WLCSP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 56. LQFP48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 57. LQFP48 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 58. LQFP48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 59. UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 60. UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 61. UFQFPN48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 62. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

arm

Introduction STM32L462CE STM32L462RE STM32L462VE

12/210 DS11913 Rev 5

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32L462xx microcontrollers.

This document should be read in conjunction with the STM32L41x, STM32L42x,

STM32L43x, STM32L44x, STM32L45x, STM32L46x reference manual (RM0394), available

from the STMicroelectronics website www.st.com.

For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 Technical

Reference Manual, available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS11913 Rev 5 13/210

STM32L462CE STM32L462RE STM32L462VE Description

2 Description

The STM32L462xx devices are ultra-low-power microcontrollers based on the

high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to

80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision that

supports all Arm® single-precision data-processing instructions and data types. It also

implements a full set of DSP instructions and a memory protection unit (MPU) which

enhances application security.

The STM32L462xx devices embed high-speed memories (Flash memory up to 512 Kbyte,

160 Kbyte of SRAM), a Quad SPI Flash memories interface (available on all packages) and

an extensive range of enhanced I/Os and peripherals connected to two APB buses, two

AHB buses and a 32-bit multi-AHB bus matrix.

The STM32L462xx devices embed several protection mechanisms for embedded Flash

memory and SRAM: readout protection, write protection, proprietary code readout

protection and Firewall.

The devices offer a fast 12-bit ADC (5 Msps), two comparators, one operational amplifier,

one DAC channel, an internal voltage reference buffer, a low-power RTC, one general-

purpose 32-bit timer, one 16-bit PWM timer dedicated to motor control, four general-purpose

16-bit timers, and two 16-bit low-power timers.

In addition, up to 21 capacitive sensing channels are available.

They also feature standard and advanced communication interfaces, namely four I2Cs,

three SPIs, three USARTs, one UART and one Low-Power UART, one SAI, one SDMMC,

one CAN, one USB full-speed device crystal less.

The STM32L462xx devices embed an AES hardware accelerator.

The STM32L462xx operates in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C

(+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive

set of power-saving modes makes possible the design of low-power applications.

Some independent power supplies are supported: analog independent supply input for

ADC, DAC, OPAMP and comparators. A VBAT input makes it possible to backup the RTC

and backup registers.

The STM32L462xx family offers seven packages from 48 to 100-pin packages.

Description STM32L462CE STM32L462RE STM32L462VE

14/210 DS11913 Rev 5

Table 1. STM32L462xx family device features and peripheral counts

Peripheral STM32L462Vx STM32L462Rx STM32L462Cx

Flash memory 512KB

SRAM 160KB

Quad SPI Yes

Timers

Advanced

control 1 (16-bit)

General

purpose

2 (16-bit)

1 (32-bit)

Basic 2 (16-bit)

Low -power 2 (16-bit)

SysTick timer 1

Watchdog

timers

(independent,

window)

Comm.

interfaces

SPI 3

I2C4

USART

UART

LPUART

SAI 1

CAN 1

USB FS Yes

SDMMC Yes No

RTC Yes

Tamper pins 3 2 2

Random generator Yes

AES Yes

GPIOs

Wakeup pins

Capacitive sensing

Number of channels 21 12 6

12-bit ADC

Number of channels

12-bit DAC channels 1

Internal voltage reference

buffer Yes No No

Analog comparator 2

Operational amplifiers 1

DS11913 Rev 5 15/210

STM32L462CE STM32L462RE STM32L462VE Description

Max. CPU frequency 80 MHz

Operating voltage 1.71 to 3.6 V

Operating temperature

Ambient operating temperature:

-40 to 85 °C / -40 to 125 °C

Junction temperature:

-40 to 105 °C / -40 to 130 °C

Packages LQFP100

UFBGA100

WLCSP64

LQFP64

UFBGA64

LQFP48

UFQFPN48

Table 1. STM32L462xx family device features and peripheral counts (continued)

Peripheral STM32L462Vx STM32L462Rx STM32L462Cx

Description STM32L462CE STM32L462RE STM32L462VE

16/210 DS11913 Rev 5

Figure 1. STM32L462xx block diagram

Note: AF: alternate function on I/O pins.

MSv40939V1

Flash

up to

512 KB

GPIO PORT A

EXT IT. WKUP

83 AF

PA[15:0]

TIM1 / PWM

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

USART1

RX, TX, CK,CTS,

RTS as AF

SPI1

MOSI, MISO,

SCK, NSS as AF

APB260 M Hz

APB1 30MHz

OUT1

ITF

WWDG

RTC_TS

OSC32_IN

OSC32_OUT

smcard

IrDA

16b

SDIO / MMC

D[7:0]

CMD, CK as AF

VBAT = 1.55 to 3.6 V

JTAG & SW

ARM Cortex-M4

80 MHz

FPU

NVIC

ETM

MPU

DMA2

ART

ACCEL/

CACHE

RNG

FIFO

@ VDDA

BOR

Supply

supervision

PVD, PVM

Int

reset

XTAL 32 kHz

MAN AGT

RTC

FCLK

Standby

interface

IWDG

@VBAT

@ VDD

@VDD

AWU

Reset & clock

control

PCLKx

Voltage

regulator

3.3 to 1.2 V

VDD Power management

@ VDD

RTC_TAMPx

Backup register

AHB bus-matrix

TIM15

2 channels,

1 compl. channel, BKIN as AF

TIM6

TIM2

D-BUS

SRAM2 32 KB

APB1 80 MHz (max)

SRAM1 128 KB

I-BUS

S-BUS

DMA1

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PH[1:0],

PH[3]

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

GPIO PORT H

16b

TIM16 16b

1 channel,

1 compl. channel, BKIN as AF

16b

32b 4 channels, ETR as AF

OSC_IN

OSC_OUT

HCLKx

XTAL OSC

4- 16MHz

16 external analog inputs

VREF+

USAR T 2MBps

Temperature sensor

@ VDDA

SAI1

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

Touch sensing controller

7 Groups of

4 channels max as AF RC HSI

RC LSI

PLL 1&2

MSI

Quad SPI memory interface

D0[3:0],

D1[3:0],

CLK0,

CLK1

COMP1

INP, INM, OUT

COMP2

INP, INM, OUT

@ VDDA

RTC_OUT

AHB1 80 MHz

CRC

APB2 80MHz

AHB2 80 MHz

FIREWALL

VREF Buffer

@ VDDA

@ VDD

VDD = 1.71 to 3.6 V

VSS

VDDA, VSSA

VDD, VSS, NRST

VDDUSB

TRACECLK

TRACED[3:0]

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

ITF

ADC1

HSI48

AES

AHB/APB1AHB/APB2

VOUT, VINM, VINP

OpAmp1

@VDDA

FIFO

TX, RX as AF

bxCAN1

SCL, SDA, SMBA as AF

I2C3/SMBUS

SCL, SDA, SMBA as AF

I2C2/SMBUS

I2C1/SMBUS SCL, SDA, SMBA as AF

MOSI, MISO, SCK, NSS as AF

SPI3

MOSI, MISO, SCK, NSS as AF

SPI2

USART3 RX, TX, CK, CTS, RTS as AF

smcard

IrDA

USART2 RX, TX, CK, CTS, RTS as AF

smcard

IrDA

CRS CRS_SYNC

USB FS

@ VDDUSB

FIFO

PHY

NOE

LPUART1 RX, TX, CTS, RTS as AF

SWPMI1 IO

RX, TX, SUSPEND as AF

LPTIM1 IN1, IN2, OUT, ETR as AF

LPTIM2 IN1, OUT, ETR as AF

SCL, SDA, SMBA as AF

I2C4/SMBUS

DFSDM

SDCKIN[3:0], SDDATIN[3:0],

SDCKOUT, SDTRIG as AF

UART4 RX, TX, CTS, RTS as AF

IrDA

DAC1

DS11913 Rev 5 17/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for

embedded systems, developed to provide a low-cost platform that meets the needs of MCU

implementation with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced response to interrupts.

The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-

efficiency, delivering the high-performance expected from an Arm® core in the memory size

usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions enabling efficient signal processing and

complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage

development tools, while avoiding saturation.

With its embedded Arm® core, the STM32L462xx family is compatible with all Arm® tools

and software.

Figure 1 shows the general block diagram of the STM32L462xx family devices.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard

Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm®

Cortex®-M4 over Flash memory technologies, which normally requires the processor to wait

for the Flash memory at higher frequencies.

To release the processor near 100 DMIPS performance at 80 MHz, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 80 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole

4 Gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

Functional overview STM32L462CE STM32L462RE STM32L462VE

18/210 DS11913 Rev 5

3.4 Embedded Flash memory

STM32L462xx devices feature up to 512 Kbyte of embedded Flash memory available for

storing programs and data in single bank architecture. The Flash memory contains 256

pages of 2 Kbyte.

Flexible protections can be configured thanks to option bytes:

•Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is

selected

– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial

wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This

selection is irreversible.

•Write protection (WRP): the protected area is protected against erasing and

programming. Two areas can be selected, with 2-Kbyte granularity.

•Proprietary code readout protection (PCROP): a part of the flash memory can be

protected against read and write from third parties. The protected area is execute-only:

it can only be reached by the STM32 CPU, as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.

The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP)

allows the user to select if the PCROP area is erased or not when the RDP protection

is changed from Level 1 to Level 0.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

•single error detection and correction

•double error detection.

Table 2. Access status versus readout protection level and execution modes

Area Protection

level

User execution Debug, boot from RAM or boot

from system memory (loader)

Read Write Erase Read Write Erase

Main

memory

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

System

memory

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

Option

bytes

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

Backup

registers

1YesYesN/A

(1)

1. Erased when RDP change from Level 1 to Level 0.

No No N/A(1)

2 Yes Yes N/A N/A N/A N/A

SRAM2 1 Yes Yes Yes(1) No No No(1)

2 Yes Yes Yes N/A N/A N/A

DS11913 Rev 5 19/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

The address of the ECC fail can be read in the ECC register.

3.5 Embedded SRAM

STM32L462xx devices feature 160 Kbyte of embedded SRAM, split into two blocks:

•128 Kbyte mapped at address 0x2000 0000 (SRAM1)

•32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This memory is also mapped at address 0x2002 0000, offering a contiguous address

space with the SRAM1 (32 Kbyte aliased by bit band)

This block is accessed through the ICode/DCode buses for maximum performance.

These 32 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

3.6 Firewall

The device embeds a Firewall which protects code sensitive and secure data from any

access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

The Firewall main features are the following:

•Three segments can be protected and defined thanks to the Firewall registers:

– Code segment (located in Flash or SRAM1 if defined as executable protected

area)

– Non-volatile data segment (located in Flash)

– Volatile data segment (located in SRAM1)

•The start address and the length of each segments are configurable:

– Code segment: up to 1024 Kbyte with granularity of 256 bytes

– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes

– Volatile data segment: up to 128 Kbyte with a granularity of 64 bytes

•Specific mechanism implemented to open the Firewall to get access to the protected

areas (call gate entry sequence)

•Volatile data segment can be shared or not with the non-protected code

•Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of

protection.

3.7 Boot modes

At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select

one of three boot options:

•Boot from user Flash

•Boot from system memory

•Boot from embedded SRAM

Functional overview STM32L462CE STM32L462RE STM32L462VE

20/210 DS11913 Rev 5

BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the

value of a user option bit to free the GPIO pad if needed.

A Flash empty check mechanism is implemented to force the boot from system flash if the

first flash memory location is not programmed and if the boot selection is configured to boot

from main flash.

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART, I2C, SPI, CAN or USB FS in Device mode through DFU (device firmware

upgrade).

3.8 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.9 Power supply management

3.9.1 Power supply schemes

•VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and

the system analog such as reset, power management and internal clocks. It is provided

externally through VDD pins.

•VDDA = 1.62 V (ADC/COMPs) / 1.8 (DAC/OPAMP) / 2.4 V (VREFBUF) to 3.6 V:

external analog power supply for ADC, DAC, OPAMP, Comparators and Voltage

reference buffer. The VDDA voltage level is independent from the VDD voltage.

•VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The

VDDUSB voltage level is independent from the VDD voltage.

•VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when VDD is not present.

Note: When the functions supplied by VDDA are not used, this supply should preferably be shorted

to VDD.

Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V

tolerant.

Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1, with

VDDIO1 = VDD.

WWE [Jag

DS11913 Rev 5 21/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

Figure 2. Power supply overview

During power-up and power-down phases, the following power sequence requirements

must be respected:

•When VDD is below 1 V, other power supplies (VDDA) must remain below VDD +

300 mV.

•When VDD is above 1 V, all power supplies are independent.

During the power-down phase, VDD can temporarily become lower than other supplies only

if the energy provided to the MCU remains below 1 mJ; this allows external decoupling

capacitors to be discharged with different time constants during the power-down transient

phase.

MSv39216V3

Low voltage detector

VDDA

VDDA domain

VSS

VDD

VBAT

A/D converters

Comparators

D/A converters

Operational amplifiers

Voltage reference buffer

VDD domain

I/O ring

VSSA

Reset block

Temp. sensor

PLL, HSI, MSI, HSI48

Standby circuitry

(Wakeup logic, IWDG)

Voltage regulator

VDDIO1

LSE crystal 32 K osc

BKP registers

RCC BDCR register

RTC

Backup domain

Core

Memories

Digital peripherals

VCORE domain

VCORE

USB transceivers

VDDUSB

VSS

,,,,,,,4, , ,,,,,,,,,,,,,,,,,,,,,,,,,

Functional overview STM32L462CE STM32L462RE STM32L462VE

22/210 DS11913 Rev 5

Figure 3. Power-up/down sequence

1. VDDX refers to VDDA.

3.9.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes

except Shutdown and ensuring proper operation after power-on and during power down.

The device remains in reset mode when the monitored supply voltage VDD is below a

specified threshold, without the need for an external reset circuit.

The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected

through option bytes.The device features an embedded programmable voltage detector

(PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An

interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is

higher than the VPVD threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the device embeds a Peripheral Voltage Monitor which compares the

independent supply voltage VDDA with a fixed threshold in order to ensure that the

peripheral is in its functional supply range.

MSv47490V1

0.3

VBOR0

3.6

Operating modePower-on Power-down time

VDDX(1)

VDD

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD

DS11913 Rev 5 23/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

3.9.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main

regulator (MR) and the low-power regulator (LPR).

•The MR is used in the Run and Sleep modes and in the Stop 0 mode.

•The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is

also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention.

•Both regulators are in power-down in Standby and Shutdown modes: the regulator

output is in high impedance, and the kernel circuitry is powered down thus inducing

zero consumption.

The ultralow-power STM32L462xx supports dynamic voltage scaling to optimize its power

consumption in run mode. The voltage from the Main Regulator that supplies the logic

(VCORE) can be adjusted according to the system’s maximum operating frequency.

There are two power consumption ranges:

•Range 1 with the CPU running at up to 80 MHz.

•Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also

limited to 26 MHz.

The VCORE can be supplied by the low-power regulator, the main regulator being switched

off. The system is then in Low-power run mode.

•Low-power run mode with the CPU running at up to 2 MHz. Peripherals with

independent clock can be clocked by HSI16.

3.9.4 Low-power modes

The ultra-low-power STM32L462xx supports seven low-power modes to achieve the best

compromise between low-power consumption, short startup time, available peripherals and

available wakeup sources.

Functional overview STM32L462CE STM32L462RE STM32L462VE

24/210 DS11913 Rev 5

Table 3. STM32L462xx modes overview

Mode Regulator(1) CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source Consumption(3) Wakeup time

Run MR range 1 Yes ON(4) ON Any All N/A 94 µA/MHz N/A

MR range2 All except USB_FS, RNG 85 µA/MHz

LPRun LPR Yes ON(4) ON

Any

except

PLL

All except USB_FS, RNG N/A 95 µA/MHz to Range 1: 4 µs

to Range 2: 64 µs

Sleep MR range 1 No ON(4) ON(5) Any All Any interrupt or

event

27 µA/MHz 6 cycles

MR range2 All except USB_FS, RNG 27 µA/MHz

LPSleep LPR No ON(4) ON(5) Any

except

PLL

All except USB_FS, RNG Any interrupt or

event 38 µA/MHz 6 cycles

Stop 0

MR Range 1

No OFF ON LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1)

USARTx (x=1...3)(6)

UART4(6)

LPUART1(6)

I2Cx (x=1...4)(7)

LPTIMx (x=1,2)

***

All other peripherals are

frozen.

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1...3)(6)

UART4(6)

LPUART1(6)

I2Cx (x=1...4)(7)

LPTIMx (x=1,2)

USB_FS(8)

125 µA

2.47 µs in SRAM

4.1 µs in Flash

MR Range 2 125 µA

STM32L462CE STM32L462RE STM32L462VE Functional overview

DS11913 Rev 5 25/210

Stop 1 LPR No Off ON LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1)

USARTx (x=1...3)(6)

UART4(6)

LPUART1(6)

I2Cx (x=1...4)(7)

LPTIMx (x=1,2)

***

All other peripherals are

frozen.

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1...3)(6)

UART4(6)

LPUART1(6)

I2Cx (x=1...4)(7)

LPTIMx (x=1,2)

USB_FS(8)

9.85 µA w/o RTC

10.5 µA w RTC

5.7 µs in SRAM

7 µs in Flash

Stop 2 LPR No Off ON LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

I2C3(7)

LPUART1(6)

LPTIM1

***

All other peripherals are

frozen.

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

I2C3(7)

LPUART1(6)

LPTIM1

2.05 µA w/o RTC

2.30 µA w/RTC

5.8 µs in SRAM

8.3 µs in Flash

Table 3. STM32L462xx modes overview (continued)

Mode Regulator(1) CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source Consumption(3) Wakeup time

Functional overview STM32L462CE STM32L462RE STM32L462VE

26/210 DS11913 Rev 5

Standby

LPR

Power

ed Off Off

SRAM

2 ON

LSE

LSI

BOR, RTC, IWDG

***

All other peripherals are

powered off.

***

I/O configuration can be

floating, pull-up or pull-down

Reset pin

5 I/Os (WKUPx)(9)

BOR, RTC, IWDG

0.35 µA w/o RTC

0.52 µA w/ RTC

16.1 µs

OFF

Power

Off

0.10 µA w/o RTC

0.27 µA w/ RTC

Shutdown OFF Power

ed Off Off

Power

Off

LSE

RTC

***

All other peripherals are

powered off.

***

I/O configuration can be

floating, pull-up or pull-

down(10)

Reset pin

5 I/Os (WKUPx)(9)

RTC

0.02 µA w/o RTC

0.17 µA w/ RTC 256 µs

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in

LPRun/LPSleep.

4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

5. The SRAM1 and SRAM2 clocks can be gated on or off independently.

6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. USB_FS wakeup by resume from suspend and attach detection protocol event.

9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

Table 3. STM32L462xx modes overview (continued)

Mode Regulator(1) CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source Consumption(3) Wakeup time

DS11913 Rev 5 27/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the

user to select one of the low-power modes described below:

•Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•Low-power run mode

This mode is achieved with VCORE supplied by the low-power regulator to minimize the

regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

•Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the low-

power run mode.

•Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI

RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still

running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode

to detect their wakeup condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,

most of the VCORE domain is put in a lower leakage mode.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller

wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator

remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI

up to 48 MHz or HSI16, depending on software configuration.

•Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The

internal regulator is switched off so that the VCORE domain is powered off. The PLL, the

MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with

internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1 and register contents are lost except for registers

in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in

Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention

mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset,

WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,

periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

The system clock after wakeup is MSI up to 8 MHz.

Functional overview STM32L462CE STM32L462RE STM32L462VE

28/210 DS11913 Rev 5

•Shutdown mode

The Shutdown mode permits to achieve the lowest power consumption. The internal

regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16,

the MSI, the LSI and the HSE oscillators are also switched off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2 and register contents are lost except for registers in the Backup

domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin

event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic

wakeup, timestamp, tamper).

The system clock after wakeup is MSI at 4 MHz.

DS11913 Rev 5 29/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

Table 4. Functionalities depending on the working mode(1)

Peripheral Run Sleep

Low-

power

run

Low-

power

sleep

Stop 0/1 Stop 2 Standby Shutdown

VBAT

Wakeup capability

CPU Y - Y - - --------

Flash memory (up to

512 KB) O(2) O(2) O(2) O(2) ---------

SRAM1 (128 KB) Y Y(3) YY

(3) Y-Y------

SRAM2 (32 KB) Y Y(3) YY

(3) Y-Y-O

(4) ----

Quad SPI O O O O - --------

Backup registers Y Y Y Y Y -Y-Y-Y-Y

Brown-out reset

(BOR) YYYYYYYYYY- --

Programmable

voltage detector

(PVD)

OOOOO

OOO- ----

Peripheral voltage

monitor (PVMx;

x=1,3,4)

OOOOO

OOO- ----

DMA OOOO-

--------

High speed Internal

(HSI16) OOOO

(5) -(5) ------

Oscillator RC48 O O - - - --------

High speed external

(HSE) OOOO-

--------

Low speed internal

(LSI) OOOOO

-O-O----

Low speed external

(LSE) OOOOO

-O-O-O-O

Multi-Speed internal

(MSI) OOOO-

--------

Clock security

system (CSS) OOOO-

--------

Clock security

system on LSE OOOOO

OOOOO- --

RTC / Auto wakeup O O O O O OOOOOOOO

Number of RTC

Tamper pins 33333O3O3O3O3

Functional overview STM32L462CE STM32L462RE STM32L462VE

30/210 DS11913 Rev 5

USARTx (x=1,2,3)

UART4 OOOOO

(6) O(6) -------

Low-power UART

(LPUART) OOOOO

(6) O(6) O(6) O(6) -----

I2Cx (x=1,2,4) O O O O O(7) O(7) -------

I2C3 OOOOO

(7) O(7) O(7) O(7) -----

SPIx (x=1,2,3) O O O O - --------

CAN OOOO-

--------

SDMMC1 O O O O - --------

SAIx (x=1) O O O O - --------

DFSDM1 OOOO-

--------

ADCx (x=1) O O O O - --------

DAC1 O O O O O --------

VREFBUF O O O O O --------

OPAMPx (x=1) O O O O O --------

COMPx (x=1,2) O O O O O OOO- ----

Temperature sensor O O O O - --------

Timers (TIMx) O O O O - --------

Low-power timer 1

(LPTIM1) OOOOOOOO- ----

Low-power timer 2

(LPTIM2) OOOOO

O- ------

Independent

watchdog (IWDG) OOOOO

OOOOO- --

Window watchdog

(WWDG) OOOO-

--------

SysTick timer O O O O - --------

Touch sensing

controller (TSC) OOOO---------

Random number

generator (RNG) O(8) O(8) -----------

Table 4. Functionalities depending on the working mode(1) (continued)

Peripheral Run Sleep

Low-

power

run

Low-

power

sleep

Stop 0/1 Stop 2 Standby Shutdown

VBAT

Wakeup capability

DS11913 Rev 5 31/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

3.9.5 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is

“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is

deactivated when the reset source is internal.

3.9.6 VBAT operation

The VBAT pin permits to power the device VBAT domain from an external battery, an

external supercapacitor, or from VDD when no external battery and an external

supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup

registers. Three anti-tamper detection pins are available in VBAT mode.

VBAT operation is automatically activated when VDD is not present.

An internal VBAT battery charging circuit is embedded and can be activated when VDD is

present.

Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events

do not exit it from VBAT operation.

CRC calculation unit O O O O - --------

GPIOs OOOOO

OOO(9) 5

pins

(10)

(11) 5

pins

(10) -

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.

2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.

3. The SRAM clock can be gated on or off.

4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by

the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not

need it anymore.

6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or

received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. Voltage scaling Range 1 only.

9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when

exiting the Shutdown mode.

Table 4. Functionalities depending on the working mode(1) (continued)

Peripheral Run Sleep

Low-

power

run

Low-

power

sleep

Stop 0/1 Stop 2 Standby Shutdown

VBAT

Wakeup capability

Functional overview STM32L462CE STM32L462RE STM32L462VE

32/210 DS11913 Rev 5

3.10 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run

and sleep, Stop 0, Stop 1 and Stop 2 modes.

Table 5. STM32L462xx peripherals interconnect matrix

Interconnect source Interconnect

destination Interconnect action

Run

Sleep

Low-power run

Low-power sleep

Stop 0 / Stop 1

Stop 2

TIMx

TIMx Timers synchronization or chaining Y Y Y Y - -

ADCx

DAC1

DFSDM1

Conversion triggers Y Y Y Y - -

DMA Memory to memory transfer trigger Y Y Y Y - -

COMPx Comparator output blanking Y Y Y Y - -

TIM15/TIM16 IRTIM Infrared interface output generation Y Y Y Y - -

COMPx

TIM1

TIM2

Timer input channel, trigger, break from

analog signals comparison YYYY - -

LPTIMERx Low-power timer triggered by analog

signals comparison YYYYYY

(1)

ADCx TIM1 Timer triggered by analog watchdog Y Y Y Y - -

RTC

TIM16 Timer input channel from RTC events Y Y Y Y - -

LPTIMERx Low-power timer triggered by RTC alarms

or tampers YYYYYY

(1)

All clocks sources (internal

and external)

TIM2

TIM15, 16

Clock source used as input channel for

RC measurement and trimming YYYY - -

CSS

CPU (hard fault)

RAM (parity error)

Flash memory (ECC error)

COMPx

PVD

DFSDM1 (analog

watchdog, short circuit

detection)

TIM1

TIM15,16 Timer break Y Y Y Y - -

DS11913 Rev 5 33/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

GPIO

TIMx External trigger Y Y Y Y - -

LPTIMERx External trigger Y Y Y Y Y Y

(1)

ADCx

DAC1

DFSDM1

Conversion external trigger Y Y Y Y - -

1. LPTIM1 only.

Table 5. STM32L462xx peripherals interconnect matrix (continued)

Interconnect source Interconnect

destination Interconnect action

Run

Sleep

Low-power run

Low-power sleep

Stop 0 / Stop 1

Stop 2

Functional overview STM32L462CE STM32L462RE STM32L462VE

34/210 DS11913 Rev 5

3.11 Clocks and startup

The clock controller (see Figure 4) distributes the clocks coming from different oscillators to

the core and the peripherals. It also manages clock gating for low-power modes and

ensures clock robustness. It features:

•Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

•Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

•Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

•System clock source: four different clock sources can be used to drive the master

clock SYSCLK:

– 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply

a PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can

supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate

12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is

available in the system (LSE), the MSI frequency can be automatically trimmed by

hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.

– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency

at 80 MHz.

•RC48 with clock recovery system (HSI48): internal RC48 MHz clock source can be

used to drive the SDMMC or the RNG peripherals. This clock can be output on the

MCO.

•Auxiliary clock source: two ultralow-power clock sources that can be used to drive

the real-time clock:

– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability

modes. The LSE can also be configured in bypass mode for an external clock.

– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock accuracy is ±5% accuracy.

•Peripheral clock sources: Several peripherals (SDMMC, RNG, SAI, USARTs, I2Cs,

LPTimers, ADC) have their own independent clock whatever the system clock. Two

PLLs, each having three independent outputs allowing the highest flexibility, can

generate independent clocks for the ADC, the SDMMC/RNG and the SAI.

•Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz

clock (MSI). The prescaler ratio and clock source can be changed by the application

program as soon as the code execution starts.

•Clock security system (CSS): this feature can be enabled by software. If a HSE clock

failure occurs, the master clock is automatically switched to HSI16 and a software

DS11913 Rev 5 35/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

interrupt is generated if enabled. LSE failure can also be detected and generated an

interrupt.

•Clock-out capability:

–MCO: microcontroller clock output: it outputs one of the internal clocks for

external use by the application. Low frequency clocks (LSI, LSE) are available

down to Stop 1 low power state.

–LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes

down to Standby mode. LSE can also be output on LSCO in Shutdown mode.

LSCO is not available in VBAT mode.

Several prescalers permit to configure the AHB frequency, the high speed APB (APB2) and

the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB

domains is 80 MHz.

LSE HSE svsch Msw HSHG S S msmcm PLUEM2CLK PUADMCM LS‘ svscLK svsm

Functional overview STM32L462CE STM32L462RE STM32L462VE

36/210 DS11913 Rev 5

Figure 4. Clock tree

MSv40980V2

SYSCLK

MCO

LSCO

PLL

to IWDG

to RTC

to PWR

HCLK

to AHB bus, core, memory and DMA

FCLK Cortex free running clock

to Cortex system timer

to APB1 peripherals

to APB2 peripherals

PCLK1

PCLK2

LSE

HSI16

SYSCLK to USARTx

x=2..3

to UART4

to LPUART1

to I2Cx

x=1,2,3,4

to LPTIMx

x=1,2

SAI1_EXTCLK

to TIMx

x=2,6,7

OSC32_OUT

OSC32_IN

MSI HSI16

HSE

HSI16

LSI

LSE

HSE

SYSCLK

HSE

MSI

HSI16

LSE OSC

32.768 kHz /32

AHB PRESC

/ 1,2,..512

/ 8

APB1 PRESC

/ 1,2,4,8,16

x1 or x2

HSI16

SYSCLK

LSI

LSE

HSI16

APB2 PRESC

/ 1,2,4,8,16

to TIMx

x=1,15,16

x1 or x2

to USART1

LSE

HSI16

SYSCLK

/ P

/ Q

/ R

PLLSAI1

/ P

/ Q

/ R

/ M

MSI RC

100 kHz – 48 MHz

HSI RC

16 MHz

HSE OSC

4-48 MHz

Clock

detector

OSC_OUT

OSC_IN

/ 1→16

LSI RC 32 kHz

Clock

source

control

PLLSAI1CLK

PLL48M1CLK

PLLCLK

PLLSAI2CLK

PLL48M2CLK

PLLADC1CLK

HSI48

MSI

PLLCLK

48 MHz clock to USB, RNG, SDMMC

to ADC

to SAI1

MSI

SYSCLK

PLLADC1CLK

HSI16

HSI RC

48 MHz

CRS

SYSCLK to DFSDM1

DS11913 Rev 5 37/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

3.12 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be

achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

3.13 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 6: DMA implementation for the features

implementation.

Direct memory access (DMA) is used in order to provide high-speed data transfer between

peripherals and memory as well as memory to memory. Data can be quickly moved by DMA

without any CPU actions. This keeps CPU resources free for other operations.

The two DMA controllers have 14 channels in total, each dedicated to managing memory

access requests from one or more peripherals. Each has an arbiter for handling the priority

between DMA requests.

The DMA supports:

•14 independently configurable channels (requests)

•Each channel is connected to dedicated hardware DMA requests, software trigger is

also supported on each channel. This configuration is done by software.

•Priorities between requests from channels of one DMA are software programmable (4

levels consisting of very high, high, medium, low) or hardware in case of equality

(example: request 1 has priority over request 2)

•Independent source and destination transfer size (byte, half word, word), emulating

packing and unpacking. Source/destination addresses must be aligned on the data

size.

•Support for circular buffer management

•3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)

logically ORed together in a single interrupt request for each channel

•Memory-to-memory transfer

•Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral

transfers

•Access to Flash, SRAM, APB and AHB peripherals as source and destination

•Programmable number of data to be transferred: up to 65536.

Table 6. DMA implementation

DMA features DMA1 DMA2

Number of regular channels 7 7

Functional overview STM32L462CE STM32L462RE STM32L462VE

38/210 DS11913 Rev 5

3.14 Interrupts and events

3.14.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-

M4.

The NVIC benefits are the following:

•Closely coupled NVIC gives low latency interrupt processing

•Interrupt entry vector table address passed directly to the core

•Allows early processing of interrupts

•Processing of late arriving higher priority interrupts

•Support for tail chaining

•Processor state automatically saved on interrupt entry, and restored on interrupt exit,

with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.14.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 37 edge detector lines used to generate

interrupt/event requests and wake-up the system from Stop mode. Each external line can be

independently configured to select the trigger event (rising edge, falling edge, both) and can

be masked independently. A pending register maintains the status of the interrupt requests.

The internal lines are connected to peripherals with wakeup from Stop mode capability. The

EXTI can detect an external line with a pulse width shorter than the internal clock period. Up

to 83 GPIOs can be connected to the 16 external interrupt lines.

DS11913 Rev 5 39/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

3.15 Analog to digital converter (ADC)

The device embeds a successive approximation analog-to-digital converter with the

following features:

•12-bit native resolution, with built-in calibration

•5.33 Msps maximum conversion rate with full resolution

– Down to 18.75 ns sampling time

– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit

resolution)

•Up to 16 external channels.

•4 internal channels: internal reference voltage, temperature sensor, VBAT/3 and

DAC1_OUT1.

•One external reference pin is available on some package, allowing the input voltage

range to be independent from the power supply

•Single-ended and differential mode inputs

•Low-power design

– Capable of low-current operation at low conversion rate (consumption decreases

linearly with speed)

– Dual clock domain architecture: ADC speed independent from CPU frequency

•Highly versatile digital interface

– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups

of analog signals conversions can be programmed to differentiate background and

high-priority real-time conversions

– ADC supports multiple trigger inputs for synchronization with on-chip timers and

external signals

– Results stored into data register or in RAM with DMA controller support

– Data pre-processing: left/right alignment and per channel offset compensation

– Built-in oversampling unit for enhanced SNR

– Channel-wise programmable sampling time

– Three analog watchdog for automatic voltage monitoring, generating interrupts

and trigger for selected timers

– Hardware assistant to prepare the context of the injected channels to allow fast

context switching

3.15.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.

The temperature sensor is internally connected to the ADC1_IN17 input channel which is

used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall

accuracy of the temperature measurement. As the offset of the temperature sensor varies

from chip to chip due to process variation, the uncalibrated internal temperature sensor is

suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is

individually factory-calibrated by ST. The temperature sensor factory calibration data are

stored by ST in the system memory area, accessible in read-only mode.

Functional overview STM32L462CE STM32L462RE STM32L462VE

40/210 DS11913 Rev 5

3.15.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for

the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input

channel. The precise voltage of VREFINT is individually measured for each part by ST

during production test and stored in the system memory area. It is accessible in read-only

mode.

3.15.3 VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage

using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the VBAT voltage may be

higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally

connected to a bridge divider by 3. As a consequence, the converted digital value is one

third the VBAT voltage.

3.16 Digital to analog converter (DAC)

One 12-bit buffered DAC channel can be used to convert digital signals into analog voltage

signal outputs. The chosen design structure is composed of integrated resistor strings and

an amplifier in inverting configuration.

Table 7. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS ADC raw data acquired at a

temperature of 30 °C (± 5 °C),

VDDA = VREF+ = 3.0 V (± 10 mV)

0x1FFF 75A8 - 0x1FFF 75A9

TS_CAL2

TS ADC raw data acquired at a

temperature of 130 °C (± 5 °C),

VDDA = VREF+ = 3.0 V (± 10 mV)

0x1FFF 75CA - 0x1FFF 75CB

Table 8. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT

Raw data acquired at a

temperature of 30 °C (± 5 °C),

VDDA = VREF+ = 3.0 V (± 10 mV)

0x1FFF 75AA - 0x1FFF 75AB

DS11913 Rev 5 41/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

This digital interface supports the following features:

•Up to two DAC output channels

•8-bit or 12-bit output mode

•Buffer offset calibration (factory and user trimming)

•Left or right data alignment in 12-bit mode

•Synchronized update capability

•Noise-wave generation

•Triangular-wave generation

•Dual DAC channel independent or simultaneous conversions

•DMA capability for each channel

•External triggers for conversion

•Sample and hold low-power mode, with internal or external capacitor

The DAC channels are triggered through the timer update outputs that are also connected

to different DMA channels.

3.17 Voltage reference buffer (VREFBUF)

The STM32L462xx devices embed an voltage reference buffer which can be used as

voltage reference for ADCs, DAC and also as voltage reference for external components

through the VREF+ pin.

The internal voltage reference buffer supports two voltages:

•2.048 V

•2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal

voltage reference buffer is off.

The VREF+ pin is double-bonded with VDDA on some packages. In these packages the

internal voltage reference buffer is not available.

Figure 5. Voltage reference buffer

MSv40197V1

VREFBUF

Low frequency

cut-off capacitor

DAC, ADC

Bandgap +

VDDA

100 nF

VREF+

Functional overview STM32L462CE STM32L462RE STM32L462VE

42/210 DS11913 Rev 5

3.18 Comparators (COMP)

The STM32L462xx devices embed two rail-to-rail comparators with programmable

reference voltage (internal or external), hysteresis and speed (low speed for low-power) and

with selectable output polarity.

The reference voltage can be one of the following:

•External I/O

•DAC output channels

•Internal reference voltage or submultiple (1/4, 1/2, 3/4).

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers

and can be also combined into a window comparator.

3.19 Operational amplifier (OPAMP)

The STM32L462xx embeds one operational amplifier with external or internal follower

routing and PGA capability.

The operational amplifier features:

•Low input bias current

•Low offset voltage

•Low-power mode

•Rail-to-rail input

3.20 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution for adding capacitive sensing

functionality to any application. Capacitive sensing technology is able to detect finger

presence near an electrode which is protected from direct touch by a dielectric (such as

glass or plastic). The capacitive variation introduced by the finger (or any conductive object)

is measured using a proven implementation based on a surface charge transfer acquisition

principle.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware

library which is free to use and allows touch sensing functionality to be implemented reliably

in the end application.

DS11913 Rev 5 43/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

The main features of the touch sensing controller are the following:

•Proven and robust surface charge transfer acquisition principle

•Supports up to 21 capacitive sensing channels

•Up to 3 capacitive sensing channels can be acquired in parallel offering a very good

response time

•Spread spectrum feature to improve system robustness in noisy environments

•Full hardware management of the charge transfer acquisition sequence

•Programmable charge transfer frequency

•Programmable sampling capacitor I/O pin

•Programmable channel I/O pin

•Programmable max count value to avoid long acquisition when a channel is faulty

•Dedicated end of acquisition and max count error flags with interrupt capability

•One sampling capacitor for up to 3 capacitive sensing channels to reduce the system

components

•Compatible with proximity, touchkey, linear and rotary touch sensor implementation

•Designed to operate with STMTouch touch sensing firmware library

Note: The number of capacitive sensing channels is dependent on the size of the packages and

subject to I/O availability.

3.21 Digital filter for Sigma-Delta modulators (DFSDM)

The device embeds one DFSDM with 2 digital filters modules and 4 external input serial

channels (transceivers) or alternately 4 internal parallel inputs support.

The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to

microcontroller and then to perform digital filtering of the received data streams (which

represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse

Density Modulation) microphones and perform PDM to PCM conversion and filtering in

Functional overview STM32L462CE STM32L462RE STM32L462VE

44/210 DS11913 Rev 5

hardware. DFSDM features optional parallel data stream inputs from microcontrollers

memory (through DMA/CPU transfers into DFSDM).

DFSDM transceivers support several serial interface formats (to support various Σ∆

modulators). DFSDM digital filter modules perform digital processing according user

selected filter parameters with up to 24-bit final ADC resolution.

The DFSDM peripheral supports:

•4 multiplexed input digital serial channels:

– configurable SPI interface to connect various SD modulator(s)

– configurable Manchester coded 1 wire interface support

– PDM (Pulse Density Modulation) microphone input support

– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

– clock output for SD modulator(s): 0..20 MHz

•alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):

– internal sources: device memory data streams (DMA)

•2 digital filter modules with adjustable digital signal processing:

–Sinc

x filter: filter order/type (1..5), oversampling ratio (up to 1..1024)

– integrator: oversampling ratio (1..256)

•up to 24-bit output data resolution, signed output data format

•automatic data offset correction (offset stored in register by user)

•continuous or single conversion

•start-of-conversion triggered by:

– software trigger

– internal timers

– external events

– start-of-conversion synchronously with first digital filter module (DFSDM1_FLT0)

•analog watchdog feature:

– low value and high value data threshold registers

– dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)

– input from final output data or from selected input digital serial channels

– continuous monitoring independently from standard conversion

•short circuit detector to detect saturated analog input values (bottom and top range):

– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream

– monitoring continuously each input serial channel

•break signal generation on analog watchdog event or on short circuit detector event

•extremes detector:

– storage of minimum and maximum values of final conversion data

– refreshed by software

•DMA capability to read the final conversion data

•interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial

channel clock absence

•“regular” or “injected” conversions:

– “regular” conversions can be requested at any time or even in continuous mode

DS11913 Rev 5 45/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

without having any impact on the timing of “injected” conversions

– “injected” conversions for precise timing and with high conversion priority

3.22 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated

analog circuit.

3.23 Advanced encryption standard hardware accelerator (AES)

The devices embed an AES hardware accelerator can be used to both encipher and

decipher data using AES algorithm.

The AES peripheral supports:

•Encryption/Decryption using AES Rijndael Block Cipher algorithm

•NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

•128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x

32-bit registers)

•Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois

Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher

Message Authentication Code mode (CMAC) supported.

•Key scheduler

•Key derivation for decryption

•128-bit data block processing

•128-bit, 256-bit key length

•1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer.

•Register access supporting 32-bit data width only.

•One 128-bit Register for the initialization vector when AES is configured in CBC mode

or for the 32-bit counter initialization when CTR mode is selected, GCM mode or

CMAC mode.

•Automatic data flow control with support of direct memory access (DMA) using 2

channels, one for incoming data, and one for outcoming data.

•Suspend a message if another message with a higher priority needs to be processed

Table 9. DFSDM1 implementation

DFSDM features DFSDM1

Number of channels 8

Number of filters 4

Input from internal ADC -

Supported trigger sources 10

Pulses skipper -

ID registers support -

Functional overview STM32L462CE STM32L462RE STM32L462VE

46/210 DS11913 Rev 5

3.24 Timers and watchdogs

The STM32L462xx includes one advanced control timers, up to five general-purpose timers,

two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table

below compares the features of the advanced control, general purpose and basic timers.

3.24.1 Advanced-control timer (TIM1)

The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6

channels. They have complementary PWM outputs with programmable inserted dead-

times. They can also be seen as complete general-purpose timers. The 4 independent

channels can be used for:

•Input capture

•Output compare

•PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

•One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs

disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.24.2) using the same architecture, so the advanced-control timer can work

together with the TIMx timers via the Timer Link feature for synchronization or event

chaining.

Table 10. Timer feature comparison

Timer type Timer Counter

resolution

Counter

type

Prescaler

factor

DMA

request

generation

Capture/

compare

channels

Complementary

outputs

Advanced

control TIM1 16-bit Up, down,

Up/down

Any integer

between 1

and 65536

Yes 4 3

General-

purpose TIM2 32-bit Up, down,

Up/down

Any integer

between 1

and 65536

Yes 4 No

General-

purpose TIM3 16-bit Up, down,

Up/down

Any integer

between 1

and 65536

Yes 4 No

General-

purpose TIM15 16-bit Up

Any integer

between 1

and 65536

Yes 2 1

General-

purpose TIM16 16-bit Up

Any integer

between 1

and 65536

Yes 1 1

Basic TIM6 16-bit Up

Any integer

between 1

and 65536

Yes 0 No

DS11913 Rev 5 47/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

3.24.2 General-purpose timers (TIM2, TIM3, TIM15, TIM16)

There are up to three synchronizable general-purpose timers embedded in the

STM32L462xx (see Table 10 for differences). Each general-purpose timer can be used to

generate PWM outputs, or act as a simple time base.

•TIM2, TIM3

They are full-featured general-purpose timers:

– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.

– TIM3 has 16-bit auto-reload up/downcounter and 16-bit prescaler.

These timers feature 4 independent channels for input capture/output compare, PWM

or one-pulse mode output. They can work with the other general-purpose timers via the

Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoder.

•TIM15 and 16

They are general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has 2 channels and 1 complementary channel

– TIM16 has 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode

output.

The timers can work together via the Timer Link feature for synchronization or event

chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

3.24.3 Basic timer (TIM6)

The basic timer is mainly used for DAC trigger generation. It can also be used as generic

16-bit timebase.

3.24.4 Low-power timer (LPTIM1 and LPTIM2)

The devices embed two low-power timers. These timers have an independent clock and are

running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to

wakeup the system from Stop mode.

LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 is active in Stop 0 and Stop 1 mode.

Functional overview STM32L462CE STM32L462RE STM32L462VE

48/210 DS11913 Rev 5

This low-power timer supports the following features:

•16-bit up counter with 16-bit autoreload register

•16-bit compare register

•Configurable output: pulse, PWM

•Continuous/ one shot mode

•Selectable software/hardware input trigger

•Selectable clock source

– Internal clock sources: LSE, LSI, HSI16 or APB clock

– External clock source over LPTIM input (working even with no internal clock

source running, used by pulse counter application).

•Programmable digital glitch filter

•Encoder mode (LPTIM1 only)

3.24.5 Infrared interface (IRTIM)

The STM32L462xx includes one infrared interface (IRTIM), which can be used with an

infrared LED to perform remote control functions. It uses TIM15 and TIM16 output channels

to generate output signal waveforms on IR_OUT pin.

3.24.6 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 32 kHz internal RC (LSI) and as it operates independently

from the main clock, it can operate in Stop and Standby modes. It can be used either as a

watchdog to reset the device when a problem occurs, or as a free running timer for

application timeout management. It is hardware or software configurable through the option

bytes. The counter can be frozen in debug mode.

3.24.7 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

3.24.8 SysTick timer

This timer is dedicated to real-time operating systems, but can also be used as a standard

down counter. It features:

•A 24-bit down counter

•Autoreload capability

•Maskable system interrupt generation when the counter reaches 0

•Programmable clock source

DS11913 Rev 5 49/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

3.25 Real-time clock (RTC) and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:

•Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format.

•Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

•Two programmable alarms.

•On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize it with a master clock.

•Reference clock detection: a more precise second source clock (50 or 60 Hz) can be

used to enhance the calendar precision.

•Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

inaccuracy.

•Three anti-tamper detection pins with programmable filter.

•Timestamp feature, which can be used to save the calendar content. This function can

be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to

VBAT mode.

•17-bit auto-reload wakeup timer (WUT) for periodic events with programmable

resolution and period.

The RTC and the 32 backup registers are supplied through a switch that takes power either

from the VDD supply when present or from the VBAT pin.

The backup registers are 32-bit registers used to store 128 bytes of user application data

when VDD power is not present. They are not reset by a system or power reset, or when the

device wakes up from Standby or Shutdown mode.

The RTC clock sources can be:

•A 32.768 kHz external crystal (LSE)

•An external resonator or oscillator (LSE)

•The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)

•The high-speed external clock (HSE) divided by 32.

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the

LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in

all low-power modes except Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt

and wakeup the device from the low-power modes.

Functional overview STM32L462CE STM32L462RE STM32L462VE

50/210 DS11913 Rev 5

3.26 Inter-integrated circuit interface (I2C)

The device embeds four I2C. Refer to Table 11 for the features implementation.

The I2C bus interface handles communications between the microcontroller and the serial

I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

•I2C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

•System Management Bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (Packet Error Checking) generation and verification with ACK

control

– Address resolution protocol (ARP) support

– SMBus alert

•Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility

•Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent from the PCLK reprogramming. Refer to

Figure 4: Clock tree.

•Wakeup from Stop mode on address match

•Programmable analog and digital noise filters

•1-byte buffer with DMA capability

Table 11. I2C implementation

I2C features(1)

1. X: supported

I2C1 I2C2 I2C3 I2C4

Standard-mode (up to 100 kbit/s) X X X X

Fast-mode (up to 400 kbit/s) X X X X

Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X X

Programmable analog and digital noise filters X X X X

SMBus/PMBus hardware support X X X X

Independent clock X X X X

Wakeup from Stop 1 mode on address match X X X X

Wakeup from Stop 2 mode on address match - - X -

DS11913 Rev 5 51/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

3.27 Universal synchronous/asynchronous receiver transmitter

(USART)

The STM32L462xx devices have three embedded universal synchronous receiver

transmitters (USART1, USART2 and USART3) and one universal asynchronous receiver

transmitters (UART4).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and

have LIN Master/Slave capability. They provide hardware management of the CTS and RTS

signals, and RS485 Driver Enable, and are able to communicate at speeds of up to

10 Mbit/s.

USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and

SPI-like communication capability.

All USART have a clock domain independent from the CPU clock, allowing the USARTx

(x=1,2,3,4) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The

wake up events from Stop mode are programmable and can be:

•Start bit detection

•Any received data frame

•A specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 12. STM32L462xx USART/UART/LPUART features

USART modes/features(1)

1. X = supported.

USART1 USART2 USART3 UART4 LPUART1

Hardware flow control for modem X X X X X

Continuous communication using DMA X X X X X

Multiprocessor communication X X X X X

Synchronous mode X X X - -

Smartcard mode X X X - -

Single-wire half-duplex communication X X X X X

IrDA SIR ENDEC block X X X X -

LIN mode X X X X -

Dual clock domain XXXX X

Wakeup from Stop 0 / Stop 1 modes X X X X X

Wakeup from Stop 2 mode - - - - X

Receiver timeout interrupt X X X X -

Modbus communication X X X X -

Auto baud rate detection X (4 modes) -

Driver Enable X X X X X

LPUART/USART data length 7, 8 and 9 bits

Functional overview STM32L462CE STM32L462RE STM32L462VE

52/210 DS11913 Rev 5

3.28 Low-power universal asynchronous receiver transmitter

(LPUART)

The device embeds one Low-Power UART. The LPUART supports asynchronous serial

communication with minimum power consumption. It supports half duplex single wire

communication and modem operations (CTS/RTS). It allows multiprocessor

communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the

system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop

mode are programmable and can be:

•Start bit detection

•Any received data frame

•A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600

baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while

having an extremely low energy consumption. Higher speed clock can be used to reach

higher baudrates.

LPUART interface can be served by the DMA controller.

DS11913 Rev 5 53/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

3.29 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s

slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8

master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI

interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

3.30 Serial audio interfaces (SAI)

The device embeds 1 SAI. Refer to Tabl e 13: SAI implementation for the features

implementation. The SAI bus interface handles communications between the

microcontroller and the serial audio protocol.

The SAI peripheral supports:

•Two independent audio sub-blocks which can be transmitters or receivers with their

respective FIFO.

•8-word integrated FIFOs for each audio sub-block.

•Synchronous or asynchronous mode between the audio sub-blocks.

•Master or slave configuration independent for both audio sub-blocks.

•Clock generator for each audio block to target independent audio frequency sampling

when both audio sub-blocks are configured in master mode.

•Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.

•Peripheral with large configurability and flexibility permitting to target as example the

following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF

out.

•Up to 16 slots available with configurable size and with the possibility to select which

ones are active in the audio frame.

•Number of bits by frame may be configurable.

•Frame synchronization active level configurable (offset, bit length, level).

•First active bit position in the slot is configurable.

•LSB first or MSB first for data transfer.

•Mute mode.

•Stereo/Mono audio frame capability.

•Communication clock strobing edge configurable (SCK).

•Error flags with associated interrupts if enabled respectively.

– Overrun and underrun detection.

– Anticipated frame synchronization signal detection in slave mode.

– Late frame synchronization signal detection in slave mode.

– Codec not ready for the AC’97 mode in reception.

•Interruption sources when enabled:

–Errors.

– FIFO requests.

•DMA interface with 2 dedicated channels to handle access to the dedicated integrated

FIFO of each SAI audio sub-block.

Functional overview STM32L462CE STM32L462RE STM32L462VE

54/210 DS11913 Rev 5

3.31 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bitrate up to 1 Mbit/s. It

can receive and transmit standard frames with 11-bit identifiers as well as extended frames

with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

The CAN peripheral supports:

•Supports CAN protocol version 2.0 A, B Active

•Bit rates up to 1 Mbit/s

•Transmission

– Three transmit mailboxes

– Configurable transmit priority

•Reception

– Two receive FIFOs with three stages

– 14 Scalable filter banks

– Identifier list feature

– Configurable FIFO overrun

•Time-triggered communication option

– Disable automatic retransmission mode

– 16-bit free running timer

– Time Stamp sent in last two data bytes

•Management

– Maskable interrupts

– Software-efficient mailbox mapping at a unique address space

3.32 Secure digital input/output and MultiMediaCards Interface

(SDMMC)

The card host interface (SDMMC) provides an interface between the APB peripheral bus

and MultiMediaCards (MMCs), SD memory cards and SDIO cards.

Table 13. SAI implementation

SAI features Support(1)

1. X: supported

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X

Mute mode X

Stereo/Mono audio frame capability. X

16 slots X

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X

FIFO Size X (8 Word)

SPDIF X

DS11913 Rev 5 55/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

The SDMMC features include the following:

•Full compliance with MultiMediaCard System Specification Version 4.2. Card support

for three different databus modes: 1-bit (default), 4-bit and 8-bit

•Full compatibility with previous versions of MultiMediaCards (forward compatibility)

•Full compliance with SD Memory Card Specifications Version 2.0

•Full compliance with SD I/O Card Specification Version 2.0: card support for two

different databus modes: 1-bit (default) and 4-bit

•Data transfer up to 48 MHz for the 8 bit mode

•Data write and read with DMA capability

3.33 Universal serial bus (USB)

The STM32L462xx devices embed a full-speed USB device peripheral compliant with the

USB specification version 2.0. The internal USB PHY supports USB FS signaling,

embedded DP pull-up and also battery charging detection according to Battery Charging

Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function

interface with added support for USB 2.0 Link Power Management. It has software-

configurable endpoint setting with packet memory up-to 1 KB and suspend/resume support.

It requires a precise 48 MHz clock which can be generated from the internal main PLL (the

clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in

automatic trimming mode. The synchronization for this oscillator can be taken from the USB

data stream itself (SOF signalization) which allows crystal less operation.

3.34 Clock recovery system (CRS)

The STM32L462xx devices embed a special block which allows automatic trimming of the

internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device

operational range. This automatic trimming is based on the external synchronization signal,

which could be either derived from LSE oscillator, from an external signal on CRS_SYNC

pin or generated by user software. For faster lock-in during startup it is also possible to

combine automatic trimming with manual trimming action.

3.35 Quad SPI memory interface (QUADSPI)

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI

Flash memories. It can operate in any of the three following modes:

•Indirect mode: all the operations are performed using the QUADSPI registers

•Status polling mode: the external Flash memory status register is periodically read and

an interrupt can be generated in case of flag setting

•Memory-mapped mode: the external Flash is memory mapped and is seen by the

system as if it were an internal memory

Both throughput and capacity can be increased two-fold using dual-flash mode, where two

Quad SPI flash memories are accessed simultaneously.

Functional overview STM32L462CE STM32L462RE STM32L462VE

56/210 DS11913 Rev 5

The Quad SPI interface supports:

•Three functional modes: indirect, status-polling, and memory-mapped

•Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two

flash memories in parallel.

•SDR and DDR support

•Fully programmable opcode for both indirect and memory mapped mode

•Fully programmable frame format for both indirect and memory mapped mode

•Each of the five following phases can be configured independently (enable, length,

single/dual/quad communication)

– Instruction phase

– Address phase

– Alternate bytes phase

– Dummy cycles phase

– Data phase

•Integrated FIFO for reception and transmission

•8, 16, and 32-bit data accesses are allowed

•DMA channel for indirect mode operations

•Programmable masking for external flash flag management

•Timeout management

•Interrupt generation on FIFO threshold, timeout, status match, operation complete, and

access error

DS11913 Rev 5 57/210

STM32L462CE STM32L462RE STM32L462VE Functional overview

3.36 Development support

3.36.1 Serial wire JTAG debug port (SWJ-DP)

The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins

can be reused as GPIO with alternate function): the JTAG TMS and TCK pins are shared

with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to

switch between JTAG-DP and SW-DP.

3.36.2 Embedded Trace Macrocell™

The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and

data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32L462xx through a small number of ETM pins to an external hardware trace port

analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then

formatted for display on the host computer that runs the debugger software. TPA hardware

is commercially available from common development tool vendors.

The Embedded Trace Macrocell™ operates with third party debugger software tools.

ps2 I ‘ m I 2 m I 3 >25 I 4 m I 5 van I 6 m: I 7 P0403032 w I a Pc‘5rosc32 out I g vss I «J van I u PHuosc w I ‘2 PHvosc out I ‘3 LQFP‘IOO was: I m Pco I ‘5 PCI I m Pcz I w m I us VSSA I m mg; I 20 man I 21 vum I 22 no I 23 pm I 24 w I 25

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

58/210 DS11913 Rev 5

4 Pinouts and pin description

Figure 6. STM32L462Vx LQFP100 pinout(1)

1. The above figure shows the package top view.

MSv40963V2

LQFP100

VSS

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0

PA1

PA2

PC15-OSC32_OUT

VDD

PE5

VBAT

PC14-OSC32_IN

PE2

PE3

PE4

PE6

PC13

100

PA3

VSS

PA5

PC4

PB2

VDD

PA4

PC5

PE8

PE11

PA6

PA7

PE9

PE12

PE15

PB0

PB1

PE13

PB10

VSS

PE7

PE10

PE14

PB11

VDD

PC9

PC7

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

PA8

PC8

PA13

PA11

PA9

VDD

VSS

VDDUSB

PA12

PA10

VDD

VSS

PB9

PB7

PB3

PE1

PE0

PB6

PD6

PD3

PB8

PH3-BOOT0

PD5

PD2

PC12

PB5

PB4

PD1

PC11

PA15

PD7

PD4

PD0

PC10

PA14

van I ‘ PC‘S I 2 PCM’OSCSQ w I 3 Pcwoscaz out I 4 we osc w I 5 PH‘rOSC out I s ”C“ ' E LQFP64

DS11913 Rev 5 59/210

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

Figure 7. STM32L462Vx UFBGA100 ballout(1)

1. The above figure shows the package top view.

Figure 8. STM32L462Rx LQFP64 pinout(1)

1. The above figure shows the package top view.

MSv40961V2

PE3 PE1 PB8 PH3-BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12

123456789101112

PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11

PC13 PE5 PE0 VDD PB5 PD2 PD0 PC11 VDDUSB PA10

PC14-

OSC32_IN PE6 VSS PA9 PA 8 PC9

PC15-

OSC32_OUT VBAT VSS PC8 PC7 PC6

PH0-OSC_IN VSS VSS VSS

PH1-

OSC_OUT VDD VDD VDD

PC0 NRST VDD PD15 PD14 PD13

VSSA PC1 PC2 PD12 PD11 PD10

VREF- PC3 PA2 PA5 PC4 PD9 PD8 PB15 PB14 PB13

VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12

VDDA PA1 PA4 PA7 PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15

UFBGA100

MSv40957V2

LQFP64

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

PC13

PA3

VSS

PA5

PC4

PB2

VDD

PA4

PC5

PB11

PA6

PA7

VSS

PB0

PB1

PB10

VDD

VDDUSB

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VSS

VDD

VSS

PH3-BOOT0

PB5

PC12

PB9

PB8

PB4

PC10

PB7

PB6

PA15

PB3

PD2

PC11

PA14

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

60/210 DS11913 Rev 5

Figure 9. STM32L462Rx UFBGA64 ballout(1)

1. The above figure shows the package top view.

Figure 10. STM32L462Rx WLCSP64 pinout(1)

1. The above figure shows the package top view.

MSv40959V2

PC14-

OSC32_IN PC13 PB9 PB4 PB3 PA15 PA14 PA13

12345678

PC15-

OSC32_OUT VBAT PB8 PH3-BOOT0 PD2 PC11 PC10 PA12

PH0-OSC_IN VSS PB7 PB5 PC12 PA11

PH1-

OSC_OUT VDD PB6

NRST PC1 PC0

VSSA/VREF- PC2

PC3 PA0

VDDA/VREF+ PA1 PA4

PA3

PA2

PC4

PB1

PB0

VDDUSB

VSS

PA7

PA6

PA5

VDD

VSS

PB11

PB10

PB15

PC7

PA8

PC5

PB2

PC6

VDD

VSS

PA10 PA9

PB12

PB13

PB14

PC8

PC9

MSv40955V2

VDDUSB PA15 PC12 PB4 PB7 PB8 VSS VDD

12345678

VSS VDD PC11 PB3 PB6 PH3-BOOT0 VBAT PC13

PA10 PA13 PA14 PD2 PB5 PC14-

OSC32_IN

PA9 PA11 PA12

PC7 PC9 PA8

PB15 PC6

PB14 PB13

VDD VSS PB11

PB12

PC8

PB0

PC5

PA5

PA7 PC3

PB10

PB2

PB1

PC4

PC10

VDD

PA2

VDDA/VREF+

PC1

NRST

PA6

PA4

PA3

PA0

PC2

PB9 PC15-

OSC32_OUT

PA1

VSSA/VREF-

PC0

PH1-

OSC_OUT

PH0-OSC_IN

VBAT I ‘ Pm: I 2 PCM’OSCE)? w l 3 PCIEVOSCSZ out I 4 we use w I 5 PHIVOSC out I s anr I 7 LQFP48

DS11913 Rev 5 61/210

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

Figure 11. STM32L462Cx LQFP48 pinout(1)

1. The above figure shows the package top view.

Figure 12. STM32L462Cx UFQFPN48 pinout(1)

1. The above figure shows the package top view.

MSv36897V3

LQFP48

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

PA3

PA4

PA7

PB2

VDD

PA5

PA6

PB10

PB0

PB1

PB11

VSS

VDDUSB

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PH3-BOOT0

PB5

PA14

PB9

PB8

PB4

PB7

PB6

PB3

PA15

MSv40953V2

UFQFPN48

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

PA3

PA4

PA7

PB2

VDD

PA5

PA6

PB10

PB0

PB1

PB11

VSS

VDDUSB

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PH3-BOOT0

PB5

PA14

PB9

PB8

PB4

PB7

PB6

PB3

PA15

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

62/210 DS11913 Rev 5

Table 14. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after

reset is the same as the actual pin name

Pin type

S Supply pin

I Input only pin

I/O Input / output pin

I/O structure

FT 5 V tolerant I/O

TT 3.6 V tolerant I/O

RST Bidirectional reset pin with embedded weak pull-up resistor

Option for TT or FT I/Os

_f (1) I/O, Fm+ capable

_u (2) I/O, with USB function supplied by VDDUSB

_a (3) I/O, with Analog switch function supplied by VDDA

Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

functions

Alternate

functions Functions selected through GPIOx_AFR registers

Additional

functions Functions directly selected/enabled through peripheral registers

1. The related I/O structures in Table 15 are: FT_f, FT_fa.

2. The related I/O structures in Table 15 are: FT_u, FT_fu.

3. The related I/O structures in Table 15 are: FT_a, FT_fa, TT_a.

Table 15. STM32L462xx pin definitions

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

LQFP48, UFQFPN48

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional functions

---- 1B2 PE2 I/O FT -

TRACECK, TIM3_ETR,

TSC_G7_IO1,

SAI1_MCLK_A,

EVENTOUT

---- 2A1 PE3 I/O FT -

TRACED0, TIM3_CH1,

TSC_G7_IO2, SAI1_SD_B,

EVENTOUT

DS11913 Rev 5 63/210

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

---- 3B1 PE4 I/O FT -

TRACED1, TIM3_CH2,

DFSDM1_DATIN3,

TSC_G7_IO3, SAI1_FS_A,

EVENTOUT

---- 4C2 PE5 I/O FT -

TRACED2, TIM3_CH3,

DFSDM1_CKIN3,

TSC_G7_IO4,

SAI1_SCK_A, EVENTOUT

---- 5D2 PE6 I/O FT - TRACED3, TIM3_CH4,

SAI1_SD_A, EVENTOUT RTC_TAMP3, WKUP3

1B71B2 6 E2 VBAT S - - - -

2B82A2 7 C1 PC13 I/O FT (1)

(2) EVENTOUT RTC_TAMP1, RTC_TS,

RTC_OUT, WKUP2

3C83A1 8 D1

PC14-

OSC32_

(PC14)

I/O FT (1)

(2) EVENTOUT OSC32_IN

4C74B1 9 E1

PC15-

OSC32_

OUT

(PC15)

I/O FT (1)

(2) EVENTOUT OSC32_OUT

----10F2 VSS S - - - -

----11G2 VDD S - - - -

5D85C112 F1

PH0-

OSC_IN

(PH0)

I/O FT - EVENTOUT OSC_IN

6E86D113 G1

PH1-

OSC_

OUT

(PH1)

I/O FT - EVENTOUT OSC_OUT

7 F8 7 E1 14 H2 NRST I/O RST - - -

- D7 8 E3 15 H1 PC0 I/O FT_fa -

LPTIM1_IN1, I2C4_SCL,

I2C3_SCL, LPUART1_RX,

LPTIM2_IN1, EVENTOUT

ADC1_IN1

- D5 9 E2 16 J2 PC1 I/O FT_fa -

TRACED0, LPTIM1_OUT,

I2C4_SDA, I2C3_SDA,

LPUART1_TX, EVENTOUT

ADC1_IN2

Table 15. STM32L462xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

LQFP48, UFQFPN48

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional functions

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

64/210 DS11913 Rev 5

-D610F217 J3 PC2 I/O FT_a -

LPTIM1_IN2, SPI2_MISO,

DFSDM1_CKOUT,

EVENTOUT

ADC1_IN3

-E711G118 K2 PC3 I/OFT_a-

LPTIM1_ETR, SPI2_MOSI,

SAI1_SD_A, LPTIM2_ETR,

EVENTOUT

ADC1_IN4

----19J1 VSSA S - - - -

----20K1 VREF- S - - - -

8G812F1 - - VSSA/

VREF- S-- - -

----21L1VREF+ S - - - VREFBUF_OUT

----22M1 VDDA S - - - -

9F713H1 - - VDDA/

VREF+ S-- - -

10 H8 14 G2 23 L2 PA0 I/O FT_a -

TIM2_CH1, USART2_CTS,

UART4_TX, COMP1_OUT,

SAI1_EXTCLK, TIM2_ETR,

EVENTOUT

OPAMP1_VINP,

COMP1_INM,

ADC1_IN5, RTC_TAMP2,

WKUP1

11 E6 15 H2 24 M2 PA1 I/O FT_a -

TIM2_CH2, I2C1_SMBA,

SPI1_SCK,

USART2_RTS_DE,

UART4_RX, TIM15_CH1N,

EVENTOUT

OPAMP1_VINM,

COMP1_INP, ADC1_IN6

12 G7 16 F3 25 K3 PA2 I/O FT_a -

TIM2_CH3, USART2_TX,

LPUART1_TX,

QUADSPI_BK1_NCS,

COMP2_OUT, TIM15_CH1,

EVENTOUT

COMP2_INM,

ADC1_IN7,

WKUP4,LSCO

13 F6 17 G3 26 L3 PA3 I/O TT_a -

TIM2_CH4, USART2_RX,

LPUART1_RX,

QUADSPI_CLK,

SAI1_MCLK_A,

TIM15_CH2, EVENTOUT

OPAMP1_VOUT,

COMP2_INP, ADC1_IN8

- - 18 C2 27 E3 VSS S - - - -

-H719D228 H3 VDD S - - - -

14 G6 20 H3 29 M3 PA4 I/O TT_a -

SPI1_NSS, SPI3_NSS,

USART2_CK, SAI1_FS_B,

LPTIM2_OUT, EVENTOUT

COMP1_INM,

COMP2_INM,

ADC1_IN9, DAC1_OUT1

Table 15. STM32L462xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

LQFP48, UFQFPN48

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional functions

DS11913 Rev 5 65/210

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

15 F5 21 F4 30 K4 PA5 I/O TT_a -

TIM2_CH1, TIM2_ETR,

SPI1_SCK,

DFSDM1_CKOUT,

LPTIM2_ETR, EVENTOUT

COMP1_INM,

COMP2_INM,

ADC1_IN10

16 H6 22 G4 31 L4 PA6 I/O FT_a -

TIM1_BKIN, TIM3_CH1,

SPI1_MISO, COMP1_OUT,

USART3_CTS,

LPUART1_CTS,

QUADSPI_BK1_IO3,

TIM1_BKIN_COMP2,

TIM16_CH1, EVENTOUT

ADC1_IN11

17 E5 23 H4 32 M4 PA7 I/O FT_fa -

TIM1_CH1N, TIM3_CH2,

I2C3_SCL, SPI1_MOSI,

DFSDM1_DATIN0,

QUADSPI_BK1_IO2,

COMP2_OUT, EVENTOUT

ADC1_IN12

- E4 24 H5 33 K5 PC4 I/O FT_a - USART3_TX, EVENTOUT COMP1_INM,

ADC1_IN13

- G5 25 H6 34 L5 PC5 I/O FT_a - USART3_RX, EVENTOUT COMP1_INP,

ADC1_IN14, WKUP5

18 H5 26 F5 35 M5 PB0 I/O FT_a -

TIM1_CH2N, TIM3_CH3,

SPI1_NSS,

DFSDM1_CKIN0,

USART3_CK,

QUADSPI_BK1_IO1,

COMP1_OUT,

SAI1_EXTCLK,

EVENTOUT

ADC1_IN15

19 F4 27 G5 36 M6 PB1 I/O FT_a -

TIM1_CH3N, TIM3_CH4,

DFSDM1_DATIN0,

USART3_RTS_DE,

LPUART1_RTS_DE,

QUADSPI_BK1_IO0,

LPTIM2_IN1, EVENTOUT

COMP1_INM,

ADC1_IN16

20 G4 28 G6 37 L6 PB2 I/O FT_a -

RTC_OUT, LPTIM1_OUT,

I2C3_SMBA,

DFSDM1_CKIN0,

EVENTOUT

COMP1_INP

----38M7 PE7 I/O FT -

TIM1_ETR,

DFSDM1_DATIN2,

SAI1_SD_B, EVENTOUT

Table 15. STM32L462xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

LQFP48, UFQFPN48

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional functions

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

66/210 DS11913 Rev 5

----39L7 PE8 I/O FT -

TIM1_CH1N,

DFSDM1_CKIN2,

SAI1_SCK_B, EVENTOUT

----40M8 PE9 I/O FT -

TIM1_CH1,

DFSDM1_CKOUT,

SAI1_FS_B, EVENTOUT

----41L8 PE10 I/O FT -

TIM1_CH2N, TSC_G5_IO1,

QUADSPI_CLK,

SAI1_MCLK_B,

EVENTOUT

----42M9 PE11 I/O FT -

TIM1_CH2, TSC_G5_IO2,

QUADSPI_BK1_NCS,

EVENTOUT

----43L9 PE12 I/O FT -

TIM1_CH3N, SPI1_NSS,

TSC_G5_IO3,

QUADSPI_BK1_IO0,

EVENTOUT

----44M10PE13 I/O FT -

TIM1_CH3, SPI1_SCK,

TSC_G5_IO4,

QUADSPI_BK1_IO1,

EVENTOUT

----45M11PE14 I/O FT -

TIM1_CH4, TIM1_BKIN2,

TIM1_BKIN2_COMP2,

SPI1_MISO,

QUADSPI_BK1_IO2,

EVENTOUT

----46M12PE15 I/O FT -

TIM1_BKIN,

TIM1_BKIN_COMP1,

SPI1_MOSI,

QUADSPI_BK1_IO3,

EVENTOUT

21 H4 29 G7 47 L10 PB10 I/O FT_f -

TIM2_CH3, I2C4_SCL,

I2C2_SCL, SPI2_SCK,

USART3_TX,

LPUART1_RX,

TSC_SYNC,

QUADSPI_CLK,

COMP1_OUT,

SAI1_SCK_A, EVENTOUT

Table 15. STM32L462xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

LQFP48, UFQFPN48

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional functions

DS11913 Rev 5 67/210

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

22 H3 30 H7 48 L11 PB11 I/O FT_f -

TIM2_CH4, I2C4_SDA,

I2C2_SDA, USART3_RX,

LPUART1_TX,

QUADSPI_BK1_NCS,

COMP2_OUT, EVENTOUT

23 H2 31 D6 49 F12 VSS S - - - -

24 H1 32 E6 50 G12 VDD S - - - -

25 G3 33 H8 51 L12 PB12 I/O FT -

TIM1_BKIN,

TIM1_BKIN_COMP2,

I2C2_SMBA, SPI2_NSS,

DFSDM1_DATIN1,

USART3_CK,

LPUART1_RTS_DE,

TSC_G1_IO1, CAN1_RX,

SAI1_FS_A, TIM15_BKIN,

EVENTOUT

26 G2 34 G8 52 K12 PB13 I/O FT_f -

TIM1_CH1N, I2C2_SCL,

SPI2_SCK,

DFSDM1_CKIN1,

USART3_CTS,

LPUART1_CTS,

TSC_G1_IO2, CAN1_TX,

SAI1_SCK_A,

TIM15_CH1N, EVENTOUT

27 G1 35 F8 53 K11 PB14 I/O FT_f -

TIM1_CH2N, I2C2_SDA,

SPI2_MISO,

DFSDM1_DATIN2,

USART3_RTS_DE,

TSC_G1_IO3,

SAI1_MCLK_A,

TIM15_CH1, EVENTOUT

28 F1 36 F7 54 K10 PB15 I/O FT -

RTC_REFIN, TIM1_CH3N,

SPI2_MOSI,

DFSDM1_CKIN2,

TSC_G1_IO4, SAI1_SD_A,

TIM15_CH2, EVENTOUT

----55K9 PD8 I/O FT -USART3_TX, EVENTOUT -

----56K8 PD9 I/O FT -USART3_RX, EVENTOUT -

----57J12 PD10 I/O FT - USART3_CK,

TSC_G6_IO1, EVENTOUT -

Table 15. STM32L462xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

LQFP48, UFQFPN48

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional functions

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

68/210 DS11913 Rev 5

----58J11 PD11 I/O FT -

I2C4_SMBA,

USART3_CTS,

TSC_G6_IO2,

LPTIM2_ETR, EVENTOUT

----59J10 PD12 I/O FT -

I2C4_SCL,

USART3_RTS_DE,

TSC_G6_IO3,

LPTIM2_IN1, EVENTOUT

----60H12PD13 I/O FT -

I2C4_SDA, TSC_G6_IO4,

LPTIM2_OUT, EVENTOUT -

----61H11 PD14 I/O FT - EVENTOUT -

----62H10PD15 I/O FT - EVENTOUT -

-F237F663E12 PC6 I/O FT -

TIM3_CH1,

DFSDM1_CKIN3,

TSC_G4_IO1,

SDMMC1_D6, EVENTOUT

-E138E764E11 PC7 I/O FT -

TIM3_CH2,

DFSDM1_DATIN3,

TSC_G4_IO2,

SDMMC1_D7, EVENTOUT

-F339E865E10 PC8 I/O FT - TIM3_CH3, TSC_G4_IO3,

SDMMC1_D0, EVENTOUT -

-E240D866D12 PC9 I/O FT -

TIM3_CH4, TSC_G4_IO4,

USBNOE, SDMMC1_D1,

EVENTOUT

29 E3 41 D7 67 D11 PA8 I/O FT -

MCO, TIM1_CH1,

DFSDM1_CKIN1,

USART1_CK,

SAI1_SCK_A,

LPTIM2_OUT, EVENTOUT

30 D1 42 C7 68 D10 PA9 I/O FT_f -

TIM1_CH2, I2C1_SCL,

DFSDM1_DATIN1,

USART1_TX, SAI1_FS_A,

TIM15_BKIN, EVENTOUT

31 C1 43 C6 69 C12 PA10 I/O FT_f -

TIM1_CH3, I2C1_SDA,

USART1_RX,

USBCRS_SYNC,

SAI1_SD_A, EVENTOUT

Table 15. STM32L462xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

LQFP48, UFQFPN48

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional functions

DS11913 Rev 5 69/210

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

32 D2 44 C8 70 B12 PA11 I/O FT_u -

TIM1_CH4, TIM1_BKIN2,

SPI1_MISO, COMP1_OUT,

USART1_CTS, CAN1_RX,

USBDM,

TIM1_BKIN2_COMP1,

EVENTOUT

33 D3 45 B8 71 A12 PA12 I/O FT_fu -

TIM1_ETR, SPI1_MOSI,

USART1_RTS_DE,

CAN1_TX, USBDP,

EVENTOUT

34 C2 46 A8 72 A11

PA13

(JTMS/

SWDIO)

I/O FT (3) JTMS/SWDAT, IR_OUT,

USBNOE, SAI1_SD_B,

EVENTOUT

35 B1 47 D5 - - VSS S - - - -

36 A1 48 E5 73 C11 VDDUSB S - - - -

----74F11 VSS S - - - -

-B2- - 75G11 VDD S - - - -

37 C3 49 A7 76 A10

PA14

(JTCK/

SWCLK)

I/O FT (3)

JTCK/SWCLK,

LPTIM1_OUT, I2C1_SMBA,

I2C4_SMBA, SAI1_FS_B,

EVENTOUT

38 A2 50 A6 77 A9 PA15

(JTDI) I/O FT (3)

JTDI, TIM2_CH1,

TIM2_ETR, USART2_RX,

SPI1_NSS, SPI3_NSS,

USART3_RTS_DE,

UART4_RTS_DE,

TSC_G3_IO1, EVENTOUT

-D451B778B11 PC10 I/O FT -

TRACED1, SPI3_SCK,

USART3_TX, UART4_TX,

TSC_G3_IO2,

SDMMC1_D2, EVENTOUT

-B352B679C10 PC11 I/O FT -

SPI3_MISO, USART3_RX,

UART4_RX, TSC_G3_IO3,

SDMMC1_D3, EVENTOUT

-A353C580B10 PC12 I/O FT -

TRACED3, SPI3_MOSI,

USART3_CK,

TSC_G3_IO4,

SDMMC1_CK, EVENTOUT

Table 15. STM32L462xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

LQFP48, UFQFPN48

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional functions

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

70/210 DS11913 Rev 5

----81C9 PD0 I/O FT - SPI2_NSS, CAN1_RX,

EVENTOUT -

----82B9 PD1 I/O FT - SPI2_SCK, CAN1_TX,

EVENTOUT -

-C454B583 C8 PD2 I/O FT -

TRACED2, TIM3_ETR,

USART3_RTS_DE,

TSC_SYNC,

SDMMC1_CMD,

EVENTOUT

----84B8 PD3 I/O FT -

SPI2_MISO,

DFSDM1_DATIN0,

USART2_CTS,

QUADSPI_BK2_NCS,

EVENTOUT

----85B7 PD4 I/O FT -

SPI2_MOSI,

DFSDM1_CKIN0,

USART2_RTS_DE,

QUADSPI_BK2_IO0,

EVENTOUT

----86A6 PD5 I/O FT -

USART2_TX,

QUADSPI_BK2_IO1,

EVENTOUT

----87B6 PD6 I/O FT -

DFSDM1_DATIN1,

USART2_RX,

QUADSPI_BK2_IO2,

SAI1_SD_A, EVENTOUT

----88A5 PD7 I/O FT -

DFSDM1_CKIN1,

USART2_CK,

QUADSPI_BK2_IO3,

EVENTOUT

39 B4 55 A5 89 A8

PB3

(JTDO/

TRACE

SWO)

I/O FT_a (3)

JTDO/TRACESWO,

TIM2_CH2, SPI1_SCK,

SPI3_SCK,

USART1_RTS_DE,

SAI1_SCK_B, EVENTOUT

COMP2_INM

Table 15. STM32L462xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

LQFP48, UFQFPN48

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional functions

DS11913 Rev 5 71/210

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

40 A4 56 A4 90 A7 PB4

(NJTRST) I/O FT_fa (3)

NJTRST, TIM3_CH1,

I2C3_SDA, SPI1_MISO,

SPI3_MISO,

USART1_CTS,

TSC_G2_IO1,

SAI1_MCLK_B,

EVENTOUT

COMP2_INP

41 C5 57 C4 91 C5 PB5 I/O FT -

LPTIM1_IN1, TIM3_CH2,

CAN1_RX, I2C1_SMBA,

SPI1_MOSI, SPI3_MOSI,

USART1_CK,

TSC_G2_IO2,

COMP2_OUT, SAI1_SD_B,

TIM16_BKIN, EVENTOUT

42 B5 58 D3 92 B5 PB6 I/O FT_fa -

LPTIM1_ETR, I2C1_SCL,

I2C4_SCL, USART1_TX,

CAN1_TX, TSC_G2_IO3,

SAI1_FS_B, TIM16_CH1N,

EVENTOUT

COMP2_INP

43 A5 59 C3 93 B4 PB7 I/O FT_fa -

LPTIM1_IN2, I2C1_SDA,

I2C4_SDA, USART1_RX,

UART4_CTS,

TSC_G2_IO4, EVENTOUT

COMP2_INM, PVD_IN

44 B6 60 B4 94 A4

PH3-

BOOT0

(BOOT0)

I/O - - EVENTOUT BOOT0

45 A6 61 B3 95 A3 PB8 I/O FT_f -

I2C1_SCL, CAN1_RX,

SDMMC1_D4,

SAI1_MCLK_A,

TIM16_CH1, EVENTOUT

46 C6 62 A3 96 B3 PB9 I/O FT_f -

IR_OUT, I2C1_SDA,

SPI2_NSS, CAN1_TX,

SDMMC1_D5, SAI1_FS_A,

EVENTOUT

----97C3 PE0 I/O FT -TIM16_CH1, EVENTOUT -

----98A2 PE1 I/O FT - EVENTOUT -

47 A7 63 D4 99 D3 VSS S - - - -

48 A8 64 E4 100 C4 VDD S - - - -

Table 15. STM32L462xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

LQFP48, UFQFPN48

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional functions

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

72/210 DS11913 Rev 5

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of

the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup

domain and RTC register descriptions in the RM0394 reference manual.

3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4

pins and the internal pull-down on PA14 pin are activated.

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

DS11913 Rev 5 73/210

Table 16. Alternate function AF0 to AF7(1)

Port

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SYS_AF TIM1/TIM2

LPTIM1

I2C4/TIM1/

TIM2/TIM3

I2C4/USART2/

CAN1/TIM1

I2C1/I2C2/

I2C3/I2C4 SPI1/SPI2/I2C4 SPI3/DFSDM/

COMP1

USART1/

USART2/

USART3

Port A

PA0-TIM2_CH1-----USART2_CTS

PA1 - TIM2_CH2 - - I2C1_SMBA SPI1_SCK - USART2_RTS_

PA2-TIM2_CH3-----USART2_TX

PA3-TIM2_CH4-----USART2_RX

PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK

PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK DFSDM1_

CKOUT -

PA6 - TIM1_BKIN TIM3_CH1 - - SPI1_MISO COMP1_OUT USART3_CTS

PA7 - TIM1_CH1N TIM3_CH2 - I2C3_SCL SPI1_MOSI DFSDM1_

DATIN0 -

PA8MCOTIM1_CH1----

DFSDM1_

CKIN1 USART1_CK

PA9 - TIM1_CH2 - - I2C1_SCL - DFSDM1_

DATIN1 USART1_TX

PA10 - TIM1_CH3 - - I2C1_SDA - - USART1_RX

PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO COMP1_OUT USART1_CTS

PA12 - TIM1_ETR - - - SPI1_MOSI - USART1_RTS_

PA13JTMS/SWDATIR_OUT------

PA14 JTCK/SWCLK LPTIM1_OUT - - I2C1_SMBA I2C4_SMBA - -

PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS SPI3_NSS USART3_RTS_

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

74/210 DS11913 Rev 5

Port B

PB0 - TIM1_CH2N TIM3_CH3 - - SPI1_NSS DFSDM1_

CKIN0 USART3_CK

PB1 - TIM1_CH3N TIM3_CH4 - - - DFSDM1_

DATIN0

USART3_RTS_

PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - DFSDM1_

CKIN0 -

PB3 JTDO/

TRACESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK USART1_RTS_

PB4 NJTRST - TIM3_CH1 - I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS

PB5 - LPTIM1_IN1 TIM3_CH2 CAN1_RX I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK

PB6 - LPTIM1_ETR - - I2C1_SCL I2C4_SCL - USART1_TX

PB7 - LPTIM1_IN2 - - I2C1_SDA I2C4_SDA - USART1_RX

PB8----I2C1_SCL---

PB9 - IR_OUT - - I2C1_SDA SPI2_NSS - -

PB10 - TIM2_CH3 - I2C4_SCL I2C2_SCL SPI2_SCK - USART3_TX

PB11 - TIM2_CH4 - I2C4_SDA I2C2_SDA - - USART3_RX

PB12 - TIM1_BKIN - TIM1_BKIN_C

OMP2 I2C2_SMBA SPI2_NSS DFSDM1_

DATIN1 USART3_CK

PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK DFSDM1_

CKIN1 USART3_CTS

PB14 - TIM1_CH2N - - I2C2_SDA SPI2_MISO DFSDM1_

DATIN2

USART3_RTS_

PB15 RTC_REFIN TIM1_CH3N - - - SPI2_MOSI DFSDM1_

CKIN2 -

Table 16. Alternate function AF0 to AF7(1) (continued)

Port

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SYS_AF TIM1/TIM2

LPTIM1

I2C4/TIM1/

TIM2/TIM3

I2C4/USART2/

CAN1/TIM1

I2C1/I2C2/

I2C3/I2C4 SPI1/SPI2/I2C4 SPI3/DFSDM/

COMP1

USART1/

USART2/

USART3

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

DS11913 Rev 5 75/210

Port C

PC0 - LPTIM1_IN1 I2C4_SCL - I2C3_SCL - - -

PC1 TRACED0 LPTIM1_OUT I2C4_SDA - I2C3_SDA - - -

PC2 - LPTIM1_IN2 - - - SPI2_MISO DFSDM1_

CKOUT -

PC3 - LPTIM1_ETR - - - SPI2_MOSI - -

PC4-------USART3_TX

PC5-------USART3_RX

PC6 - - TIM3_CH1 - - - DFSDM1_

CKIN3 -

PC7 - - TIM3_CH2 - - - DFSDM1_

DATIN3 -

PC8--TIM3_CH3-----

PC9--TIM3_CH4-----

PC10TRACED1-----SPI3_SCKUSART3_TX

PC11------SPI3_MISOUSART3_RX

PC12TRACED3-----SPI3_MOSIUSART3_CK

PC13--------

PC14--------

PC15--------

Table 16. Alternate function AF0 to AF7(1) (continued)

Port

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SYS_AF TIM1/TIM2

LPTIM1

I2C4/TIM1/

TIM2/TIM3

I2C4/USART2/

CAN1/TIM1

I2C1/I2C2/

I2C3/I2C4 SPI1/SPI2/I2C4 SPI3/DFSDM/

COMP1

USART1/

USART2/

USART3

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

76/210 DS11913 Rev 5

Port D

PD0 - - - - - SPI2_NSS - -

PD1 - - - - - SPI2_SCK - -

PD2 TRACED2 - TIM3_ETR - - - - USART3_RTS_

PD3 - - - - - SPI2_MISO DFSDM1_

DATIN0 USART2_CTS

PD4 - - - - - SPI2_MOSI DFSDM1_

CKIN0

USART2_RTS_

PD5-------USART2_TX

PD6------

DFSDM1_

DATIN1 USART2_RX

PD7------

DFSDM1_

CKIN1 USART2_CK

PD8-------USART3_TX

PD9-------USART3_RX

PD10-------USART3_CK

PD11 - - - - I2C4_SMBA - - USART3_CTS

PD12 - - - - I2C4_SCL - - USART3_RTS_

PD13----I2C4_SDA---

PD14--------

PD15--------

Table 16. Alternate function AF0 to AF7(1) (continued)

Port

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SYS_AF TIM1/TIM2

LPTIM1

I2C4/TIM1/

TIM2/TIM3

I2C4/USART2/

CAN1/TIM1

I2C1/I2C2/

I2C3/I2C4 SPI1/SPI2/I2C4 SPI3/DFSDM/

COMP1

USART1/

USART2/

USART3

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

DS11913 Rev 5 77/210

Port E

PE0--------

PE1--------

PE2 TRACECK - TIM3_ETR - - - - -

PE3 TRACED0 - TIM3_CH1 - - - - -

PE4 TRACED1 - TIM3_CH2 - - - DFSDM1_

DATIN3 -

PE5 TRACED2 - TIM3_CH3 - - - DFSDM1_

CKIN3 -

PE6 TRACED3 - TIM3_CH4 - - - - -

PE7-TIM1_ETR----

DFSDM1_

DATIN2 -

PE8-TIM1_CH1N----

DFSDM1_

CKIN2 -

PE9-TIM1_CH1----

DFSDM1_

CKOUT -

PE10-TIM1_CH2N------

PE11-TIM1_CH2------

PE12 - TIM1_CH3N - - - SPI1_NSS - -

PE13 - TIM1_CH3 - - - SPI1_SCK - -

PE14 - TIM1_CH4 TIM1_BKIN2 TIM1_BKIN2_

COMP2 - SPI1_MISO - -

PE15 - TIM1_BKIN - TIM1_BKIN_

COMP1 - SPI1_MOSI - -

Table 16. Alternate function AF0 to AF7(1) (continued)

Port

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SYS_AF TIM1/TIM2

LPTIM1

I2C4/TIM1/

TIM2/TIM3

I2C4/USART2/

CAN1/TIM1

I2C1/I2C2/

I2C3/I2C4 SPI1/SPI2/I2C4 SPI3/DFSDM/

COMP1

USART1/

USART2/

USART3

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

78/210 DS11913 Rev 5

Port H

PH0--------

PH1--------

PH3--------

1. Refer to Table 17 for AF8 to AF15.

Table 16. Alternate function AF0 to AF7(1) (continued)

Port

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SYS_AF TIM1/TIM2

LPTIM1

I2C4/TIM1/

TIM2/TIM3

I2C4/USART2/

CAN1/TIM1

I2C1/I2C2/

I2C3/I2C4 SPI1/SPI2/I2C4 SPI3/DFSDM/

COMP1

USART1/

USART2/

USART3

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

DS11913 Rev 5 79/210

Table 17. Alternate function AF8 to AF15(1)

Port

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

UART4/

LPUART1/

CAN1

CAN1/TSC CAN1/USB/

QUADSPI -

SDMMC1/

COMP1/

COMP2

SAI1 TIM2/TIM15/

TIM16/LPTIM2 EVENTOUT

Port A

PA0 UART4_TX - - - COMP1_OUT SAI1_EXTCLK TIM2_ETR EVENTOUT

PA1UART4_RX-----TIM15_CH1NEVENTOUT

PA2 LPUART1_TX - QUADSPI_

BK1_NCS - COMP2_OUT - TIM15_CH1 EVENTOUT

PA3 LPUART1_RX - QUADSPI_CLK - - SAI1_MCLK_A TIM15_CH2 EVENTOUT

PA4-----SAI1_FS_BLPTIM2_OUTEVENTOUT

PA5------LPTIM2_ETREVENTOUT

PA6 LPUART1_CTS - QUADSPI_

BK1_IO3 -TIM1_BKIN_

COMP2 - TIM16_CH1 EVENTOUT

PA7 - - QUADSPI_

BK1_IO2 - COMP2_OUT - - EVENTOUT

PA8-----SAI1_SCK_ALPTIM2_OUTEVENTOUT

PA9-----SAI1_FS_ATIM15_BKINEVENTOUT

PA10 - - USBCRS_

SYNC - - SAI1_SD_A - EVENTOUT

PA11 - CAN1_RX USBDM - TIM1_BKIN2_

COMP1 - - EVENTOUT

PA12 - CAN1_TX USBDP - - - - EVENTOUT

PA13 - - USBNOE - - SAI1_SD_B - EVENTOUT

PA14-----SAI1_FS_B-EVENTOUT

PA15 UART4_RTS_

DE TSC_G3_IO1 - - - - - EVENTOUT

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

80/210 DS11913 Rev 5

Port B

PB0 - - QUADSPI_

BK1_IO1 - COMP1_OUT SAI1_EXTCLK - EVENTOUT

PB1 LPUART1_RTS

_DE -QUADSPI_

BK1_IO0 - - - LPTIM2_IN1 EVENTOUT

PB2------ -EVENTOUT

PB3-----SAI1_SCK_B-EVENTOUT

PB4 - TSC_G2_IO1 - - - SAI1_MCLK_B - EVENTOUT

PB5 - TSC_G2_IO2 - - COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT

PB6 CAN1_TX TSC_G2_IO3 - - - SAI1_FS_B TIM16_CH1N EVENTOUT

PB7 UART4_CTS TSC_G2_IO4 - - - - - EVENTOUT

PB8 - CAN1_RX - - SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT

PB9 - CAN1_TX - - SDMMC1_D5 SAI1_FS_A - EVENTOUT

PB10 LPUART1_RX TSC_SYNC QUADSPI_CLK - COMP1_OUT SAI1_SCK_A - EVENTOUT

PB11 LPUART1_TX - QUADSPI_

BK1_NCS - COMP2_OUT - - EVENTOUT

PB12 LPUART1_RTS

_DE TSC_G1_IO1 CAN1_RX - - SAI1_FS_A TIM15_BKIN EVENTOUT

PB13 LPUART1_CTS TSC_G1_IO2 CAN1_TX - - SAI1_SCK_A TIM15_CH1N EVENTOUT

PB14 - TSC_G1_IO3 - - - SAI1_MCLK_A TIM15_CH1 EVENTOUT

PB15 - TSC_G1_IO4 - - - SAI1_SD_A TIM15_CH2 EVENTOUT

Table 17. Alternate function AF8 to AF15(1) (continued)

Port

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

UART4/

LPUART1/

CAN1

CAN1/TSC CAN1/USB/

QUADSPI -

SDMMC1/

COMP1/

COMP2

SAI1 TIM2/TIM15/

TIM16/LPTIM2 EVENTOUT

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

DS11913 Rev 5 81/210

Port C

PC0LPUART1_RX-----LPTIM2_IN1EVENTOUT

PC1LPUART1_TX----- -EVENTOUT

PC2------ -EVENTOUT

PC3-----SAI1_SD_ALPTIM2_ETREVENTOUT

PC4------ -EVENTOUT

PC5------ -EVENTOUT

PC6 - TSC_G4_IO1 - - SDMMC1_D6 - - EVENTOUT

PC7 - TSC_G4_IO2 - - SDMMC1_D7 - - EVENTOUT

PC8 - TSC_G4_IO3 - - SDMMC1_D0 - - EVENTOUT

PC9 - TSC_G4_IO4 USBNOE - SDMMC1_D1 - - EVENTOUT

PC10 UART4_TX TSC_G3_IO2 - - SDMMC1_D2 - - EVENTOUT

PC11 UART4_RX TSC_G3_IO3 - - SDMMC1_D3 - - EVENTOUT

PC12 - TSC_G3_IO4 - - SDMMC1_CK - - EVENTOUT

PC13------ -EVENTOUT

PC14------ -EVENTOUT

PC15------ -EVENTOUT

Table 17. Alternate function AF8 to AF15(1) (continued)

Port

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

UART4/

LPUART1/

CAN1

CAN1/TSC CAN1/USB/

QUADSPI -

SDMMC1/

COMP1/

COMP2

SAI1 TIM2/TIM15/

TIM16/LPTIM2 EVENTOUT

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

82/210 DS11913 Rev 5

Port D

PD0 - CAN1_RX - - - - - EVENTOUT

PD1 - CAN1_TX - - - - - EVENTOUT

PD2 - TSC_SYNC - - SDMMC1_

CMD - - EVENTOUT

PD3 - - QUADSPI_

BK2_NCS - - - - EVENTOUT

PD4 - - QUADSPI_

BK2_IO0 - - - - EVENTOUT

PD5 - - QUADSPI_

BK2_IO1 - - - - EVENTOUT

PD6 - - QUADSPI_

BK2_IO2 - - SAI1_SD_A - EVENTOUT

PD7 - - QUADSPI_

BK2_IO3 - - - - EVENTOUT

PD8------ -EVENTOUT

PD9------ -EVENTOUT

PD10 - TSC_G6_IO1 - - - - - EVENTOUT

PD11 - TSC_G6_IO2 - - - - LPTIM2_ETR EVENTOUT

PD12 - TSC_G6_IO3 - - - - LPTIM2_IN1 EVENTOUT

PD13 - TSC_G6_IO4 - - - - LPTIM2_OUT EVENTOUT

PD14------ -EVENTOUT

PD15------ -EVENTOUT

Table 17. Alternate function AF8 to AF15(1) (continued)

Port

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

UART4/

LPUART1/

CAN1

CAN1/TSC CAN1/USB/

QUADSPI -

SDMMC1/

COMP1/

COMP2

SAI1 TIM2/TIM15/

TIM16/LPTIM2 EVENTOUT

STM32L462CE STM32L462RE STM32L462VE Pinouts and pin description

DS11913 Rev 5 83/210

Port E

PE0------TIM16_CH1EVENTOUT

PE1------ -EVENTOUT

PE2 - TSC_G7_IO1 - - - SAI1_MCLK_A - EVENTOUT

PE3 - TSC_G7_IO2 - - - SAI1_SD_B - EVENTOUT

PE4 - TSC_G7_IO3 - - - SAI1_FS_A - EVENTOUT

PE5 - TSC_G7_IO4 - - - SAI1_SCK_A - EVENTOUT

PE6-----SAI1_SD_A-EVENTOUT

PE7-----SAI1_SD_B-EVENTOUT

PE8-----SAI1_SCK_B-EVENTOUT

PE9-----SAI1_FS_B-EVENTOUT

PE10 - TSC_G5_IO1 QUADSPI_CLK - - SAI1_MCLK_B - EVENTOUT

PE11 - TSC_G5_IO2 QUADSPI_

BK1_NCS - - - - EVENTOUT

PE12 - TSC_G5_IO3 QUADSPI_

BK1_IO0 - - - - EVENTOUT

PE13 - TSC_G5_IO4 QUADSPI_

BK1_IO1 - - - - EVENTOUT

PE14 - - QUADSPI_

BK1_IO2 - - - - EVENTOUT

PE15 - - QUADSPI_

BK1_IO3 - - - - EVENTOUT

Port H

PH0------ -EVENTOUT

PH1------ -EVENTOUT

PH3------ -EVENTOUT

Table 17. Alternate function AF8 to AF15(1) (continued)

Port

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

UART4/

LPUART1/

CAN1

CAN1/TSC CAN1/USB/

QUADSPI -

SDMMC1/

COMP1/

COMP2

SAI1 TIM2/TIM15/

TIM16/LPTIM2 EVENTOUT

Pinouts and pin description STM32L462CE STM32L462RE STM32L462VE

84/210 DS11913 Rev 5

1. Refer to Table 16 for AF0 to AF7.

DS11913 Rev 5 85/210

STM32L462CE STM32L462RE STM32L462VE Memory mapping

5 Memory mapping

Figure 13. STM32L462xx memory map

MSv40981V3

0xFFFF FFFF

0xE000 0000

0xC000 0000

0xA000 1000

0x8000 0000

0x6000 0000

0x4000 0000

0x2000 0000

0x0000 0000

Cortex™-M4

with FPU

Internal

Peripherals

SRAM1

CODE

OTP area

System memory

Flash memory

Flash, system memory

or SRAM, depending on

BOOT configuration

AHB2

AHB1

APB2

APB1

0x5006 0C00

0x4800 0000

0x4002 4400

0x4002 0000

0x4001 5800

0x4001 0000

0x4000 9800

0x4000 0000

0x1FFF FFFF

0x1FFF 0000

0x0808 0000

0x0800 0000

0x0008 0000

0x0000 0000

Reserved

0x1000 8000

0x1000 0000

SRAM2

QUADSPI

registers

Options Bytes

0x1FFF 7000

0x1FFF 7400

0x1FFF 7800

0x1FFF 7810

Reserved

QUADSPI registers

0xBFFF FFFF

0xA000 1400

0xA000 1000

Reserved

0x5FFF FFFF

0x9000 0000

QUADSPI Flash

bank

SRAM2

0x2002 0000

0xA000 0000

0x2002 7FFF

Memory mapping STM32L462CE STM32L462RE STM32L462VE

86/210 DS11913 Rev 5

Table 18. STM32L462xx memory map and peripheral register boundary addresses(1)

Bus Boundary address Size(bytes) Peripheral

AHB2

0x5006 0800 - 0x5006 0BFF 1 KB RNG

0x5006 0400 - 0x5006 07FF 1 KB Reserved

0x5006 0000 - 0x5006 03FF 1 KB AES

0x5004 0400 - 0x5005 FFFF 126 KB Reserved

0x5004 0000 - 0x5004 03FF 1 KB ADC

0x5000 0000 - 0x5003 FFFF 16 KB Reserved

0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved

0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH

0x4800 1400 - 0x4800 1BFF 2 KB Reserved

0x4800 1000 - 0x4800 13FF 1 KB GPIOE

0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD

0x4800 0800 - 0x4800 0BFF 1 KB GPIOC

0x4800 0400 - 0x4800 07FF 1 KB GPIOB

0x4800 0000 - 0x4800 03FF 1 KB GPIOA

-0x4002 4400 - 0x47FF FFFF ~127 MB Reserved

AHB1

0x4002 4000 - 0x4002 43FF 1 KB TSC

0x4002 3400 - 0x4002 3FFF 1 KB Reserved

0x4002 3000 - 0x4002 33FF 1 KB CRC

0x4002 2400 - 0x4002 2FFF 3 KB Reserved

0x4002 2000 - 0x4002 23FF 1 KB FLASH registers

0x4002 1400 - 0x4002 1FFF 3 KB Reserved

0x4002 1000 - 0x4002 13FF 1 KB RCC

0x4002 0800 - 0x4002 0FFF 2 KB Reserved

0x4002 0400 - 0x4002 07FF 1 KB DMA2

0x4002 0000 - 0x4002 03FF 1 KB DMA1

DS11913 Rev 5 87/210

STM32L462CE STM32L462RE STM32L462VE Memory mapping

APB2

0x4001 6400 - 0x4001 FFFF 39 KB Reserved

0x4001 6000 - 0x4000 63FF 1 KB DFSDM1

0x4001 5800 - 0x4001 5FFF 2 KB Reserved

0x4001 5400 - 0x4000 57FF 1 KB SAI1

0x4001 4800 - 0x4000 53FF 3 KB Reserved

0x4001 4400 - 0x4001 47FF 1 KB TIM16

0x4001 4000 - 0x4001 43FF 1 KB TIM15

0x4001 3C00 - 0x4001 3FFF 1 KB Reserved

0x4001 3800 - 0x4001 3BFF 1 KB USART1

0x4001 3400 - 0x4001 37FF 1 KB Reserved

APB2

0x4001 3000 - 0x4001 33FF 1 KB SPI1

0x4001 2C00 - 0x4001 2FFF 1 KB TIM1

0x4001 2800 - 0x4001 2BFF 1 KB SDMMC1

0x4001 2000 - 0x4001 27FF 2 KB Reserved

0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL

0x4001 0800- 0x4001 1BFF 5 KB Reserved

0x4001 0400 - 0x4001 07FF 1 KB EXTI

0x4001 0200 - 0x4001 03FF

1 KB

COMP

0x4001 0030 - 0x4001 01FF VREFBUF

0x4001 0000 - 0x4001 002F SYSCFG

Table 18. STM32L462xx memory map and peripheral register boundary addresses(1)

(continued)

Bus Boundary address Size(bytes) Peripheral

Memory mapping STM32L462CE STM32L462RE STM32L462VE

88/210 DS11913 Rev 5

APB1

0x4000 9800 - 0x4000 FFFF 26 KB Reserved

0x4000 9400 - 0x4000 97FF 1 KB LPTIM2

0x4000 8800 - 0x4000 93FF 3 KB Reserved

0x4000 8400 - 0x4000 87FF 1 KB I2C4

0x4000 8000 - 0x4000 83FF 1 KB LPUART1

0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1

0x4000 7800 - 0x4000 7BFF 1 KB OPAMP

0x4000 7400 - 0x4000 77FF 1 KB DAC1

0x4000 7000 - 0x4000 73FF 1 KB PWR

0x4000 6C00 - 0x4000 6FFF 1 KB USB SRAM

0x4000 6800 - 0x4000 6BFF 1 KB USB FS

0x4000 6400 - 0x4000 67FF 1 KB CAN1

0x4000 6000 - 0x4000 63FF 1 KB CRS

0x4000 5C00- 0x4000 5FFF 1 KB I2C3

0x4000 5800 - 0x4000 5BFF 1 KB I2C2

0x4000 5400 - 0x4000 57FF 1 KB I2C1

0x4000 5000 - 0x4000 53FF 1 KB Reserved

0x4000 4C00 - 0x4000 4FFF 1 KB UART4

0x4000 4800 - 0x4000 4BFF 1 KB USART3

0x4000 4400 - 0x4000 47FF 1 KB USART2

0x4000 4000 - 0x4000 43FF 1 KB Reserved

0x4000 3C00 - 0x4000 3FFF 1 KB SPI3

0x4000 3800 - 0x4000 3BFF 1 KB SPI2

0x4000 3400 - 0x4000 37FF 1 KB Reserved

0x4000 3000 - 0x4000 33FF 1 KB IWDG

0x4000 2C00 - 0x4000 2FFF 1 KB WWDG

APB1

0x4000 2800 - 0x4000 2BFF 1 KB RTC

0x4000 1400 - 0x4000 27FF 5 KB Reserved

0x4000 1000 - 0x4000 13FF 1 KB TIM6

0x4000 0800- 0x4000 0FFF 2 KB Reserved

0x4000 0400 - 0x4000 07FF 1 KB TIM3

0x4000 0000 - 0x4000 03FF 1 KB TIM2

1. The gray color is used for reserved boundary addresses.

Table 18. STM32L462xx memory map and peripheral register boundary addresses(1)

(continued)

Bus Boundary address Size(bytes) Peripheral

Figure 14. Pin loading conditions 5L Figure 15. Pin input voltage

DS11913 Rev 5 89/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

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6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean ±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They

are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean ±2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 14.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 15.

Figure 14. Pin loading conditions Figure 15. Pin input voltage

MS19210V1

MCU pin

C = 50 pF

MS19211V1

MCU pin

I I II EEG E3 I leI

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

90/210 DS11913 Rev 5

6.1.6 Power supply scheme

Figure 16. Power supply scheme

Caution: Each power supply pair (such as VDD/VSS, VDDA/VSSA) must be decoupled with filtering

ceramic capacitors as shown above. These capacitors must be placed as close as possible

to, or below, the appropriate pins on the underside of the PCB to ensure the good

functionality of the device.

MSv43827V2

VDD

Level shifter

logic

Kernel logic

(CPU, Digital

& Memories)

Backup circuitry

(LSE, RTC,

Backup registers)

OUT

Regulator

GPIOs

1.55 – 3.6 V

n x 100 nF

+1 x 4.7 μF

n x VSS

n x VDD

VBAT

VCORE

Power switch

VDDIO1

ADC/

DAC/

OPAMP/

COMPs/

VREFBUF

VREF+

VREF-

VDDA

10 nF

+1 μF

VDDA

VSSA

VREF

100 nF +1 μF

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STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

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6.1.7 Current consumption measurement

Figure 17. Current consumption measurement scheme

The IDD_ALL parameters given in Table 26 to Table 38 represent the total MCU consumption

including the current supplying VDD, VDDA, VDDUSB and VBAT.

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics,

Table 20: Current characteristics and Table 21: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of

the device at these conditions is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability. Exposure to maximum rating conditions for

extended periods may affect device reliability. Device mission profile (application conditions)

is compliant with JEDEC JESD47 qualification standard, extended mission profiles are

available on demand.

MS35002V2

IDD_USB

VDDUSB

IDD_VBAT

VBAT

IDD

VDD

IDDA

VDDA

Table 19. Voltage characteristics(1)

Symbol Ratings Min Max Unit

VDDX - VSS External main supply voltage (including

VDD, VDDA, VDDUSB, VBAT)-0.3 4.0 V

VIN(2)

Input voltage on FT_xxx pins VSS-0.3 min (VDD, VDDA, VDDUSB)

+ 4.0(3)(4)

Input voltage on TT_xx pins VSS-0.3 4.0

Input voltage on any other pins VSS-0.3 4.0

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|ΔVDDx|Variations between different VDDX power

pins of the same domain -50mV

|VSSx-VSS|Variations between all the different ground

pins(5) -50mV

1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power

supply, in the permitted range.

2. VIN maximum must always be respected. Refer to Table 20: Current characteristics for the maximum allowed injected

current values.

3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.

4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

5. Include VREF- pin.

Table 19. Voltage characteristics(1) (continued)

Symbol Ratings Min Max Unit

Table 20. Current characteristics

Symbol Ratings Max Unit

∑IVDD Total current into sum of all VDD power lines (source)(1) 140

∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 140

IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100

IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100

IIO(PIN)

Output current sunk by any I/O and control pin except FT_f 20

Output current sunk by any FT_f pin 20

Output current sourced by any I/O and control pin 20

∑IIO(PIN)

Total output current sunk by sum of all I/Os and control pins(2) 100

Total output current sourced by sum of all I/Os and control pins(2) 100

IINJ(PIN)(3)

Injected current on FT_xxx, TT_xx, RST and B pins, except PA4,

PA5 -5/+0(4)

Injected current on PA4, PA5 -5/0

∑|IINJ(PIN)|Total injected current (sum of all I/Os and control pins)(5) 25

1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power

supplies, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be

sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the

specified maximum value.

4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 19: Voltage

characteristics for the maximum allowed input voltage values.

5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative

injected currents (instantaneous values).

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Table 21. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150 °C

TJMaximum junction temperature 150 °C

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6.3 Operating conditions

6.3.1 General operating conditions

Table 22. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency - 0 80

MHzfPCLK1 Internal APB1 clock frequency - 0 80

fPCLK2 Internal APB2 clock frequency - 0 80

VDD Standard operating voltage - 1.71

(1) 3.6 V

VDDA Analog supply voltage

ADC or COMP used 1.62

3.6 V

DAC or OPAMP used 1.8

VREFBUF used 2.4

ADC, DAC, OPAMP, COMP,

VREFBUF not used 0

VBAT Backup operating voltage - 1.55 3.6 V

VDDUSB USB supply voltage USB used 3.0 3.6 V

USB not used 0 3.6

VIN I/O input voltage

TT_xx I/O -0.3 VDDIOx+0.3

All I/O except TT_xx -0.3

Min(Min(VDD, VDDA,

VDDUSB)+3.6 V,

5.5 V)(2)(3)

Power dissipation at

TA = 85 °C for suffix 6

LQFP100 - 357

UFBGA100 - 267

LQFP64 - 345

UFBGA64 - 308

WLCSP64 - 377

LQFP48 - 346

UFQFPN48 - 690

Power dissipation at

TA = 125 °C for suffix 3(4)

LQFP100 - 89

UFBGA100 - 67

LQFP64 - 86

UFBGA64 - 77

WLCSP64 - 94

LQFP48 - 86

UFQFPN48 - 172

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STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

6.3.2 Operating conditions at power-up / power-down

The parameters given in Table 23 are derived from tests performed under the ambient

temperature condition summarized in Table 22.

The requirements for power-up/down sequence specified in Section 3.9.1: Power supply

schemes must be respected.

6.3.3 Embedded reset and power control block characteristics

The parameters given in Table 24 are derived from tests performed under the ambient

temperature conditions summarized in Table 22: General operating conditions.

Ambient temperature for the

suffix 6 version

Maximum power dissipation –40 85

°C

Low-power dissipation(5) –40 105

Ambient temperature for the

suffix 3 version

Maximum power dissipation –40 125

Low-power dissipation(5) –40 130

TJ Junction temperature range Suffix 6 version –40 105 °C

Suffix 3 version –40 130

1. When RESET is released functionality is guaranteed down to VBOR0 Min.

2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.

Maximum I/O input voltage is the smallest value between Min(VDD, VDDA, VDDUSB)+3.6 V and 5.5V.

3. For operation with voltage higher than Min (VDD, VDDA, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must

be disabled.

4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.8: Thermal characteristics).

5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8:

Thermal characteristics).

Table 22. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

Table 23. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

tVDD

VDD rise time rate -0∞

µs/V

VDD fall time rate 10 ∞

tVDDA

VDDA rise time rate -0∞

µs/V

VDDA fall time rate 10 ∞

tVDDUSB

VDDUSB rise time rate -0∞

µs/V

VDDUSB fall time rate 10 ∞

Table 24. Embedded reset and power control block characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit

tRSTTEMPO(2) Reset temporization after

BOR0 is detected VDD rising - 250 400 μs

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96/210 DS11913 Rev 5

VBOR0(2) Brown-out reset threshold 0 Rising edge 1.62 1.66 1.7 V

Falling edge 1.6 1.64 1.69

VBOR1 Brown-out reset threshold 1 Rising edge 2.06 2.1 2.14 V

Falling edge 1.96 2 2.04

VBOR2 Brown-out reset threshold 2 Rising edge 2.26 2.31 2.35 V

Falling edge 2.16 2.20 2.24

VBOR3 Brown-out reset threshold 3 Rising edge 2.56 2.61 2.66 V

Falling edge 2.47 2.52 2.57

VBOR4 Brown-out reset threshold 4 Rising edge 2.85 2.90 2.95 V

Falling edge 2.76 2.81 2.86

VPVD0 Programmable voltage

detector threshold 0

Rising edge 2.1 2.15 2.19 V

Falling edge 2 2.05 2.1

VPVD1 PVD threshold 1 Rising edge 2.26 2.31 2.36 V

Falling edge 2.15 2.20 2.25

VPVD2 PVD threshold 2 Rising edge 2.41 2.46 2.51 V

Falling edge 2.31 2.36 2.41

VPVD3 PVD threshold 3 Rising edge 2.56 2.61 2.66 V

Falling edge 2.47 2.52 2.57

VPVD4 PVD threshold 4 Rising edge 2.69 2.74 2.79 V

Falling edge 2.59 2.64 2.69

VPVD5 PVD threshold 5 Rising edge 2.85 2.91 2.96 V

Falling edge 2.75 2.81 2.86

VPVD6 PVD threshold 6 Rising edge 2.92 2.98 3.04 V

Falling edge 2.84 2.90 2.96

Vhyst_BORH0 Hysteresis voltage of BORH0

Hysteresis in

continuous

mode

-20-

Hysteresis in

other mode -30-

Vhyst_BOR_PVD Hysteresis voltage of BORH

(except BORH0) and PVD --100-mV

IDD

(BOR_PVD)(2) BOR(3) (except BOR0) and

PVD consumption from VDD --1.11.6µA

VPVM1 VDDUSB peripheral voltage

monitoring - 1.18 1.22 1.26 V

VPVM3 VDDA peripheral voltage

monitoring

Rising edge 1.61 1.65 1.69 V

Falling edge 1.6 1.64 1.68

Table 24. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions(1) Min Typ Max Unit

DS11913 Rev 5 97/210

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182

VPVM4 VDDA peripheral voltage

monitoring

Rising edge 1.78 1.82 1.86 V

Falling edge 1.77 1.81 1.85

Vhyst_PVM3 PVM3 hysteresis - - 10 - mV

Vhyst_PVM4 PVM4 hysteresis - - 10 - mV

IDD (PVM1)

(2) PVM1 consumption from VDD --0.2-µA

IDD

(PVM3/PVM4)

(2)

PVM3 and PVM4

consumption from VDD --2-µA

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power

sleep modes.

2. Guaranteed by design.

3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply

current characteristics tables.

Table 24. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions(1) Min Typ Max Unit

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98/210 DS11913 Rev 5

6.3.4 Embedded voltage reference

The parameters given in Table 25 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 22: General operating

conditions.

Table 25. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage –40 °C < TA < +130 °C 1.182 1.212 1.232 V

tS_vrefint (1) ADC sampling time when

reading the internal reference

voltage

-4

(2) --µs

tstart_vrefint Start time of reference voltage

buffer when ADC is enable --812

(2) µs

IDD(VREFINTBUF)

VREFINT buffer consumption

from VDD when converted by

ADC

- - 12.5 20(2) µA

∆VREFINT

Internal reference voltage

spread over the temperature

range

VDD = 3 V - 5 7.5(2) mV

TCoeff Temperature coefficient –40°C < TA < +130°C - 30 50(2) ppm/°C

ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) ppm

VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V

VREFINT_DIV1 1/4 reference voltage

24 25 26

VREFINT

VREFINT_DIV2 1/2 reference voltage 49 50 51

VREFINT_DIV3 3/4 reference voltage 74 75 76

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

VREFINT

DS11913 Rev 5 99/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

Figure 18. VREFINT versus temperature

MSv40169V1

1.185

1.19

1.195

1.2

1.205

1.21

1.215

1.22

1.225

1.23

1.235

-40 -20 0 20 40 60 80 100 120

°C

Mean Min Max

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

100/210 DS11913 Rev 5

6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code.

The current consumption is measured as described in Figure 17: Current consumption

measurement scheme.

Typical and maximum current consumption

The MCU is placed under the following conditions:

•All I/O pins are in analog input mode

•All peripherals are disabled except when explicitly mentioned

•The Flash memory access time is adjusted with the minimum wait states number,

depending on the fHCLK frequency (refer to the table “Number of wait states according

to CPU clock (HCLK) frequency” available in the RM0394 reference manual).

•When the peripherals are enabled fPCLK = fHCLK

The parameters given in Table 26 to Table 39 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in Table 22: General

operating conditions.

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

DS11913 Rev 5 101/210

Table 26. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART enable (Cache ON Prefetch OFF)

Symbol Parameter

Conditions TYP MAX(1)

Unit

-Voltage

scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

IDD_ALL

(Run)

Supply

current in

Run mode

fHCLK = fHSE up to

48MHz included,

bypass mode

PLL ON above

48 MHz all

peripherals disable

Range 2

26 MHz 2.35 2.40 2.50 2.65 3.00 2.65 2.75 2.90 3.20 3.75

16 MHz 1.50 1.55 1.65 1.80 2.15 1.70 1.75 1.95 2.20 2.80

8 MHz 0.815 0.845 0.940 1.10 1.45 0.95 1.00 1.15 1.45 2.00

4 MHz 0.465 0.495 0.595 0.760 1.10 0.55 0.60 0.75 1.05 1.60

2 MHz 0.295 0.320 0.420 0.580 0.910 0.35 0.40 0.55 0.85 1.40

1 MHz 0.205 0.235 0.330 0.495 0.825 0.25 0.30 0.45 0.75 1.30

100 kHz 0.130 0.155 0.250 0.415 0.745 0.15 0.25 0.40 0.65 1.25

Range 1

80 MHz 8.45 8.50 8.65 8.90 9.25 9.45 9.50 9.75 10.10 10.75

72 MHz 7.65 7.70 7.85 8.05 8.45 8.50 8.60 8.80 9.15 9.85

64 MHz 6.80 6.85 7.00 7.20 7.60 7.60 7.70 7.90 8.25 8.90

48 MHz 5.10 5.15 5.25 5.45 5.85 5.70 5.80 6.00 6.35 7.00

32 MHz 3.45 3.50 3.60 3.80 4.20 3.85 3.95 4.15 4.50 5.15

24 MHz 2.60 2.65 2.80 2.95 3.35 2.95 3.05 3.20 3.55 4.20

16 MHz 1.80 1.85 1.95 2.15 2.50 2.00 2.10 2.30 2.60 3.25

IDD_ALL

(LPRun)

Supply

current in

Low-power

run mode

fHCLK = fMSI

all peripherals disable

2 MHz 225 260 365 550 900 275 335 470 770 1400

µA

1 MHz 130 160 270 450 800 170 225 375 670 1300

400 kHz 73.0 99.5 205 385 735 105 165 325 600 1250

100 kHz 38.0 71.0 175 355 705 70 140 315 565 1200

1. Guaranteed by characterization results, unless otherwise specified.

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

102/210 DS11913 Rev 5

Table 27. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART disable

Symbol Parameter

Conditions TYP MAX(1)

Unit

-Voltage

scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

IDD_ALL

(Run)

Supply

current in

Run mode

fHCLK = fHSE up to

48MHz included,

bypass mode

PLL ON above

48 MHz all

peripherals disable

Range 2

26 MHz 2.75 2.80 2.90 3.10 3.40 3.15 3.25 3.40 3.70 4.30

16 MHz 1.95 2.00 2.10 2.25 2.60 2.25 2.30 2.50 2.75 3.35

8 MHz 1.10 1.15 1.25 1.40 1.75 1.25 1.35 1.50 1.75 2.35

4 MHz 0.640 0.670 0.765 0.935 1.25 0.75 0.80 0.95 1.25 1.80

2 MHz 0.380 0.405 0.505 0.670 1.00 0.45 0.50 0.65 0.95 1.50

1 MHz 0.250 0.275 0.375 0.540 0.865 0.30 0.35 0.50 0.80 1.35

100 kHz 0.135 0.160 0.255 0.420 0.750 0.15 0.25 0.40 0.65 1.25

Range 1

80 MHz 8.85 8.90 9.05 9.30 9.70 10.0 10.5 10.5 11.0 11.5

72 MHz 8.00 8.05 8.20 8.40 8.85 9.05 9.15 9.35 9.70 10.5

64 MHz 7.90 7.95 8.10 8.35 8.75 8.95 9.10 9.35 9.70 10.5

48 MHz 6.60 6.65 6.80 7.05 7.45 7.55 7.65 7.90 8.30 9.00

32 MHz 4.75 4.80 4.95 5.15 5.55 5.40 5.50 5.75 6.10 6.80

24 MHz 3.60 3.65 3.80 4.00 4.35 4.10 4.20 4.40 4.75 5.40

16 MHz 2.60 2.65 2.75 2.95 3.35 3.00 3.05 3.25 3.60 4.25

IDD_ALL

(LPRun)

Supply

current in

Low-power

run

fHCLK = fMSI

all peripherals disable

2 MHz 340 360 470 650 1000 400 455 575 880 1550

µA

1 MHz 175 215 320 500 855 225 285 420 720 1350

400 kHz 89.5 120 225 405 760 130 185 340 620 1250

100 kHz 42.5 75.5 180 360 715 75 145 320 575 1200

1. Guaranteed by characterization results, unless otherwise specified.

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

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Table 28. Current consumption in Run and Low-power run modes, code with data processing

running from SRAM1

Symbol Parameter

Conditions TYP MAX(1)

Unit

-Voltage

scaling fHCLK 25 °C 55 °C 85 °C 105

°C

125

°C 25 °C 55 °C 85 °C 105

°C

125

°C

IDD_ALL

(Run)

Supply

current in

Run mode

fHCLK = fHSE up to

48MHz included,

bypass mode

PLL ON above

48 MHz all

peripherals disable

Range 2

26 MHz 2.40 2.40 2.55 2.70 3.05 2.70 2.75 2.90 3.20 3.80

16 MHz 1.50 1.55 1.65 1.80 2.15 1.70 1.80 1.95 2.25 2.80

8 MHz 0.820 0.850 0.950 1.10 1.45 0.95 1.00 1.15 1.45 2.00

4 MHz 0.470 0.500 0.600 0.765 1.10 0.55 0.60 0.75 1.05 1.60

2 MHz 0.295 0.325 0.420 0.585 0.915 0.35 0.40 0.55 0.85 1.40

1 MHz 0.210 0.235 0.330 0.495 0.825 0.25 0.30 0.45 0.75 1.30

100 kHz 0.130 0.155 0.250 0.415 0.750 0.15 0.25 0.35 0.65 1.25

Range 1

80 MHz 8.55 8.60 8.75 8.95 9.35 9.55 9.65 9.85 10.5 11.0

72 MHz 7.70 7.80 7.90 8.15 8.50 8.60 8.70 8.90 9.25 9.95

64 MHz 6.90 6.95 7.10 7.30 7.70 7.70 7.75 7.95 8.35 9.00

48 MHz 5.15 5.20 5.30 5.55 5.90 5.75 5.85 6.05 6.40 7.05

32 MHz 3.45 3.50 3.65 3.85 4.25 3.90 4.00 4.20 4.50 5.15

24 MHz 2.65 2.70 2.80 3.00 3.40 3.00 3.05 3.25 3.55 4.20

16 MHz 1.80 1.85 1.95 2.15 2.55 2.05 2.10 2.30 2.60 3.25

IDD_ALL

(LPRun)

Supply

current in

low-power

run mode

fHCLK = fMSI

all peripherals disable

FLASH in power-down

2 MHz 220 255 360 540 895 270 330 460 760 1400

µA

1 MHz 120 155 260 440 795 165 215 370 660 1300

400 kHz 60.0 92.0 195 375 730 100 160 330 585 1250

100 kHz 36.0 62.5 165 345 695 63.0 130 305 555 1200

1. Guaranteed by characterization results, unless otherwise specified.

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

104/210 DS11913 Rev 5

Table 29. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF)

Symbol Parameter

Conditions TYP

Unit

TYP

Unit

-Voltage

scaling Code 25 °C 25 °C

IDD_ALL

(Run)

Supply

current in

Run mode

fHCLK = fHSE up

to 48 MHz

included, bypass

mode PLL ON

above 48 MHz

all peripherals

disable

Range 2

fHCLK = 26 MHz

Reduced code(1) 2.35

µA/MHz

Coremark 2.65 102

Dhrystone 2.1 2.75 106

Fibonacci 2.60 100

While(1) 2.35 90

Range 1

fHCLK = 80 MHz

Reduced code(1) 8.45

106

µA/MHz

Coremark 9.45 118

Dhrystone 2.1 9.85 123

Fibonacci 9.25 116

While(1) 8.45 106

IDD_ALL

(LPRun)

Supply

current in

Low-power

run

fHCLK = fMSI = 2 MHz

all peripherals disable

Reduced code(1) 225

µA

113

µA/MHz

Coremark 260 130

Dhrystone 2.1 270 135

Fibonacci 245 123

While(1) 285 143

1. Reduced code used for characterization results provided in Table 26, Table 27, Table 28.

DS11913 Rev 5 105/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

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Table 30. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART disable

Symbol Parameter

Conditions TYP

Unit

TYP

Unit

-Voltage

scaling Code 25 °C 25 °C

IDD_ALL

(Run)

Supply

current in

Run mode

fHCLK = fHSE up to

48 MHz included,

bypass mode

PLL ON above

48 MHz

all peripherals

disable

Range 2

fHCLK = 26 MHz

Reduced code(1) 2.75

106

µA/MHz

Coremark 2.50 96

Dhrystone 2.1 2.50 96

Fibonacci 2.30 88

While(1) 2.20 84.6

Range 1

fHCLK = 80 MHz

Reduced code(1) 8.85

111

µA/MHz

Coremark 8.15 102

Dhrystone 2.1 8.15 102

Fibonacci 7.55 94

While(1) 7.95 99

IDD_ALL

(LPRun)

Supply

current in

Low-power

run

fHCLK = fMSI = 2 MHz

all peripherals disable

Reduced code(1) 340

µA

170

µA/MHz

Coremark 380 190

Dhrystone 2.1 355 178

Fibonacci 355 178

While(1) 405 203

1. Reduced code used for characterization results provided in Table 26, Table 27, Table 28.

Table 31. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM1

Symbol Parameter

Conditions TYP

Unit

TYP

Unit

-Voltage

scaling Code 25 °C 25 °C

IDD_ALL

(Run)

Supply

current in

Run mode

fHCLK = fHSE up to

48 MHz included,

bypass mode

PLL ON above

48 MHz all

peripherals

disable

Range 2

fHCLK = 26 MHz

Reduced code(1) 2.40

µA/MHz

Coremark 2.20 85

Dhrystone 2.1 2.35 90

Fibonacci 2.20 85

While(1) 2.30 88

Range 1

fHCLK = 80 MHz

Reduced code(1) 8.55

107

µA/MHz

Coremark 7.75 97

Dhrystone 2.1 8.45 106

Fibonacci 7.80 98

While(1) 8.75 109

IDD_ALL

(LPRun)

Supply

current in

Low-power

run

fHCLK = fMSI = 2 MHz

all peripherals disable

Reduced code(1) 220

µA

110

µA/MHz

Coremark 190 95

Dhrystone 2.1 215 108

Fibonacci 200 100

While(1) 210 105

1. Reduced code used for characterization results provided in Table 26, Table 27, Table 28.

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

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Table 32. Current consumption in Sleep and Low-power sleep modes, Flash ON

Symbol Parameter

Conditions TYP MAX(1)

Unit

-Voltage

scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

IDD_ALL

(Sleep)

Supply

current in

sleep

mode,

fHCLK = fHSE up

to 48 MHz

included, bypass

mode

pll ON above

48 MHz all

peripherals

disable

Range 2

26 MHz 0.700 0.730 0.830 1.00 1.35 0.80 0.90 1.05 1.30 1.90

16 MHz 0.475 0.505 0.605 0.775 1.10 0.55 0.65 0.80 1.05 1.65

8 MHz 0.300 0.325 0.425 0.590 0.920 0.35 0.45 0.60 0.85 1.45

4 MHz 0.210 0.235 0.335 0.500 0.830 0.25 0.30 0.45 0.75 1.35

2 MHz 0.165 0.190 0.290 0.455 0.785 0.20 0.25 0.40 0.70 1.25

1 MHz 0.145 0.170 0.265 0.430 0.760 0.15 0.25 0.40 0.65 1.25

100 kHz 0.125 0.150 0.245 0.410 0.740 0.15 0.20 0.35 0.65 1.20

Range 1

80 MHz 2.30 2.35 2.45 2.65 3.05 2.55 2.65 2.85 3.15 3.80

72 MHz 2.10 2.15 2.25 2.45 2.80 2.35 2.40 2.60 2.90 3.55

64 MHz 1.90 1.90 2.05 2.25 2.60 2.10 2.20 2.35 2.70 3.35

48 MHz 1.40 1.40 1.55 1.75 2.15 1.60 1.65 1.85 2.15 2.80

32 MHz 0.970 1.00 1.15 1.30 1.70 1.10 1.20 1.40 1.70 2.35

24 MHz 0.765 0.800 0.920 1.10 1.50 0.90 0.95 1.15 1.45 2.10

16 MHz 0.555 0.590 0.705 0.895 1.25 0.65 0.75 0.90 1.20 1.85

IDD_ALL

(LPSleep)

Supply

current in

low-power

sleep

mode

fHCLK = fMSI

all peripherals disable

2 MHz 76.0 110 215 395 745 120 185 355 610 1250

µA

1 MHz 54.0 86.5 195 370 725 88.5 160 335 585 1250

400 kHz 39.0 70.5 175 355 710 68.5 140 320 570 1200

100 kHz 35.5 75.0 195 345 715 66.0 130 305 560 1200

1. Guaranteed by characterization results, unless otherwise specified.

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

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Table 33. Current consumption in Low-power sleep modes, Flash in power-down

Symbol Parameter

Conditions TYP MAX(1)

Unit

-Voltage

scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

IDD_ALL

(LPSleep)

Supply current

in low-power

sleep mode

fHCLK = fMSI

all peripherals disable

2 MHz 76.5 105 220 410 740 110 175 350 600 1250

µA

1 MHz 54.0 81.0 195 385 715 81.5 155 325 570 1200

400 kHz 28.0 64.5 175 370 695 60.5 130 305 555 1200

100 kHz 21.5 55.0 170 360 690 58.5 120 300 550 1200

1. Guaranteed by characterization results, unless otherwise specified.

Table 34. Current consumption in Stop 2 mode

Symbol Parameter

Conditions TYP MAX(1)

Unit

-V

DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

IDD_ALL

(Stop 2)

Supply current in

Stop 2 mode,

RTC disabled

1.8 V 2.05 5.40 19.0 44.0 97.0 4.00 11.5 41.5 100 220

µA

2.4 V 2.10 5.45 19.0 44.5 98.5 4.05 11.5 42.0 100 225

3 V 2.05 5.55 19.5 45.0 100 4.10 12.0 43.0 105 230

3.6 V 2.05 5.65 20.0 46.5 105 4.20 12.0 44.0 105 235

IDD_ALL

(Stop 2 with

RTC)

Supply current in

Stop 2 mode,

RTC enabled

RTC clocked by LSI

1.8 V 2.30 5.65 19.0 44.0 97.0 4.50 12.0 42.0 100 220

µA

2.4 V 2.35 5.80 19.5 44.5 99.0 4.65 12.0 42.5 100 225

3 V 2.50 5.90 20.0 45.5 100 4.90 12.5 43.5 105 230

3.6 V 2.60 6.15 20.5 47.0 105 5.20 13.0 44.5 105 235

RTC clocked by LSE

bypassed at 32768 Hz

1.8 V 2.60 6.05 21.0 48.0 97.0 - - - - -

2.4 V 2.55 6.20 21.0 49.0 98.5 - - - - -

3 V 2.80 6.35 21.5 49.5 100 - - - - -

3.6 V 2.85 6.60 22.5 51.5 105 - - - - -

RTC clocked by LSE

quartz(2)

in low drive mode

1.8 V 2.40 5.70 19.0 44.5 98.0 - - - - -

2.4 V 2.50 5.85 19.5 45.0 99.5 - - - - -

3 V 2.60 6.00 20.0 46.0 100 - - - - -

3.6 V 2.65 6.25 20.5 47.0 105 - - - - -

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IDD_ALL

(wakeup from

Stop 2)

Supply current

during wakeup

from Stop 2

mode

Wakeup clock is

MSI = 48 MHz,

voltage Range 1.

See (3).

3 V1.85---------

Wakeup clock is

MSI = 4 MHz,

voltage Range 2.

See (3).

3 V1.50---------

Wakeup clock is

HSI16 = 16 MHz,

voltage Range 1.

See (3).

3 V1.55---------

1. Guaranteed based on test during characterization, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 41: Low-power mode wakeup timings.

Table 34. Current consumption in Stop 2 mode (continued)

Symbol Parameter

Conditions TYP MAX(1)

Unit

-V

DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

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Table 35. Current consumption in Stop 1 mode

Symbol Parameter

Conditions TYP MAX(1)

Unit

-V

DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

IDD_ALL

(Stop 1)

Supply

current in

Stop 1 mode,

RTC disabled

1.8 V 9.85 29.0 100 225 430 17.0 49.5 185 395 850

µA

2.4 V 9.85 29.5 100 225 435 17.0 49.5 185 395 850

3 V 9.90 29.5 100 225 435 17.5 50.0 185 400 850

3.6 V 10.0 28.0 105 230 410 17.5 50.5 190 405 860

IDD_ALL

(Stop 1 with

RTC)

Supply

current in stop

1 mode,

RTC enabled

RTC clocked by LSI

1.8 V 10.5 29.5 100 225 430 17.0 50.0 185 395 840

µA

2.4 V 10.5 29.5 100 225 435 17.0 50.5 185 395 845

3 V 10.5 30.0 105 225 435 17.5 50.5 185 400 855

3.6 V 10.5 30.0 105 230 440 17.5 51.5 190 405 860

RTC clocked by LSE

bypassed, at 32768 Hz

1.8 V 10.0 29.5 100 225 435 - - - - -

2.4 V 10.0 29.5 100 225 435 - - - - -

3 V 10.5 30.0 105 225 440 - - - - -

3.6 V 11.0 30.5 105 230 440 - - - - -

RTC clocked by LSE quartz(2)

in low drive mode

1.8 V 10.0 29.0 99.5 220 435 - - - - -

2.4 V 10.0 29.0 99.5 220 435 - - - - -

3 V 10.0 29.0 100 220 440 - - - - -

3.6 V 10.5 29.5 100 225 440 - - - - -

IDD_ALL

(wakeup

from Stop1)

Supply

current during

wakeup from

Stop 1

Wakeup clock MSI = 48 MHz,

voltage Range 1.

See (3).

3 V1.15---------

Wakeup clock MSI = 4 MHz,

voltage Range 2.

See (3).

3 V1.20---------

Wakeup clock HSI16 =

16 MHz, voltage Range 1.

See (3).

3 V1.20---------

1. Guaranteed based on test during characterization, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 41: Low-power mode wakeup timings.

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

110/210 DS11913 Rev 5

Table 36. Current consumption in Stop 0

Symbol Parameter

Conditions TYP MAX(1)

1. Guaranteed by characterization results, unless otherwise specified.

Unit

VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

IDD_ALL

(Stop 0)

Supply

current in

Stop 0 mode,

RTC disabled

1.8 V 125 150 240 390 645 145 190 350 600 1150

µA

2.4 V 125 150 240 390 645 150 195 355 605 1150

3 V 125 150 245 395 650 155 195 360 610 1150

3.6 V 125 155 245 400 655 155 200 365 615 1150(2)

2. Guaranteed by test in production.

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

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Table 37. Current consumption in Standby mode

Symbol Parameter

Conditions TYP MAX(1)

Unit

-V

DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

IDD_ALL

(Standby)

Supply current

in Standby

mode (backup

registers

retained),

RTC disabled

no independent watchdog

1.8 V 100 270 1200 3300 8650 205 650 3250 9250 25000

2.4 V 110 305 1400 3850 10000 225 750 3750 11000 29000

3 V 125 360 1650 4550 12000 290 950 4450 13000 33500

3.6 V 160 445 2000 5500 14500 355 1150 5250 15000 38500

with independent

watchdog

1.8 V 265 435 1350 3450 8700 - - - - -

2.4 V 335 540 1650 4100 10500 - - - - -

3 V 420 655 1950 4850 12500 - - - - -

3.6 V 580 895 2450 5950 14500 - - - - -

IDD_ALL

(Standby

with RTC)

Supply current

in Standby

mode (backup

registers

retained),

RTC enabled

RTC clocked by LSI, no

independent watchdog

1.8 V 345 505 1400 3450 8600 720 1150 3750 9550 25000

2.4 V 420 620 1650 4050 10000 875 1450 4400 11500 29000

3 V 510 745 2000 4750 12000 1070 1700 5100 13500 34000

3.6 V 635 915 2450 5900 14500 1320 2100 6000 15500 39000

RTC clocked by LSI, with

independent watchdog

1.8 V 375 540 1450 3550 8800 - - - - -

2.4 V 490 690 1800 4250 10500 - - - - -

3 V 620 860 2150 5100 12500 - - - - -

3.6 V 845 1150 2700 6200 15000 - - - - -

RTC clocked by LSE

bypassed at 32768Hz

1.8 V 395 - - - - - - - - -

2.4 V 500 - - - - - - - - -

3 V 625 - - - - - - - - -

3.6 V 795 - - - - - - - - -

RTC clocked by LSE

quartz (2) in low drive mode

1.8 V 375 550 1500 3550 8800 - - - - -

2.4 V 460 665 1750 4250 10500 - - - - -

3 V 565 810 2100 5050 12500 - - - - -

3.6 V 720 1000 2600 5900 15000 - - - - -

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

112/210 DS11913 Rev 5

IDD_ALL

(SRAM2)(3)

Supply current

to be added in

Standby mode

when SRAM2

is retained

1.8 V 250 730 2700 6350 13850 575 1800 6350 14500 32000

2.4 V 250 740 2700 6150 14000 620 1800 6450 14500 32000

3 V 255 740 2700 6450 13500 645 1850 6500 15000 32500

3.6 V 255 755 2800 6500 13500 790 1950 6500 15000 33000

IDD_ALL

(wakeup

from

Standby)

Supply current

during wakeup

from Standby

mode

Wakeup clock is

MSI = 4 MHz.

See (4).

3 V2.00---------mA

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IDD_ALL(Standby

+ RTC) + IDD_ALL(SRAM2).

4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 41: Low-power mode wakeup timings.

Table 37. Current consumption in Standby mode (continued)

Symbol Parameter

Conditions TYP MAX(1)

Unit

-V

DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Table 38. Current consumption in Shutdown mode

Symbol Parameter

Conditions TYP MAX(1)

Unit

-V

DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

IDD_ALL

(Shutdown)

Supply current

in Shutdown

mode

(backup

registers

retained) RTC

disabled

1.8 V 19.0 120 720 2200 6400 38.0 350 2050 6350 19500

2.4 V 26.0 145 855 2600 7450 62.0 400 2400 7450 22500

3 V 37.0 185 1050 3100 8700 105 500 2850 8750 26000

3.6 V 67.0 260 1350 3950 11000 160 650 3500 10500 30000

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

DS11913 Rev 5 113/210

IDD_ALL

(Shutdown

with RTC)

Supply current

in Shutdown

mode

(backup

registers

retained) RTC

enabled

RTC clocked by LSE

bypassed at 32768 Hz

1.8 V 165 275 950 2600 6550 - - - - -

2.4 V 235 370 1150 3100 7650 - - - - -

3 V 325 485 1450 3750 9050 - - - - -

3.6 V 445 655 1900 4800 11500 - - - - -

RTC clocked by LSE

quartz (2) in low drive

mode

1.8 V 290 410 1050 2550 6700 - - - - -

2.4 V 375 515 1250 3050 7800 - - - - -

3 V 480 645 1550 3700 8800 - - - - -

3.6 V 625 840 1950 4950 11500 - - - - -

IDD_ALL

(wakeup from

Shutdown)

Supply current

during wakeup

from Shutdown

mode

Wakeup clock is

MSI = 4 MHz.

See (3).

3 V 1.00 - - - - - - - - - mA

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 41: Low-power mode wakeup timings.

Table 38. Current consumption in Shutdown mode (continued)

Symbol Parameter

Conditions TYP MAX(1)

Unit

-V

DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Table 39. Current consumption in VBAT mode

Symbol Parameter

Conditions TYP MAX(1)

Unit

-V

BAT 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

IDD_VBAT

(VBAT)

Backup domain

supply current

RTC disabled

1.8 V 3.00 - - - - - - - - -

2.4 V 4.00 - - - - - - - - -

3 V 5.00 - - - - - - - - -

3.6 V 11.0 - - - - - - - - -

RTC enabled and

clocked by LSE

bypassed at 32768 Hz

1.8 V 145 165 285 550 - - - - - -

2.4 V 205 235 370 670 - - - - - -

3 V 285 315 470 820 - - - - - -

3.6 V 375 430 715 1350 - - - - - -

1. Guaranteed by characterization results, unless otherwise specified.

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

114/210 DS11913 Rev 5

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is

externally held low. The value of this current consumption can be simply computed by using

the pull-up/pull-down resistors values given in Ta ble 60: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to

estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate

voltage level is externally applied. This current consumption is caused by the input Schmitt

trigger circuits used to discriminate the input value. Unless this specific configuration is

required by the application, this supply current consumption can be avoided by configuring

these I/Os in analog mode. This is notably the case of ADC input pins which should be

configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to

floating pins, they must either be configured in analog mode, or forced internally to a definite

digital value. This can be done either by using pull-up/down resistors or by configuring the

pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 40: Peripheral current consumption), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the I/O

supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load

(internal or external) connected to the pin:

where

ISW is the current sunk by a switching I/O to charge/discharge the capacitive load

VDDIOx is the I/O supply voltage

fSW is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS

CS is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed

frequency.

ISW VDDIOx fSW C××=

DS11913 Rev 5 115/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 40. The MCU is placed

under the following conditions:

•All I/O pins are in Analog mode

•The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

•Ambient operating temperature and supply voltage conditions summarized in Table 19:

Voltage characteristics

•The power consumption of the digital part of the on-chip peripherals is given in

Table 40. The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

Table 40. Peripheral current consumption

Peripheral Range 1 Range 2 Low-power run

and sleep Unit

AHB

Bus Matrix(1) 3.2 2.9 3.1

µA/MHz

ADC independent clock domain 0.4 0.1 0.2

ADC clock domain 2.1 1.9 1.9

AES 1.7 1.5 1.6

CRC 0.4 0.2 0.3

DMA1 1.4 1.3 1.4

DMA2 1.5 1.3 1.4

FLASH 6.2 5.2 5.8

GPIOA(2) 1.7 1.4 1.6

GPIOB(2)) 1.6 1.3 1.6

GPIOC(2) 1.7 1.5 1.6

GPIOD(2) 1.8 1.6 1.7

GPIOE(2) 1.7 1.6 1.6

GPIOH(2) 0.6 0.6 0.5

QSPI 7.0 5.8 7.3

RNG independent clock domain 2.2 N/A N/A

RNG clock domain 0.5 N/A N/A

SRAM1 0.8 0.9 0.7

SRAM2 1.0 0.8 0.8

TSC 1.6 1.3 1.3

All AHB Peripherals 25.2 21.7 23.6

APB1 AHB to APB1 bridge(3) 0.9 0.7 0.9

CAN1 4.1 3.2 3.9

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APB1

DAC1 2.4 1.8 2.2

µA/MHz

RTCA 1.7 1.1 2.1

CRS 0.3 0.3 0.6

USB FS independent clock

domain 2.9 N/A N/A

USB FS clock domain 2.3 N/A N/A

I2C1 independent clock domain 3.5 2.8 3.4

I2C1 clock domain 1.1 0.9 1.0

I2C2 independent clock domain 3.5 3.0 3.4

I2C2 clock domain 1.1 0.7 0.9

I2C3 independent clock domain 2.9 2.3 2.5

I2C3 clock domain 0.9 0.4 0.8

LPUART1 independent clock

domain 1.9 1.6 1.8

LPUART1 clock domain 0.6 0.6 0.6

LPTIM1 independent clock

domain 2.9 2.4 2.8

LPTIM1 clock domain 0.8 0.4 0.7

LPTIM2 independent clock

domain 3.1 2.7 3.9

LPTIM2 clock domain 0.8 0.7 0.8

OPAMP 0.4 0.2 0.4

PWR 0.4 0.1 0.4

SPI2 1.8 1.6 1.6

SPI3 1.7 1.3 1.6

TIM2 6.2 5.0 5.9

TIM6 1.0 0.6 0.9

USART2 independent clock

domain 4.1 3.6 3.8

USART2 clock domain 1.3 0.9 1.1

USART3 independent clock

domain 4.3 3.5 4.2

USART3 clock domain 1.5 1.1 1.3

WWDG 0.5 0.5 0.5

All APB1 on 51.5 35.5 48.6

Table 40. Peripheral current consumption (continued)

Peripheral Range 1 Range 2 Low-power run

and sleep Unit

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STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

6.3.6 Wakeup time from low-power modes and voltage scaling

transition times

The wakeup times given in Table 41 are the latency between the event and the execution of

the first user instruction.

The device goes in low-power mode after the WFE (Wait For Event) instruction.

APB2

AHB to APB2(4) 1.0 0.9 0.9

µA/MHz

FW 0.2 0.2 0.2

SAI1 independent clock domain 2.3 1.8 1.9

SAI1 clock domain 2.1 1.8 2.0

SDMMC1 independent clock

domain 4.7 3.9 3.9

SDMMC1 clock domain 2.5 1.9 1.9

SPI1 1.8 1.6 1.7

SYSCFG/VREFBUF/COMP 0.6 0.5 0.6

TIM1 8.1 6.5 7.6

TIM15 3.7 3.0 3.4

TIM16 2.7 2.1 2.6

USART1 independent clock

domain 4.8 4.2 4.6

USART1 clock domain 1.5 1.3 1.7

All APB2 on 24.2 19.9 22.6

ALL 100.9 77.1 94.8

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when

the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current

consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog

mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).

3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.

4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.

Table 40. Peripheral current consumption (continued)

Peripheral Range 1 Range 2 Low-power run

and sleep Unit

Table 41. Low-power mode wakeup timings(1)

Symbol Parameter Conditions Typ Max Unit

tWUSLEEP Wakeup time from Sleep

mode to Run mode -66

Nb of

CPU

cycles

tWULPSLEEP

Wakeup time from Low-

power sleep mode to Low-

power run mode

Wakeup in Flash with Flash in power-down

during low-power sleep mode (SLEEP_PD=1

in FLASH_ACR) and with clock MSI = 2 MHz

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tWUSTOP0

Wake up time from Stop 0

mode to Run mode in

Flash

Range 1 Wakeup clock MSI = 48 MHz 3.34 4.3

µs

Wakeup clock HSI16 = 16 MHz 3.7 6.5

Range 2

Wakeup clock MSI = 24 MHz 3.8 7.1

Wakeup clock HSI16 = 16 MHz 3.7 6.5

Wakeup clock MSI = 4 MHz 9.3 7.1

Wake up time from Stop 0

mode to Run mode in

SRAM1

Range 1 Wakeup clock MSI = 48 MHz 1.85 2.7

Wakeup clock HSI16 = 16 MHz 2.68 3

Range 2

Wakeup clock MSI = 24 MHz 2.47 3.4

Wakeup clock HSI16 = 16 MHz 2.68 3

Wakeup clock MSI = 4 MHz 9.67 12.5

tWUSTOP1

Wake up time from Stop 1

mode to Run in Flash

Range 1 Wakeup clock MSI = 48 MHz 6.75 7.6

µs

Wakeup clock HSI16 = 16 MHz 7.14 8

Range 2

Wakeup clock MSI = 24 MHz 7 7.82

Wakeup clock HSI16 = 16 MHz 7.14 7.9

Wakeup clock MSI = 4 MHz 10.44 11.9

Wake up time from Stop 1

mode to Run mode in

SRAM1

Range 1 Wakeup clock MSI = 48 MHz 5.21 5.9

Wakeup clock HSI16 = 16 MHz 6.23 6.9

Range 2

Wakeup clock MSI = 24 MHz 5.73 6.4

Wakeup clock HSI16 = 16 MHz 6.23 6.9

Wakeup clock MSI = 4 MHz 10.9 12.3

Wake up time from Stop 1

mode to Low-power run

mode in Flash Regulator in

low-power

mode (LPR=1

in PWR_CR1)

Wakeup clock MSI = 2 MHz

16.05 19.2

Wake up time from Stop 1

mode to Low-power run

mode in SRAM1

17.06 20.3

Table 41. Low-power mode wakeup timings(1) (continued)

Symbol Parameter Conditions Typ Max Unit

DS11913 Rev 5 119/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

tWUSTOP2

Wake up time from Stop 2

mode to Run mode in

Flash

Range 1 Wakeup clock MSI = 48 MHz 7.93 9.1

µs

Wakeup clock HSI16 = 16 MHz 7.32 8.5

Range 2

Wakeup clock MSI = 24 MHz 8.25 9.4

Wakeup clock HSI16 = 16 MHz 7.32 8.4

Wakeup clock MSI = 4 MHz 11.43 13.3

Wake up time from Stop 2

mode to Run mode in

SRAM1

Range 1 Wakeup clock MSI = 48 MHz 5.23 6

Wakeup clock HSI16 = 16 MHz 6.33 7.1

Range 2

Wakeup clock MSI = 24 MHz 5.78 6.5

Wakeup clock HSI16 = 16 MHz 6.33 7.1

Wakeup clock MSI = 4 MHz 11.37 12.9

tWUSTBY Wakeup time from Standby

mode to Run mode Range 1 Wakeup clock MSI = 8 MHz 16.13 18.2 µs

Wakeup clock MSI = 4 MHz 24.06 26.6

tWUSTBY

SRAM2

Wakeup time from Standby

with SRAM2 to Run mode Range 1 Wakeup clock MSI = 8 MHz 16.09 18.2 µs

Wakeup clock MSI = 4 MHz 24 26.6

tWUSHDN

Wakeup time from

Shutdown mode to Run

mode

Range 1 Wakeup clock MSI = 4 MHz 255.38 316.41 µs

1. Guaranteed by characterization results.

Table 41. Low-power mode wakeup timings(1) (continued)

Symbol Parameter Conditions Typ Max Unit

Table 42. Regulator modes transition times(1)

Symbol Parameter Conditions Typ Max Unit

tWULPRUN Wakeup time from Low-power run mode to

Run mode(2) Code run with MSI 2 MHz 5 7

µs

tVOST Regulator transition time from Range 2 to

Range 1 or Range 1 to Range 2(3) Code run with MSI 24 MHz 20 40

1. Guaranteed by characterization results.

2. Time until REGLPF flag is cleared in PWR_SR2.

3. Time until VOSF flag is cleared in PWR_SR2.

Table 43. Wakeup time using USART/LPUART(1)

Symbol Parameter Conditions Typ Max Unit

tWUUSART

tWULPUART

Wakeup time needed to calculate the

maximum USART/LPUART baudrate

permitting to wakeup up from stop mode

when USART/LPUART clock source is

HSI16

Stop 0 mode - 1.7

µs

Stop 1 mode and Stop 2

mode -8.5

1. Guaranteed by design.

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

120/210 DS11913 Rev 5

6.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,

the recommended clock input waveform is shown in Figure 19: High-speed external clock

source AC timing diagram.

Figure 19. High-speed external clock source AC timing diagram

Table 44. High-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSE_ext User external clock source frequency

Voltage scaling

Range 1 -848

MHz

Voltage scaling

Range 2 -826

VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx -V

DDIOx V

VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx

tw(HSEH)

tw(HSEL) OSC_IN high or low time

Voltage scaling

Range 1 7- -

Voltage scaling

Range 2 18 - -

1. Guaranteed by design.

MS19214V2

VHSEH

tf(HSE)

90%

10%

THSE

tr(HSE)

VHSEL

tw(HSEH)

tw(HSEL)

DS11913 Rev 5 121/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,

the recommended clock input waveform is shown in Figure 20.

Figure 20. Low-speed external clock source AC timing diagram

Table 45. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fLSE_ext User external clock source frequency - - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx -V

DDIOx V

VLSEL OSC32_IN input pin low level voltage - VSS -0.3 V

DDIOx

tw(LSEH)

tw(LSEL) OSC32_IN high or low time - 250 - - ns

1. Guaranteed by design.

MS19215V2

VLSEH

tf(LSE)

90%

10%

TLSE

tr(LSE)

VLSEL

tw(LSEH)

tw(LSEL)

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122/210 DS11913 Rev 5

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on design

simulation results obtained with typical external components specified in Table 46. In the

application, the resonator and the load capacitors have to be placed as close as possible to

the oscillator pins in order to minimize output distortion and startup stabilization time. Refer

to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 21). CL1 and CL2 are usually the

same size. The crystal manufacturer typically specifies a load capacitance which is the

series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF

can be used as a rough estimate of the combined pin and board capacitance) when sizing

CL1 and CL2.

Table 46. HSE oscillator characteristics(1)

1. Guaranteed by design.

Symbol Parameter Conditions(2)

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

Min Typ Max Unit

fOSC_IN Oscillator frequency - 4 8 48 MHz

RFFeedback resistor - - 200 - kΩ

IDD(HSE) HSE current consumption

During startup(3)

3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time

--5.5

VDD = 3 V,

Rm = 30 Ω,

CL = 10 pF@8 MHz

-0.44-

VDD = 3 V,

Rm = 45 Ω,

CL = 10 pF@8 MHz

-0.45-

VDD = 3 V,

Rm = 30 Ω,

CL = 5 pF@48 MHz

-0.68-

VDD = 3 V,

Rm = 30 Ω,

CL = 10 pF@48 MHz

-0.94-

VDD = 3 V,

Rm = 30 Ω,

CL = 20 pF@48 MHz

-1.77-

Gm Maximum critical crystal

transconductance Startup - - 1.5 mA/V

tSU(HSE)(4)

4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly

with the crystal manufacturer

Startup time VDD is stabilized - 2 - ms

DS11913 Rev 5 123/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 21. Typical application with an 8 MHz crystal

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator

oscillator. All the information given in this paragraph are based on design simulation results

obtained with typical external components specified in Table 47. In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

MS19876V1

(1)

OSC_IN

OSC_OUT

Bias

controlled

gain

fHSE

REXT

8 MHz

resonator

Resonator with integrated

capacitors

CL1

CL2

Table 47. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

IDD(LSE) LSE current consumption

LSEDRV[1:0] = 00

Low drive capability -250-

LSEDRV[1:0] = 01

Medium low drive capability -315-

LSEDRV[1:0] = 10

Medium high drive capability -500-

LSEDRV[1:0] = 11

High drive capability -630-

Gmcritmax Maximum critical crystal

LSEDRV[1:0] = 00

Low drive capability --0.5

µA/V

LSEDRV[1:0] = 01

Medium low drive capability - - 0.75

LSEDRV[1:0] = 10

Medium high drive capability --1.7

LSEDRV[1:0] = 11

High drive capability --2.7

tSU(LSE)(3) Startup time VDD is stabilized - 2 - s

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

124/210 DS11913 Rev 5

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 22. Typical application with a 32.768 kHz crystal

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden

to add one.

1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

MS30253V2

OSC32_IN

OSC32_OUT

Drive

programmable

amplifier

fLSE

32.768 kHz

resonator

Resonator with integrated

capacitors

CL1

CL2

DS11913 Rev 5 125/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

6.3.8 Internal clock source characteristics

The parameters given in Table 48 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 22: General operating

conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Table 48. HSI16 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz

TRIM HSI16 user trimming step

Trimming code is not a

multiple of 64 0.2 0.3 0.4

Trimming code is a

multiple of 64 -4 -6 -8

DuCy(HSI16)(2) Duty Cycle - 45 - 55 %

∆Temp(HSI16) HSI16 oscillator frequency

drift over temperature

TA= 0 to 85 °C -1 - 1 %

TA= -40 to 125 °C -2 - 1.5 %

∆VDD(HSI16) HSI16 oscillator frequency

drift over VDD VDD=1.62 V to 3.6 V -0.1 - 0.05 %

tsu(HSI16)(2) HSI16 oscillator start-up

time - - 0.8 1.2 μs

tstab(HSI16)(2) HSI16 oscillator

stabilization time --35μs

IDD(HSI16)(2) HSI16 oscillator power

consumption - - 155 190 μA

1. Guaranteed by characterization results.

2. Guaranteed by design.

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

126/210 DS11913 Rev 5

Figure 23. HSI16 frequency versus temperature

MSv39299V1

15.6

15.7

15.8

15.9

16.1

16.2

16.3

16.4

MHz

min mean max

+1%

-1%

+2%

-2%

+1.5%

-1.5%

-40 -20 0 20 40 60 80 100 120 °C

DS11913 Rev 5 127/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

Multi-speed internal (MSI) RC oscillator

Table 49. MSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fMSI

MSI frequency

after factory

calibration, done

at VDD=3 V and

TA=30 °C

MSI mode

Range 0 98.7 100 101.3

kHz

Range 1 197.4 200 202.6

Range 2 394.8 400 405.2

Range 3 789.6 800 810.4

Range 4 0.987 1 1.013

MHz

Range 5 1.974 2 2.026

Range 6 3.948 4 4.052

Range 7 7.896 8 8.104

Range 8 15.79 16 16.21

Range 9 23.69 24 24.31

Range 10 31.58 32 32.42

Range 11 47.38 48 48.62

PLL mode

XTAL=

32.768 kHz

Range 0 - 98.304 -

kHz

Range 1 - 196.608 -

Range 2 - 393.216 -

Range 3 - 786.432 -

Range 4 - 1.016 -

MHz

Range 5 - 1.999 -

Range 6 - 3.998 -

Range 7 - 7.995 -

Range 8 - 15.991 -

Range 9 - 23.986 -

Range 10 - 32.014 -

Range 11 - 48.005 -

∆TEMP(MSI)(2) MSI oscillator

frequency drift

over temperature

MSI mode

TA= -0 to 85 °C -3.5 - 3

TA= -40 to 125 °C -8 - 6

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

128/210 DS11913 Rev 5

∆VDD(MSI)(2)

MSI oscillator

frequency drift

over VDD

(reference is 3 V)

MSI mode

Range 0 to 3

VDD=1.62 V

to 3.6 V -1.2 -

0.5

VDD=2.4 V

to 3.6 V -0.5 -

Range 4 to 7

VDD=1.62 V

to 3.6 V -2.5 -

0.7

VDD=2.4 V

to 3.6 V -0.8 -

Range 8 to 11

VDD=1.62 V

to 3.6 V -5 -

1.2

VDD=2.4 V

to 3.6 V -1.6 -

∆FSAMPLING

(MSI)(2)(6)

Frequency

variation in

sampling mode(3) MSI mode

TA= -40 to 85 °C - 1 2

TA= -40 to 125 °C - 2 4

P_USB

Jitter(MSI)(6) Period jitter for

USB clock(4) PLL mode

Range 11

for next

transition ---3.458

for paired

transition ---3.916

MT_USB

Jitter(MSI)(6) Medium term jitter

for USB clock(5) PLL mode

Range 11

for next

transition ---2

for paired

transition ---1

CC jitter(MSI)(6) RMS cycle-to-

cycle jitter PLL mode Range 11 - - 60 - ps

P jitter(MSI)(6) RMS Period jitter PLL mode Range 11 - - 50 - ps

tSU(MSI)(6) MSI oscillator

start-up time

Range 0 - - 10 20

Range 1 - - 5 10

Range 2 - - 4 8

Range 3 - - 3 7

Range 4 to 7 - - 3 6

Range 8 to 11 - - 2.5 6

tSTAB(MSI)(6) MSI oscillator

stabilization time

PLL mode

Range 11

10 % of final

frequency - - 0.25 0.5

5 % of final

frequency --0.51.25

1 % of final

frequency ---2.5

Table 49. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

DS11913 Rev 5 129/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

IDD(MSI)(6) MSI oscillator

power

consumption

MSI and

PLL mode

Range 0 - - 0.6 1

µA

Range 1 - - 0.8 1.2

Range 2 - - 1.2 1.7

Range 3 - - 1.9 2.5

Range 4 - - 4.7 6

Range 5 - - 6.5 9

Range 6 - - 11 15

Range 7 - - 18.5 25

Range 8 - - 62 80

Range 9 - - 85 110

Range 10 - - 110 130

Range 11 - - 155 190

1. Guaranteed by characterization results.

2. This is a deviation for an individual part once the initial frequency has been measured.

3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.

4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter

of MSI @48 MHz clock.

5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.

For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28

cycles.

For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over

56 cycles.

6. Guaranteed by design.

Table 49. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

[HA] +Rangemo3—O—Range4tu7+Rangestull 256 128 64 32 16 100KHZ 05 0.1 0.2 0.4 lMHZ SDDKHZ 0.8 1.6 3.2 BMHZ 6.4 16MH1 12.8 25,6 48MHZ Freq [MHz]

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

130/210 DS11913 Rev 5

Figure 24. Typical current consumption versus MSI frequency

High-speed internal 48 MHz (HSI48) RC oscillator

Table 50. HSI48 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI48 HSI48 Frequency VDD=3.0V, TA=30°C - 48 - MHz

TRIM HSI48 user trimming step - - 0.11(2) 0.18(2) %

USER TRIM

COVERAGE HSI48 user trimming coverage ±32 steps ±3(3) ±3.5(3) -%

DuCy(HSI48) Duty Cycle - 45(2) -55

(2) %

ACCHSI48_REL

Accuracy of the HSI48 oscillator

over temperature (factory

calibrated)

VDD = 3.0 V to 3.6 V,

TA = –15 to 85 °C --±3

(3)

VDD = 1.65 V to 3.6 V,

TA = –40 to 125 °C --±4.5

(3)

DVDD(HSI48) HSI48 oscillator frequency drift

with VDD

VDD = 3 V to 3.6 V - 0.025(3) 0.05(3)

VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3)

tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) μs

IDD(HSI48) HSI48 oscillator power

consumption --340

(2) 380(2) μA

DS11913 Rev 5 131/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

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Figure 25. HSI48 frequency versus temperature

Low-speed internal (LSI) RC oscillator

NT jitter Next transition jitter

Accumulated jitter on 28 cycles(4) --+/-0.15

(2) -ns

PT jitter Paired transition jitter

Accumulated jitter on 56 cycles(4) --+/-0.25

(2) -ns

1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Jitter measurement are performed without clock source activated in parallel.

Table 50. HSI48 oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

MSv40989V1

-6

-4

-2

-50 -30 -10 10 30 50 70 90 110 130

Avg min max °C

Table 51. LSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fLSI LSI Frequency VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 kHz

VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34

tSU(LSI)(2) LSI oscillator start-

up time --80130μs

tSTAB(LSI)(2) LSI oscillator

stabilization time 5% of final frequency - 125 180 μs

IDD(LSI)(2) LSI oscillator power

consumption --110180nA

1. Guaranteed by characterization results.

2. Guaranteed by design.

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

132/210 DS11913 Rev 5

6.3.9 PLL characteristics

The parameters given in Table 52 are derived from tests performed under temperature and

VDD supply voltage conditions summarized in Table 22: General operating conditions.

Table 52. PLL, PLLSAI1 characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fPLL_IN

PLL input clock(2) -4-16MHz

PLL input clock duty cycle - 45 - 55 %

fPLL_P_OUT PLL multiplier output clock P Voltage scaling Range 1 3.0968 - 80 MHz

Voltage scaling Range 2 3.0968 - 26

fPLL_Q_OUT PLL multiplier output clock Q Voltage scaling Range 1 12 - 80 MHz

Voltage scaling Range 2 12 - 26

fPLL_R_OUT PLL multiplier output clock R Voltage scaling Range 1 12 - 80 MHz

Voltage scaling Range 2 12 - 26

fVCO_OUT PLL VCO output Voltage scaling Range 1 96 - 344 MHz

Voltage scaling Range 2 96 - 128

tLOCK PLL lock time - - 15 40 μs

Jitter RMS cycle-to-cycle jitter System clock 80 MHz -40-

±ps

RMS period jitter - 30 -

IDD(PLL) PLL power consumption on

VDD(1)

VCO freq = 96 MHz - 200 260

μAVCO freq = 192 MHz - 300 380

VCO freq = 344 MHz - 520 650

1. Guaranteed by design.

2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared

between the 2 PLLs.

DS11913 Rev 5 133/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

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6.3.10 Flash memory characteristics

Table 53. Flash memory characteristics(1)

1. Guaranteed by design.

Symbol Parameter Conditions Typ Max Unit

tprog 64-bit programming time - 81.69 90.76 µs

tprog_row one row (32 double

word) programming time

normal programming 2.61 2.90

fast programming 1.91 2.12

tprog_page one page (2 Kbyte)

programming time

normal programming 20.91 23.24

fast programming 15.29 16.98

tERASE Page (2 KB) erase time - 22.02 24.47

tprog_bank one bank (512 Kbyte)

programming time

normal programming 5.35 5.95 s

fast programming 3.91 4.35

tME Mass erase time

(one or two banks) - 22.13 24.59 ms

IDD

Average consumption

from VDD

Write mode 3.4 -

Erase mode 3.4 -

Maximum current (peak) Write mode 7 (for 2 μs) -

Erase mode 7 (for 41 μs) -

Table 54. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1)

1. Guaranteed by characterization results.

Unit

NEND Endurance TA = –40 to +105 °C 10 kcycles

tRET Data retention

1 kcycle(2) at TA = 85 °C

2. Cycling performed over the whole temperature range.

Years

1 kcycle(2) at TA = 105 °C 15

1 kcycle(2) at TA = 125 °C 7

10 kcycles(2) at TA = 55 °C 30

10 kcycles(2) at TA = 85 °C 15

10 kcycles(2) at TA = 105 °C 10

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

134/210 DS11913 Rev 5

6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

the device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

•Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

•FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and

VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 55. They are based on the EMS levels and classes

defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

•Corrupted program counter

•Unexpected reset

•Critical Data corruption (control registers...)

Table 55. EMS characteristics

Symbol Parameter Conditions Level/

Class

VFESD Voltage limits to be applied on any I/O pin

to induce a functional disturbance

VDD = 3.3 V, TA = +25 °C,

fHCLK = 80 MHz,

conforming to IEC 61000-4-2

VEFTB

Fast transient voltage burst limits to be

applied through 100 pF on VDD and VSS

pins to induce a functional disturbance

VDD = 3.3 V, TA = +25 °C,

fHCLK = 80 MHz,

conforming to IEC 61000-4-4

DS11913 Rev 5 135/210

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Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the ANSI/JEDEC standard.

Table 56. EMI characteristics

Symbol Parameter Conditions Monitored

frequency band

Max vs.

[fHSE/fHCLK]Unit

8 MHz/ 80 MHz

SEMI Peak level

VDD = 3.6 V, TA = 25 °C,

LQFP100 package

compliant with IEC

61967-2

0.1 MHz to 30 MHz -8

dBµV

30 MHz to 130 MHz 2

130 MHz to 1 GHz 5

1 GHz to 2 GHz 8

EMI Level 2.5 -

Table 57. ESD absolute maximum ratings

Symbol Ratings Conditions Class Maximum

value(1)

1. Guaranteed by characterization results.

Unit

VESD(HBM) Electrostatic discharge

voltage (human body model)

TA = +25 °C, conforming

to ANSI/ESDA/JEDEC

JS-001

2 2000

VESD(CDM)

Electrostatic discharge

voltage (charge device

model)

TA = +25 °C,

conforming to ANSI/ESD

STM5.3.1

C3 250

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Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

•A supply overvoltage is applied to each power supply pin.

•A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or

above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal

product operation. However, in order to give an indication of the robustness of the

microcontroller in cases when abnormal injection accidentally happens, susceptibility tests

are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher

than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out

of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or

oscillator frequency deviation).

The characterization results are given in Table 59.

Negative induced leakage current is caused by negative injection and positive induced

leakage current is caused by positive injection.

Table 58. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +105 °C conforming to JESD78A II

Table 59. I/O current injection susceptibility(1)

1. Guaranteed by characterization results.

Symbol Description

Functional

susceptibility

Unit

Negative

injection

Positive

injection

IINJ

Injected current on all pins except PA4, PA5, PE8, PE9,

PE10, PE11, PE12 -5 N/A(2)

2. Injection is not possible.

Injected current on PE8, PE9, PE10, PE11, PE12 -0 N/A(2)

Injected current on PA4, PA5 pins -5 0

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6.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 60 are derived from tests

performed under the conditions summarized in Table 22: General operating conditions. All

I/Os are designed as CMOS- and TTL-compliant.

Table 60. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(1)

I/O input low level

voltage 1.62 V<VDDIOx<3.6 V - - 0.3xVDDIOx (2)

I/O input low level

voltage 1.62 V<VDDIOx<3.6 V - - 0.39xVDDIOx-0.06 (3)

I/O input low level

voltage 1.08 V<VDDIOx<1.62 V - - 0.43xVDDIOx-0.1 (3)

VIH(1)

I/O input high level

voltage 1.62 V<VDDIOx<3.6 V 0.7xVDDIOx (2) --

I/O input high level

voltage 1.62 V<VDDIOx<3.6 V 0.49xVDDIOX+0.26 (3) --

I/O input high level

voltage 1.08 V<VDDIOx<1.62 V 0.61xVDDIOX+0.05 (3) --

Vhys(3) TT_xx, FT_xxx and

NRST I/O input

hysteresis

1.62 V<VDDIOx<3.6 V - 200 - mV

Ilkg

FT_xx input leakage

current(3)(4)

VIN ≤

Max(VDDXXX)(5)(6) --±100

Max(VDDXXX) ≤ VIN ≤

Max(VDDXXX)+1 V(5)(6) --650

(3)(7)

Max(VDDXXX)+1 V <

VIN ≤ 5.5 V(3)(6) - - 200(7)

FT_u and PC3 I/O

VIN ≤ Max(VDDXXX)

(5)(6) --±150

Max(VDDXXX) ≤ VIN ≤

Max(VDDXXX)+1 V(5)(6) - - 2500(3)

Max(VDDXXX)+1 V <

VIN ≤ 5.5 V(5)(6) - - 250

TT_xx input leakage

current

VIN ≤ Max(VDDXXX)(7) --±150

Max(VDDXXX) ≤ VIN <

3.6 V(7) - - 2000(3)

RPU Weak pull-up

equivalent resistor (8) VIN = VSS 25 40 55 kΩ

RPD Weak pull-down

equivalent resistor(8) VIN = VDDIOx 25 40 55 kΩ

CIO I/O pin capacitance - - 5 - pF

25 05 V‘I-Vih a“ [0 except BOOTD ,‘ —w spec 30% —mn spec 70% —vH spec m / —vm spec m —va Me ’ —Vvh,rule 1 5 2.5 3 3'5

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All I/Os are CMOS- and TTL-compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 26 for standard I/Os, and in Figure 26 for

5 V tolerant I/Os.

Figure 26. I/O input characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or

source up to ± 20 mA (with a relaxed VOL/VOH).

GPIOs PC13, PC14 and PC15 are supplied through the power switch, limiting source

capability up to 3 mA only.

1. Refer to Figure 26: I/O input characteristics.

2. Tested in production.

3. Guaranteed by design.

4. All FT_xx IO except FT_u and PC3 I/O.

5. Max(VDDXXX) is the maximum value of all the I/O supplies.

6. To sustain a voltage higher than Min(VDD, VDDA, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must be

disabled.

7. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:

ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] ₓ Ilkg(Max).

8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

MSv37613V1

Tested in production CMOS requirement Vih min = 0.7xVDDIOx

Based on simulation Vih min = 0.61xV

DDIOx

+0.05 for 1.08<V

DDIOx

<1.62 or 0.49xV

DDIOx

+0.26 for V

DDIOx

>1.62

Based on simulation Vil max =0.43xV

DDIOx

-0.1 for 1.08<V

DDIOx

<1.62 or 0.39xV

DDIOx

-0.06 for V

DDIOx

>1.62

Tested in production CMOS requirement Vil max = 0.3xVdd

TTL requirement Vih min = 2V

TTL requirement Vil max = 0.8V

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STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

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In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 6.2:

•The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum

consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating

ΣIVDD (see Table 19: Voltage characteristics).

•The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of

the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see

Table 19: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature and supply voltage conditions summarized in

Table 22: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT or TT

unless otherwise specified).

Table 61. Output voltage characteristics(1)

Symbol Parameter Conditions Min Max Unit

VOL Output low level voltage for an I/O pin CMOS port(2)

|IIO| = 8 mA(3)

VDDIOx ≥ 2.7 V

-0.4

VOH Output high level voltage for an I/O pin VDDIOx-0.4 -

VOL(4) Output low level voltage for an I/O pin TTL port(2)

|IIO| = 8 mA(5)

VDDIOx ≥ 2.7 V

-0.4

VOH(4) Output high level voltage for an I/O pin 2.4 -

VOL(4) Output low level voltage for an I/O pin PC13, PC14 and PC15

|IIO| = 3 mA

VDDIOx ≥ 2.7 V

-0.07

VOH(4) Output high level voltage for an I/O pin VDDIOx-0.35 -

VOL(4) Output low level voltage for an I/O pin |IIO| = 20 mA(5)

VDDIOx ≥ 2.7 V

-1.3

VOH(4) Output high level voltage for an I/O pin VDDIOx-1.3 -

VOL(4) Output low level voltage for an I/O pin |IIO| = 4 mA(3)

VDDIOx ≥ 1.62 V

-0.45

VOH(4) Output high level voltage for an I/O pin VDDIOx-0.45 -

VOL(4) Output low level voltage for an I/O pin |IIO| = 2 mA

1.62 V ≥ VDDIOx ≥ 1.08 V

- 0.35ₓVDDIOx

VOH(4) Output high level voltage for an I/O pin 0.65ₓVDDIOx -

VOLFM+

(4)

Output low level voltage for an FT I/O

pin in FM+ mode (FT I/O with "f"

option)

|IIO| = 20 mA

VDDIOx ≥ 2.7 V -0.4

|IIO| = 10 mA

VDDIOx ≥ 1.62 V -0.4

|IIO| = 2 mA

1.62 V ≥ VDDIOx ≥ 1.08 V -0.4

1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19:

Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

respect the absolute maximum ratings ΣIIO.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. PC13, PC14 and PC15 are tested/characterized at their maximum current of 3 mA.

4. Guaranteed by design.

5. Not applicable to PC13, PC14 and PC15.

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Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 27 and

Table 62, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under

the ambient temperature and supply voltage conditions summarized in Table 22: General

operating conditions.

Table 62. I/O AC characteristics(1)(2)

Speed Symbol Parameter Conditions Min Max Unit

Fmax Maximum frequency

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5

MHz

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 1

C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1

C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 10

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 1.5

C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1

Tr/Tf Output rise and fall time

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 52

C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 140

C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 17

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37

C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 110

Fmax Maximum frequency

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25

MHz

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 10

C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 1

C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 50

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 15

C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 1

Tr/Tf Output rise and fall time

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 9

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 16

C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 40

C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 4.5

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 9

C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 21

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Fmax Maximum frequency

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50

MHz

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25

C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5

C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3)

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.5

C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 5

Tr/Tf Output rise and fall time

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5.8

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 11

C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 28

C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 2.5

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 5

C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 12

Fmax Maximum frequency

C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 120(3)

MHz

C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 50

C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 10

C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 180(3)

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 75

C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 10

Tr/Tf Output rise and fall time

C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 3.3

nsC=30 pF, 1.62 V≤VDDIOx≤2.7 V - 6

C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 16

Fm+ Fmax Maximum frequency C=50 pF, 1.6 V≤VDDIOx≤3.6 V -1MHz

Tf Output fall time(4) -5ns

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.

Refer to the RM0394 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.

4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.

Table 62. I/O AC characteristics(1)(2) (continued)

Speed Symbol Parameter Conditions Min Max Unit

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Figure 27. I/O AC characteristics definition(1)

1. Refer to Table 62: I/O AC characteristics.

6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-

up resistor, RPU.

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature and supply voltage conditions summarized in

Table 22: General operating conditions.

MS32132V2

10%

50%

90% 10%

50%

90%

Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)

when loaded by the specified capacitance.

r(IO)out

tf(IO)out

Table 63. NRST pin characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) NRST input low level

voltage ---0.3ₓV

DDIOx

VIH(NRST) NRST input high level

voltage -0.7ₓV

DDIOx --

Vhys(NRST) NRST Schmitt trigger

voltage hysteresis --200-mV

RPU Weak pull-up

equivalent resistor(2) VIN = VSS 25 40 55 kΩ

VF(NRST) NRST input filtered

pulse ---70ns

VNF(NRST) NRST input not filtered

pulse 1.71 V ≤ VDD ≤ 3.6 V 350 - - ns

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series

resistance is minimal (~10% order).

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Figure 28. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 63: NRST pin characteristics. Otherwise the reset is not taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

6.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is

detected by the event controller.

6.3.17 Analog switches booster

MS19878V3

RPU

VDD

Internal reset

External

reset circuit(1)

NRST(2)

Filter

0.1 μF

Table 64. EXTI Input Characteristics(1)

1. Guaranteed by design.

Symbol Parameter Conditions Min Typ Max Unit

PLEC Pulse length to event

controller -20--ns

Table 65. Analog switches booster characteristics(1)

1. Guaranteed by design.

Symbol Parameter Min Typ Max Unit

VDD Supply voltage 1.62 - 3.6 V

tSU(BOOST) Booster startup time - - 240 µs

IDD(BOOST)

Booster consumption for

1.62 V ≤ VDD ≤ 2.0 V --250

µA

Booster consumption for

2.0 V ≤ VDD ≤ 2.7 V --500

Booster consumption for

2.7 V ≤ VDD ≤ 3.6 V --900

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6.3.18 Analog-to-Digital converter characteristics

Unless otherwise specified, the parameters given in Tabl e 66 are preliminary values derived

from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage

conditions summarized in Table 22: General operating conditions.

Note: It is recommended to perform a calibration after each power-up.

Table 66. ADC characteristics(1) (2)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.62 - 3.6 V

VREF+ Positive reference voltage VDDA ≥ 2 V 2 - VDDA V

VDDA < 2 V VDDA V

VREF- Negative reference

voltage -V

SSA V

fADC ADC clock frequency Range 1 0.14 - 80 MHz

Range 2 0.14 - 26

Sampling rate for FAST

channels

Resolution = 12 bits - - 5.33

Msps

Resolution = 10 bits - - 6.15

Resolution = 8 bits - - 7.27

Resolution = 6 bits - - 8.88

Sampling rate for SLOW

channels

Resolution = 12 bits - - 4.21

Resolution = 10 bits - - 4.71

Resolution = 8 bits - - 5.33

Resolution = 6 bits - - 6.15

fTRIG External trigger frequency

fADC = 80 MHz

Resolution = 12 bits - - 5.33 MHz

Resolution = 12 bits - - 15 1/fADC

VCMIN Input common mode Differential mode

(VREF++

VREF-)/2

- 0.18

(VREF++

VREF-)/2

(VREF++

VREF-)/2

+ 0.18

VAIN (3) Conversion voltage

range(2) -0-V

REF+ V

RAIN External input impedance - - - 50 kΩ

CADC Internal sample and hold

capacitor --5-pF

tSTAB Power-up time - 1 conversion

cycle

tCAL Calibration time fADC = 80 MHz 1.45 µs

-1161/f

ADC

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The maximum value of RAIN can be found in Table 67: Maximum ADC RAIN.

tLATR

Trigger conversion

latency Regular and

injected channels without

conversion abort

CKMODE = 00 1.5 2 2.5

1/fADC

CKMODE = 01 - - 2.0

CKMODE = 10 - - 2.25

CKMODE = 11 - - 2.125

tLATRINJ

Trigger conversion

latency Injected channels

aborting a regular

conversion

CKMODE = 00 2.5 3 3.5

1/fADC

CKMODE = 01 - - 3.0

CKMODE = 10 - - 3.25

CKMODE = 11 - - 3.125

tsSampling time fADC = 80 MHz 0.03125 - 8.00625 µs

- 2.5 - 640.5 1/fADC

tADCVREG_STUP

ADC voltage regulator

start-up time ---20

µs

tCONV Total conversion time

(including sampling time)

fADC = 80 MHz

Resolution = 12 bits 0.1875 - 8.1625 µs

Resolution = 12 bits

ts + 12.5 cycles for

successive approximation

= 15 to 653

1/fADC

IDDA(ADC) ADC consumption from

the VDDA supply

fs = 5 Msps - 730 830

µAfs = 1 Msps - 160 220

fs = 10 ksps - 16 50

IDDV_S(ADC)

ADC consumption from

the VREF+ single ended

mode

fs = 5 Msps - 130 160

µAfs = 1 Msps - 30 40

fs = 10 ksps - 0.6 2

IDDV_D(ADC)

ADC consumption from

the VREF+ differential

mode

fs = 5 Msps - 260 310

µAfs = 1 Msps - 60 70

fs = 10 ksps - 1.3 3

1. Guaranteed by design

2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.

3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.

Refer to Section 4: Pinouts and pin description for further details.

Table 66. ADC characteristics(1) (2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

AIN

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Table 67. Maximum ADC RAIN(1)(2)

Resolution Sampling cycle

@80 MHz

Sampling time [ns]

@80 MHz

RAIN max (Ω)

Fast channels(3) Slow channels(4)

12 bits

2.5 31.25 100 N/A

6.5 81.25 330 100

12.5 156.25 680 470

24.5 306.25 1500 1200

47.5 593.75 2200 1800

92.5 1156.25 4700 3900

247.5 3093.75 12000 10000

640.5 8006.75 39000 33000

10 bits

2.5 31.25 120 N/A

6.5 81.25 390 180

12.5 156.25 820 560

24.5 306.25 1500 1200

47.5 593.75 2200 1800

92.5 1156.25 5600 4700

247.5 3093.75 12000 10000

640.5 8006.75 47000 39000

8 bits

2.5 31.25 180 N/A

6.5 81.25 470 270

12.5 156.25 1000 680

24.5 306.25 1800 1500

47.5 593.75 2700 2200

92.5 1156.25 6800 5600

247.5 3093.75 15000 12000

640.5 8006.75 50000 50000

6 bits

2.5 31.25 220 N/A

6.5 81.25 560 330

12.5 156.25 1200 1000

24.5 306.25 2700 2200

47.5 593.75 3900 3300

92.5 1156.25 8200 6800

247.5 3093.75 18000 15000

640.5 8006.75 50000 50000

1. Guaranteed by design.

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2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.

3. Fast channels are: PC0, PC1, PC2, PC3, PA0, PA1.

4. Slow channels are: all ADC inputs except the fast channels.

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Table 68. ADC accuracy - limited test conditions 1(1)(2)(3)

Sym-

bol Parameter Conditions(4) Min Typ Max Unit

Total

unadjusted

error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

VDDA = VREF+ = 3 V,

TA = 25 °C

Single

ended

Fast channel (max speed) - 4 5

LSB

Slow channel (max speed) - 4 5

Differential Fast channel (max speed) - 3.5 4.5

Slow channel (max speed) - 3.5 4.5

EO Offset

error

Single

ended

Fast channel (max speed) - 1 2.5

Slow channel (max speed) - 1 2.5

Differential Fast channel (max speed) - 1.5 2.5

Slow channel (max speed) - 1.5 2.5

EG Gain error

Single

ended

Fast channel (max speed) - 2.5 4.5

Slow channel (max speed) - 2.5 4.5

Differential Fast channel (max speed) - 2.5 3.5

Slow channel (max speed) - 2.5 3.5

Differential

linearity

error

Single

ended

Fast channel (max speed) - 1 1.5

Slow channel (max speed) - 1 1.5

Differential Fast channel (max speed) - 1 1.2

Slow channel (max speed) - 1 1.2

Integral

linearity

error

Single

ended

Fast channel (max speed) - 1.5 2.5

Slow channel (max speed) - 1.5 2.5

Differential Fast channel (max speed) - 1 2

Slow channel (max speed) - 1 2

ENOB

Effective

number of

bits

Single

ended

Fast channel (max speed) 10.4 10.5 -

bits

Slow channel (max speed) 10.4 10.5 -

Differential Fast channel (max speed) 10.8 10.9 -

Slow channel (max speed) 10.8 10.9 -

SINAD

Signal-to-

noise and

distortion

ratio

Single

ended

Fast channel (max speed) 64.4 65 -

Slow channel (max speed) 64.4 65 -

Differential Fast channel (max speed) 66.8 67.4 -

Slow channel (max speed) 66.8 67.4 -

SNR Signal-to-

noise ratio

Single

ended

Fast channel (max speed) 65 66 -

Slow channel (max speed) 65 66 -

Differential Fast channel (max speed) 67 68 -

Slow channel (max speed) 67 68 -

DS11913 Rev 5 149/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

THD

Total

harmonic

distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

VDDA = VREF+ = 3 V,

TA = 25 °C

Single

ended

Fast channel (max speed) - -74 -73

Slow channel (max speed) - -74 -73

Differential Fast channel (max speed) - -79 -76

Slow channel (max speed) - -79 -76

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this

significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.

Table 68. ADC accuracy - limited test conditions 1(1)(2)(3) (continued)

Sym-

bol Parameter Conditions(4) Min Typ Max Unit

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

150/210 DS11913 Rev 5

Table 69. ADC accuracy - limited test conditions 2(1)(2)(3)

Sym-

bol Parameter Conditions(4) Min Typ Max Unit

Total

unadjusted

error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ VDDA

Single

ended

Fast channel (max speed) - 4 6.5

LSB

Slow channel (max speed) - 4 6.5

Differential Fast channel (max speed) - 3.5 5.5

Slow channel (max speed) - 3.5 5.5

EO Offset

error

Single

ended

Fast channel (max speed) - 1 4.5

Slow channel (max speed) - 1 5

Differential Fast channel (max speed) - 1.5 3

Slow channel (max speed) - 1.5 3

EG Gain error

Single

ended

Fast channel (max speed) - 2.5 6

Slow channel (max speed) - 2.5 6

Differential Fast channel (max speed) - 2.5 3.5

Slow channel (max speed) - 2.5 3.5

Differential

linearity

error

Single

ended

Fast channel (max speed) - 1 1.5

Slow channel (max speed) - 1 1.5

Differential Fast channel (max speed) - 1 1.2

Slow channel (max speed) - 1 1.2

Integral

linearity

error

Single

ended

Fast channel (max speed) - 1.5 3.5

Slow channel (max speed) - 1.5 3.5

Differential Fast channel (max speed) - 1 3

Slow channel (max speed) - 1 2.5

ENOB

Effective

number of

bits

Single

ended

Fast channel (max speed) 10 10.5 -

bits

Slow channel (max speed) 10 10.5 -

Differential Fast channel (max speed) 10.7 10.9 -

Slow channel (max speed) 10.7 10.9 -

SINAD

Signal-to-

noise and

distortion

ratio

Single

ended

Fast channel (max speed) 62 65 -

Slow channel (max speed) 62 65 -

Differential Fast channel (max speed) 66 67.4 -

Slow channel (max speed) 66 67.4 -

SNR Signal-to-

noise ratio

Single

ended

Fast channel (max speed) 64 66 -

Slow channel (max speed) 64 66 -

Differential Fast channel (max speed) 66.5 68 -

Slow channel (max speed) 66.5 68 -

DS11913 Rev 5 151/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

THD

Total

harmonic

distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ VDDA

Single

ended

Fast channel (max speed) - -74 -65

Slow channel (max speed) - -74 -67

Differential Fast channel (max speed) - -79 -70

Slow channel (max speed) - -79 -71

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this

significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.

Table 69. ADC accuracy - limited test conditions 2(1)(2)(3) (continued)

Sym-

bol Parameter Conditions(4) Min Typ Max Unit

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

152/210 DS11913 Rev 5

Table 70. ADC accuracy - limited test conditions 3(1)(2)(3)

Sym-

bol Parameter Conditions(4) Min Typ Max Unit

Total

unadjusted

error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ VDDA = VREF+ ≤

3.6 V,

Voltage scaling Range 1

Single

ended

Fast channel (max speed) - 5.5 7.5

LSB

Slow channel (max speed) - 4.5 6.5

Differential Fast channel (max speed) - 4.5 7.5

Slow channel (max speed) - 4.5 5.5

EO Offset

error

Single

ended

Fast channel (max speed) - 2 5

Slow channel (max speed) - 2.5 5

Differential Fast channel (max speed) - 2 3.5

Slow channel (max speed) - 2.5 3

EG Gain error

Single

ended

Fast channel (max speed) - 4.5 7

Slow channel (max speed) - 3.5 6

Differential Fast channel (max speed) - 3.5 4

Slow channel (max speed) - 3.5 5

Differential

linearity

error

Single

ended

Fast channel (max speed) - 1.2 1.5

Slow channel (max speed) - 1.2 1.5

Differential Fast channel (max speed) - 1 1.2

Slow channel (max speed) - 1 1.2

Integral

linearity

error

Single

ended

Fast channel (max speed) - 3 3.5

Slow channel (max speed) - 2.5 3.5

Differential Fast channel (max speed) - 2 2.5

Slow channel (max speed) - 2 2.5

ENOB

Effective

number of

bits

Single

ended

Fast channel (max speed) 10 10.4 -

bits

Slow channel (max speed) 10 10.4 -

Differential Fast channel (max speed) 10.6 10.7 -

Slow channel (max speed) 10.6 10.7 -

SINAD

Signal-to-

noise and

distortion

ratio

Single

ended

Fast channel (max speed) 62 64 -

Slow channel (max speed) 62 64 -

Differential Fast channel (max speed) 65 66 -

Slow channel (max speed) 65 66 -

SNR Signal-to-

noise ratio

Single

ended

Fast channel (max speed) 63 65 -

Slow channel (max speed) 63 65 -

Differential Fast channel (max speed) 66 67 -

Slow channel (max speed) 66 67 -

DS11913 Rev 5 153/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

THD

Total

harmonic

distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ VDDA = VREF+ ≤

3.6 V,

Voltage scaling Range 1

Single

ended

Fast channel (max speed) - -69 -67

Slow channel (max speed) - -71 -67

Differential

Fast channel (max speed) - -72 -71

Slow channel (max speed) - -72 -71

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this

significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.

Table 70. ADC accuracy - limited test conditions 3(1)(2)(3) (continued)

Sym-

bol Parameter Conditions(4) Min Typ Max Unit

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

154/210 DS11913 Rev 5

Table 71. ADC accuracy - limited test conditions 4(1)(2)(3)

Sym-

bol Parameter Conditions(4) Min Typ Max Unit

Total

unadjusted

error

ADC clock frequency ≤

26 MHz,

1.65 V ≤ VDDA = VREF+ ≤

3.6 V,

Voltage scaling Range 2

Single

ended

Fast channel (max speed) - 5 5.4

LSB

Slow channel (max speed) - 4 5

Differential Fast channel (max speed) - 4 5

Slow channel (max speed) - 3.5 4.5

EO Offset

error

Single

ended

Fast channel (max speed) - 2 4

Slow channel (max speed) - 2 4

Differential Fast channel (max speed) - 2 3.5

Slow channel (max speed) - 2 3.5

EG Gain error

Single

ended

Fast channel (max speed) - 4 4.5

Slow channel (max speed) - 4 4.5

Differential Fast channel (max speed) - 3 4

Slow channel (max speed) - 3 4

Differential

linearity

error

Single

ended

Fast channel (max speed) - 1 1.5

Slow channel (max speed) - 1 1.5

Differential Fast channel (max speed) - 1 1.2

Slow channel (max speed) - 1 1.2

Integral

linearity

error

Single

ended

Fast channel (max speed) - 2.5 3

Slow channel (max speed) - 2.5 3

Differential Fast channel (max speed) - 2 2.5

Slow channel (max speed) - 2 2.5

ENOB

Effective

number of

bits

Single

ended

Fast channel (max speed) 10.2 10.5 -

bits

Slow channel (max speed) 10.2 10.5 -

Differential Fast channel (max speed) 10.6 10.7 -

Slow channel (max speed) 10.6 10.7 -

SINAD

Signal-to-

noise and

distortion

ratio

Single

ended

Fast channel (max speed) 63 65 -

Slow channel (max speed) 63 65 -

Differential Fast channel (max speed) 65 66 -

Slow channel (max speed) 65 66 -

SNR Signal-to-

noise ratio

Single

ended

Fast channel (max speed) 64 65 -

Slow channel (max speed) 64 65 -

Differential Fast channel (max speed) 66 67 -

Slow channel (max speed) 66 67 -

DS11913 Rev 5 155/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

Figure 29. ADC accuracy characteristics

THD

Total

harmonic

distortion

ADC clock frequency ≤

26 MHz,

1.65 V ≤ VDDA = VREF+ ≤

3.6 V,

Voltage scaling Range 2

Single

ended

Fast channel (max speed) - -71 -69

Slow channel (max speed) - -71 -69

Differential Fast channel (max speed) - -73 -72

Slow channel (max speed) - -73 -72

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this

significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.

Table 71. ADC accuracy - limited test conditions 4(1)(2)(3) (continued)

Sym-

bol Parameter Conditions(4) Min Typ Max Unit

ET = total unajusted error: maximum deviation

between the actual and ideal transfer curves.

EO = offset error: maximum deviation

between the first actual transition and

the first ideal one.

EG = gain error: deviation between the last

ideal transition and the last actual one.

ED = differential linearity error: maximum

deviation between actual steps and the ideal ones.

EL = integral linearity error: maximum deviation

between any actual transition and the end point

correlation line.

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

4095

4094

4093

023456

17 4093 4094 4095 4096 VDDA

VSSA

1 LSB IDEAL

(1)

(3)

(2)

MS19880V2

F‘I g LJ -I|—l>|i4[>1—l II A HP

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

156/210 DS11913 Rev 5

Figure 30. Typical connection diagram using the ADC

1. Refer to Table 66: ADC characteristics for the values of RAIN and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (refer to Table 60: I/O static characteristics for the value of the pad capacitance). A high

Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced.

3. Refer to Table 60: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 16: Power supply

scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as

close as possible to the chip.

MS33900V5

Sample and hold ADC converter

12-bit

converter

Cparasitic(2) Ilkg (3)

VTCADC

VDDA

RAIN(1)

VAIN

AINx RADC

DS11913 Rev 5 157/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

6.3.19 Digital-to-Analog converter characteristics

Table 72. DAC characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage for

DAC ON

DAC output buffer OFF (no resistive

load on DAC1_OUT1 pin or internal

connection)

1.71 -

3.6

Other modes 1.80 -

VREF+ Positive reference voltage

DAC output buffer OFF (no resistive

load on DAC1_OUT1 pin or internal

connection)

1.71 -

VDDA

Other modes 1.80 -

VREF- Negative reference

voltage -V

SSA

RLResistive load DAC output

buffer ON

connected to VSSA 5- -

kΩ

connected to VDDA 25 - -

ROOutput Impedance DAC output buffer OFF 9.6 11.7 13.8 kΩ

RBON

Output impedance sample

and hold mode, output

buffer ON

VDD = 2.7 V - - 2

kΩ

VDD = 2.0 V - - 3.5

RBOFF

Output impedance sample

and hold mode, output

buffer OFF

VDD = 2.7 V - - 16.5

kΩ

VDD = 2.0 V - - 18.0

CLCapacitive load DAC output buffer ON - - 50 pF

CSH Sample and hold mode - 0.1 1 µF

VDAC_OUT Voltage on DAC1_OUT1

output

DAC output buffer ON 0.2 - VREF+

– 0.2 V

DAC output buffer OFF 0 - VREF+

tSETTLING

Settling time (full scale: for

a 12-bit code transition

between the lowest and

the highest input codes

when DAC1_OUT1

reaches final value

±0.5LSB, ±1 LSB, ±2 LSB,

±4 LSB, ±8 LSB)

Normal mode

DAC output

buffer ON

CL ≤ 50 pF,

RL ≥ 5 kΩ

±0.5 LSB - 1.7 3

µs

±1 LSB - 1.6 2.9

±2 LSB - 1.55 2.85

±4 LSB - 1.48 2.8

±8 LSB - 1.4 2.75

Normal mode DAC output buffer

OFF, ±1LSB, CL = 10 pF -22.5

tWAKEUP(2)

Wakeup time from off state

(setting the ENx bit in the

DAC Control register) until

final value ±1 LSB

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ -4.27.5

µs

Normal mode DAC output buffer

OFF, CL ≤ 10 pF -2 5

PSRR VDDA supply rejection ratio Normal mode DAC output buffer ON

CL ≤ 50 pF, RL = 5 kΩ, DC --80-28dB

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

158/210 DS11913 Rev 5

TW_to_W

Minimal time between two

consecutive writes into the

DAC_DORx register to

guarantee a correct

DAC1_OUT1 for a small

variation of the input code

(1 LSB)

DAC_MCR:MODEx[2:0] =

000 or 001

DAC_MCR:MODEx[2:0] =

010 or 011

CL ≤ 50 pF, RL ≥ 5 kΩ

CL ≤ 10 pF

1.4

--µs

tSAMP

Sampling time in sample

and hold mode (code

transition between the

lowest input code and the

highest input code when

DAC1_OUT1 reaches final

value ±1LSB)

DAC1_OUT1

pin connected

DAC output buffer

ON, CSH = 100 nF -0.73.5

DAC output buffer

OFF, CSH = 100 nF -10.5 18

DAC1_OUT1

pin not

connected

(internal

connection

only)

DAC output buffer

OFF -23.5µs

Ileak Output leakage current Sample and hold mode,

DAC1_OUT1 pin connected ---

(3) nA

CIint Internal sample and hold

capacitor - 5.2 7 8.8 pF

tTRIM Middle code offset trim

time DAC output buffer ON 50 - - µs

Voffset Middle code offset for 1

trim code step

VREF+ = 3.6 V - 1500 - µV

VREF+ = 1.8 V - 750 -

IDDA(DAC) DAC consumption from

VDDA

DAC output

buffer ON

No load, middle

code (0x800) - 315 500

µA

No load, worst code

(0xF1C) - 450 670

DAC output

buffer OFF

No load, middle

code (0x800) --0.2

Sample and hold mode, CSH =

100 nF -

315 ₓ

Ton/(Ton

+Toff)

(4)

670 ₓ

Ton/(Ton

+Toff)

(4)

Table 72. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

DS11913 Rev 5 159/210

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182

Figure 31. 12-bit buffered / non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly

without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

IDDV(DAC) DAC consumption from

VREF+

DAC output

buffer ON

No load, middle

code (0x800) - 185 240

µA

No load, worst code

(0xF1C) - 340 400

DAC output

buffer OFF

No load, middle

code (0x800) - 155 205

Sample and hold mode, buffer ON,

CSH = 100 nF, worst case -

185 ₓ

Ton/(Ton

+Toff)

(4)

400 ₓ

Ton/(Ton

+Toff)

(4)

Sample and hold mode, buffer OFF,

CSH = 100 nF, worst case -

155 ₓ

Ton/(Ton

+Toff)

(4)

205 ₓ

Ton/(Ton

+Toff)

(4)

1. Guaranteed by design.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

3. Refer to Table 60: I/O static characteristics.

4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0394 reference manual for more details.

Table 72. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

(1)

Buffer

12-bit

digital to

analog

converter

Buffered/non-buffered DAC

DACx_OUT

LOAD

ai17157d

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

160/210 DS11913 Rev 5

. Table 73. DAC accuracy(1)

Symbol Parameter Conditions Min Typ Max Unit

DNL Differential non

linearity (2)

DAC output buffer ON - - ±2

LSB

DAC output buffer OFF - - ±2

- monotonicity 10 bits guaranteed

INL Integral non

linearity(3)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ --±4

DAC output buffer OFF

CL ≤ 50 pF, no RL --±4

Offset Offset error at

code 0x800(3)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

VREF+ = 3.6 V - - ±12

VREF+ = 1.8 V - - ±25

DAC output buffer OFF

CL ≤ 50 pF, no RL --±8

Offset1 Offset error at

code 0x001(4) DAC output buffer OFF

CL ≤ 50 pF, no RL --±5

OffsetCal

Offset Error at

code 0x800

after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

VREF+ = 3.6 V - - ±5

VREF+ = 1.8 V - - ±7

Gain Gain error(5)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ --±0.5

DAC output buffer OFF

CL ≤ 50 pF, no RL --±0.5

TUE

Total

unadjusted

error

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ --±30

LSB

DAC output buffer OFF

CL ≤ 50 pF, no RL --±12

TUECal

Total

unadjusted

error after

calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ --±23LSB

SNR Signal-to-noise

ratio

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

1 kHz, BW 500 kHz

-71.2-

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

BW 500 kHz

-71.6-

THD Total harmonic

distortion

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz --78-

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz --79-

DS11913 Rev 5 161/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

SINAD

Signal-to-noise

and distortion

ratio

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz -70.4-

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz -71-

ENOB Effective

number of bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz -11.4-

bits

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz -11.5-

1. Guaranteed by design.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

4. Difference between the value measured at Code (0x001) and the ideal value.

5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when

buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.

Table 73. DAC accuracy(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

162/210 DS11913 Rev 5

6.3.20 Voltage reference buffer characteristics

Table 74. VREFBUF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply

voltage

Normal mode VRS = 0 2.4 - 3.6

VRS = 1 2.8 - 3.6

Degraded mode(2) VRS = 0 1.65 - 2.4

VRS = 1 1.65 - 2.8

VREFBUF_

OUT

Voltage

reference

output

Normal mode VRS = 0 2.046(3) 2.048 2.049(3)

VRS = 1 2.498(3) 2.5 2.502(3)

Degraded mode(2) VRS = 0 VDDA-150 mV - VDDA

VRS = 1 VDDA-150 mV - VDDA

TRIM Trim step

resolution ---±0.05±0.1%

CL Load capacitor - - 0.5 1 1.5 µF

esr

Equivalent

Serial Resistor

of Cload

----2Ω

Iload Static load

current ----4mA

Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V Iload = 500 µA - 200 1000 ppm/V

Iload = 4 mA - 100 500

Iload_reg Load

regulation 500 μA ≤ Iload ≤4 mA Normal mode - 50 500 ppm/mA

TCoeff Temperature

coefficient

-40 °C < TJ < +125 °C - -

Tcoeff_

vrefint +

50 ppm/ °C

0 °C < TJ < +50 °C - -

Tcoeff_

vrefint +

PSRR Power supply

rejection

DC 40 60 - dB

100 kHz 25 40 -

tSTART Start-up time

CL = 0.5 µF(4) - 300 350

µsCL = 1.1 µF(4) - 500 650

CL = 1.5 µF(4) - 650 800

IINRUSH

Control of

maximum DC

current drive

on VREFBUF_

OUT during

start-up phase

(5)

---8-mA

DS11913 Rev 5 163/210

STM32L462CE STM32L462RE STM32L462VE Electrical characteristics

182

IDDA(VREF

BUF)

VREFBUF

consumption

from VDDA

Iload = 0 µA - 16 25

µAIload = 500 µA - 18 30

Iload = 4 mA - 35 50

1. Guaranteed by design, unless otherwise specified.

2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which follows (VDDA - drop

voltage).

3. Guaranteed by test in production.

4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.

5. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in

the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.

Table 74. VREFBUF characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

164/210 DS11913 Rev 5

6.3.21 Comparator characteristics

Table 75. COMP characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.62 - 3.6

VVIN Comparator input voltage

range -0-V

DDA

VBG(2) Scaler input voltage - VREFINT

VSC Scaler offset voltage - - ±5 ±10 mV

IDDA(SCALER) Scaler static consumption

from VDDA

BRG_EN=0 (bridge disable) - 200 300 nA

BRG_EN=1 (bridge enable) - 0.8 1 µA

tSTART_SCALER Scaler startup time - - 100 200 µs

tSTART

Comparator startup time to

reach propagation delay

specification

High-speed

mode

VDDA ≥ 2.7 V - - 5

µs

VDDA < 2.7 V - - 7

Medium mode VDDA ≥ 2.7 V - - 15

VDDA < 2.7 V - - 25

Ultra-low-power mode - - 40

tD(3) Propagation delay with

100 mV overdrive

High-speed

mode

VDDA ≥ 2.7 V - 55 80 ns

VDDA < 2.7 V - 65 100

Medium mode - 0.55 0.9 µs

Ultra-low-power mode - 4 7

Voffset Comparator offset error Full common

mode range --±5±20mV

Vhys Comparator hysteresis

No hysteresis - 0 -

Low hysteresis - 8 -

Medium hysteresis - 15 -

High hysteresis - 27 -

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6.3.22 Operational amplifiers characteristics

IDDA(COMP) Comparator consumption

from VDDA

Ultra-low-

power mode

Static - 400 600

With 50 kHz

±100 mV overdrive

square signal

-1200-

Medium mode

Static - 5 7

µA

With 50 kHz

±100 mV overdrive

square signal

-6-

High-speed

mode

Static - 70 100

With 50 kHz

±100 mV overdrive

square signal

-75-

Ibias Comparator input bias

current ----

(4) nA

1. Guaranteed by design, unless otherwise specified.

2. Refer to Table 25: Embedded internal voltage reference.

3. Guaranteed by characterization results.

4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 60: I/O static characteristics.

Table 75. COMP characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Table 76. OPAMP characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply

voltage(2) -1.8-3.6V

CMIR Common mode

input range -0-V

DDA V

VIOFFSET Input offset

voltage

25 °C, No Load on output. - - ±1.5 mV

All voltage/Temp. - - ±3

∆VIOFFSET Input offset

voltage drift

Normal mode - ±5 - μV/°C

Low-power mode - ±10 -

TRIMOFFSETP

TRIMLPOFFSETP

Offset trim step

at low common

input voltage

(0.1 ₓ VDDA)

--0.81.1

TRIMOFFSETN

TRIMLPOFFSETN

Offset trim step

at high common

input voltage

(0.9 ₓ VDDA)

--11.35

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ILOAD Drive current Normal mode VDDA ≥ 2 V - - 500

µA

Low-power mode - - 100

ILOAD_PGA Drive current in

PGA mode

Normal mode VDDA ≥ 2 V - - 450

Low-power mode - - 50

RLOAD

Resistive load

(connected to

VSSA or to

VDDA)

Normal mode

VDDA < 2 V

4--

kΩ

Low-power mode 20 - -

RLOAD_PGA

Resistive load

in PGA mode

(connected to

VSSA or to

VDDA)

Normal mode

VDDA < 2 V

4.5 - -

Low-power mode 40 - -

CLOAD Capacitive load - - - 50 pF

CMRR Common mode

rejection ratio

Normal mode - -85 - dB

Low-power mode - -90 -

PSRR Power supply

rejection ratio

Normal mode CLOAD ≤ 50 pf,

RLOAD ≥ 4 kΩ DC 70 85 -

Low-power mode CLOAD ≤ 50 pf,

RLOAD ≥ 20 kΩ DC 72 90 -

GBW Gain Bandwidth

Product

Normal mode VDDA ≥ 2.4 V

(OPA_RANGE = 1)

550 1600 2200

kHz

Low-power mode 100 420 600

Normal mode VDDA < 2.4 V

(OPA_RANGE = 0)

250 700 950

Low-power mode 40 180 280

SR(3)

Slew rate

(from 10 and

90% of output

voltage)

Normal mode VDDA ≥ 2.4 V -700-

V/ms

Low-power mode - 180 -

Normal mode VDDA < 2.4 V -300-

Low-power mode - 80 -

AO Open loop gain Normal mode 55 110 - dB

Low-power mode 45 110 -

VOHSAT(3) High saturation

voltage

Normal mode Iload = max or Rload =

min Input at VDDA.

VDDA -

100 --

Low-power mode VDDA -

50 --

VOLSAT(3) Low saturation

voltage

Normal mode Iload = max or Rload =

min Input at 0.

- - 100

Low-power mode - - 50

φmPhase margin Normal mode - 74 - °

Low-power mode - 66 -

Table 76. OPAMP characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

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GM Gain margin Normal mode - 13 - dB

Low-power mode - 20 -

tWAKEUP Wake up time

from OFF state.

Normal mode

CLOAD ≤ 50 pf,

RLOAD ≥ 4 kΩ

follower

configuration

-510

µs

Low-power mode

CLOAD ≤ 50 pf,

RLOAD ≥ 20 kΩ

follower

configuration

-1030

Ibias OPAMP input

bias current General purpose input - - -(4) nA

PGA gain(3) Non inverting

gain value -

-2-

-4-

-8-

-16-

Rnetwork

R2/R1 internal

resistance

values in PGA

mode(5)

PGA Gain = 2 - 80/80 -

kΩ/kΩ

PGA Gain = 4 - 120/

40 -

PGA Gain = 8 - 140/

20 -

PGA Gain = 16 - 150/

10 -

Delta R

Resistance

variation (R1 or

R2)

--15-15%

PGA gain error PGA gain error - -1 - 1 %

PGA BW

PGA bandwidth

for different non

inverting gain

Gain = 2 - - GBW/

MHz

Gain = 4 - - GBW/

Gain = 8 - - GBW/

Gain = 16 - - GBW/

16 -

Table 76. OPAMP characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

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6.3.23 Temperature sensor characteristics

en Voltage noise

density

Normal mode at 1 kHz, Output

loaded with 4 kΩ -500-

nV/√Hz

Low-power mode at 1 kHz, Output

loaded with 20 kΩ -600-

Normal mode at 10 kHz, Output

loaded with 4 kΩ -180-

Low-power mode at 10 kHz, Output

loaded with 20 kΩ -290-

IDDA(OPAMP)(3) OPAMP

consumption

from VDDA

Normal mode no Load, quiescent

mode

- 120 260

µA

Low-power mode - 45 100

1. Guaranteed by design, unless otherwise specified.

2. The temperature range is limited to 0 °C-125 °C when VDDA is below 2 V

3. Guaranteed by characterization results.

4. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 60: I/O static characteristics.

5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between

OPAMP inverting input and ground. The PGA gain =1+R2/R1

Table 76. OPAMP characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Table 77. TS characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VTS linearity with temperature - ±1 ±2 °C

Avg_Slope(2) Average slope 2.3 2.5 2.7 mV/°C

V30 Voltage at 30°C (±5 °C)(3) 0.742 0.76 0.785 V

tSTART

(TS_BUF)(1) Sensor Buffer Start-up time in continuous mode(4) -815µs

tSTART(1) Start-up time when entering in continuous mode(4) -70120µs

tS_temp(1) ADC sampling time when reading the temperature 5 - - µs

IDD(TS)(1) Temperature sensor consumption from VDD, when

selected by ADC -4.77 µA

1. Guaranteed by design.

2. Guaranteed by characterization results.

3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 7:

Temperature sensor calibration values.

4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

BAT VBAT

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6.3.24 VBAT monitoring characteristics

6.3.25 Timer characteristics

The parameters given in the following tables are guaranteed by design.

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Table 78. VBAT monitoring characteristics

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT -39-kΩ

Q Ratio on VBAT measurement - 3 - -

Er(1)

1. Guaranteed by design.

Error on Q -10 - 10 %

tS_vbat(1) ADC sampling time when reading the VBAT 12 - - µs

Table 79. VBAT charging characteristics

Symbol Parameter Conditions Min Typ Max Unit

RBC

Battery

charging

resistor

VBRS = 0 - 5 -

kΩ

VBRS = 1 - 1.5 -

Table 80. TIMx(1) characteristics

1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.

Symbol Parameter Conditions Min Max Unit

tres(TIM) Timer resolution time -1-t

TIMxCLK

fTIMxCLK = 80 MHz 12.5 - ns

fEXT Timer external clock

frequency on CH1 to CH4

-0f

TIMxCLK/2 MHz

fTIMxCLK = 80 MHz 0 40 MHz

ResTIM Timer resolution

TIMx (except

TIM2) -16bit

TIM2 - 32

tCOUNTER 16-bit counter clock

period

- 1 65536 tTIMxCLK

fTIMxCLK = 80 MHz 0.0125 819.2 µs

tMAX_COUNT Maximum possible count

with 32-bit counter

- - 65536 × 65536 tTIMxCLK

fTIMxCLK = 80 MHz - 53.68 s

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6.3.26 Communication interfaces characteristics

I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user

manual rev. 03 for:

•Standard-mode (Sm): with a bitrate up to 100 kbit/s

•Fast-mode (Fm): with a bitrate up to 400 kbit/s

•Fast-mode Plus (Fm+): with a bitrate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly

configured (refer to RM0394 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS

connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins

support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O

port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog

filter characteristics:

Table 81. IWDG min/max timeout period at 32 kHz (LSI)(1)

1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there

is always a full RC period of uncertainty.

Prescaler divider PR[2:0] bits Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF Unit

/4 0 0.125 512

/8 1 0.250 1024

/16 2 0.500 2048

/32 3 1.0 4096

/64 4 2.0 8192

/128 5 4.0 16384

/256 6 or 7 8.0 32768

Table 82. WWDG min/max timeout value at 80 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit

1 0 0.0512 3.2768

2 1 0.1024 6.5536

4 2 0.2048 13.1072

8 3 0.4096 26.2144

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Table 83. I2C analog filter characteristics(1)

1. Guaranteed by design.

Symbol ParameterMinMaxUnit

tAF

Maximum pulse width of spikes

that are suppressed by the analog

filter

50(2)

2. Spikes with widths below tAF(min) are filtered.

260(3)

3. Spikes with widths above tAF(max) are not filtered

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SPI characteristics

Unless otherwise specified, the parameters given in Table 84 for SPI are derived from tests

performed under the ambient temperature, fPCLKx frequency and supply voltage conditions

summarized in Table 22: General operating conditions.

•Output speed is set to OSPEEDRy[1:0] = 11

•Capacitive load C = 30 pF

•Measurement points are done at CMOS levels: 0.5 ₓ VDD

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 84. SPI characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fSCK

1/tc(SCK) SPI clock frequency

Master mode receiver/full duplex

2.7 < VDD < 3.6 V

Voltage Range 1

MHz

Master mode receiver/full duplex

1.71 < VDD < 3.6 V

Voltage Range 1

Master mode transmitter

1.71 < VDD < 3.6 V

Voltage Range 1

Slave mode receiver

1.71 < VDD < 3.6 V

Voltage Range 1

Slave mode transmitter/full duplex

2.7 < VDD < 3.6 V

Voltage Range 1

37(2)

Slave mode transmitter/full duplex

1.71 < VDD < 3.6 V

Voltage Range 1

20(2)

Voltage Range 2 13

tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4ₓTPCLK --ns

th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2ₓTPCLK --ns

tw(SCKH)

tw(SCKL) SCK high and low time Master mode TPCLK-2 TPCLK TPCLK+2 ns

tsu(MI) Data input setup time Master mode 4 - - ns

tsu(SI) Slave mode 1.5 - -

th(MI) Data input hold time Master mode 6.5 - - ns

th(SI) Slave mode 1.5 - -

ta(SO) Data output access time Slave mode 9 - 36 ns

tdis(SO) Data output disable time Slave mode 9 - 16 ns

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Figure 32. SPI timing diagram - slave mode and CPHA = 0

tv(SO) Data output valid time

Slave mode 2.7 < VDD < 3.6 V

Voltage Range 1 - 12.5 13.5

Slave mode 1.71 < VDD < 3.6 V

Voltage Range 1 -12.524

Slave mode 1.71 < VDD < 3.6 V

Voltage Range 2 -12.533

tv(MO) Master mode - 4.5 6

th(SO) Data output hold time Slave mode 7 - - ns

th(MO) Master mode 0 - -

1. Guaranteed by characterization results.

2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or

high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

having tsu(MI) = 0 while Duty(SCK) = 50 %.

Table 84. SPI characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

MSv41658V1

NSS input

CPHA=0

CPOL=0

SCK input

CPHA=0

CPOL=1

MISO output

MOSI input

tsu(SI)

th(SI)

tw(SCKL)

tw(SCKH)

tc(SCK)

tr(SCK)

th(NSS)

tdis(SO)

tsu(NSS)

ta(SO) tv(SO)

Next bits IN

Last bit OUT

First bit IN

First bit OUT Next bits OUT

th(SO) tf(SCK)

Last bit IN

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Figure 33. SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

Figure 34. SPI timing diagram - master mode

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

MSv41659V1

NSS input

CPHA=1

CPOL=0

SCK input

CPHA=1

CPOL=1

MISO output

MOSI input

tsu(SI) th(SI)

tw(SCKL)

tw(SCKH)

tsu(NSS)

tc(SCK)

ta(SO) tv(SO)

First bit OUT Next bits OUT

Next bits IN

Last bit OUT

th(SO) tr(SCK)

tf(SCK) th(NSS)

tdis(SO)

First bit IN Last bit IN

ai14136c

SCK Output

CPHA= 0

MOSI

OUTPUT

MISO

INP UT

CPHA= 0

LSB OUT

LSB IN

CPOL=0

CPOL=1

B IT1 OUT

NSS input

tc(SCK)

tw(SCKH)

tw(SCKL)

tr(SCK)

tf(SCK)

th(MI)

High

SCK Output

CPHA=1

CPOL=0

CPOL=1

tsu(MI)

tv(MO) th(MO)

MSB IN BIT6 IN

MSB OUT

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Quad SPI characteristics

Unless otherwise specified, the parameters given in Table 85 and Table 86 for Quad SPI

are derived from tests performed under the ambient temperature, fAHB frequency and VDD

supply voltage conditions summarized in Table 22: General operating conditions, with the

following configuration:

•Output speed is set to OSPEEDRy[1:0] = 11

•Capacitive load C = 15 or 20 pF

•Measurement points are done at CMOS levels: 0.5 ₓ VDD

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics.

Table 85. Quad SPI characteristics in SDR mode(1)

Symbol Parameter Conditions Min Typ Max Unit

FCK

1/t(CK)

Quad SPI clock frequency

1.71 < VDD< 3.6 V, CLOAD = 20 pF

Voltage Range 1 --40

MHz

1.71 < VDD< 3.6 V, CLOAD = 15 pF

Voltage Range 1 --48

2.7 < VDD< 3.6 V, CLOAD = 15 pF

Voltage Range 1 --60

1.71 < VDD < 3.6 V CLOAD = 20 pF

Voltage Range 2 --26

tw(CKH) Quad SPI clock high and

low time fAHBCLK= 48 MHz, presc=0 t(CK)/2-2 - t(CK)/2

tw(CKL) t(CK)/2 - t(CK)/2+2

ts(IN) Data input setup time Voltage Range 1 2 - -

Voltage Range 2 3.5 - -

th(IN) Data input hold time Voltage Range 1 5 - -

Voltage Range 2 6.5 - -

tv(OUT) Data output valid time Voltage Range 1 - 1 5

Voltage Range 2 - 3 5

th(OUT) Data output hold time Voltage Range 1 0 - -

Voltage Range 2 0 - -

1. Guaranteed by characterization results.

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Table 86. QUADSPI characteristics in DDR mode(1)

Symbol Parameter Conditions Min Typ Max Unit

FCK

1/t(CK)

Quad SPI clock

frequency

1.71 < VDD < 3.6 V, CLOAD = 20 pF

Voltage Range 1 --40

MHz

2 < VDD < 3.6 V, CLOAD = 20 pF

Voltage Range 1 --48

1.71 < VDD < 3.6 V, CLOAD = 15 pF

Voltage Range 1 --48

1.71 < VDD < 3.6 V CLOAD = 20 pF

Voltage Range 2 --26

tw(CKH) Quad SPI clock high

and low time fAHBCLK = 48 MHz, presc=0 t(CK)/2-2 - t(CK)/2

tw(CKL) t(CK)/2 - t(CK)/2+2

tsr(IN) Data input setup time

on rising edge

Voltage Range 1 1 --

Voltage Range 2 3.5

tsf(IN) Data input setup time

on falling edge

Voltage Range 1 1 --

Voltage Range 2 1.5

thr(IN) Data input hold time

on rising edge

Voltage Range 1 6 --

Voltage Range 2 6.5

thf(IN) Data input hold time

on falling edge

Voltage Range 1 5.5 --

Voltage Range 2 5.5

tvr(OUT) Data output valid time

on rising edge

Voltage Range 1 -55.5

Voltage Range 2 9.5 14

tvf(OUT) Data output valid time

on falling edge

Voltage Range 1 -58.5

Voltage Range 2 15 19

thr(OUT) Data output hold time

on rising edge

Voltage Range 1 3.5 - -

Voltage Range 2 8 -

thf(OUT) Data output hold time

on falling edge

Voltage Range 1 3.5 - -

Voltage Range 2 13 -

1. Guaranteed by characterization results.

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Figure 35. Quad SPI timing diagram - SDR mode

Figure 36. Quad SPI timing diagram - DDR mode

MSv36878V1

Data output D0 D1 D2

Clock

Data input D0 D1 D2

t(CK) tw(CKH) tw(CKL)

tr(CK) tf(CK)

ts(IN) th(IN)

tv(OUT) th(OUT)

MSv36879V3

Data output IO0 IO2 IO4

Clock

Data input IO0 IO2 IO4

t(CLK) tw(CLKH) tw(CLKL)

tr(CLK) tf(CLK)

tsf(IN) thf(IN)

tvf(OUT) thr(OUT)

IO1 IO3 IO5

tvr(OUT) thf(OUT)

tsr(IN) thr(IN)

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SAI characteristics

Unless otherwise specified, the parameters given in Table 87 for SAI are derived

from tests performed under the ambient temperature, fPCLKx frequency and VDD

supply voltage conditions summarized inTable 22: General operating conditions, with

the following configuration:

•Output speed is set to OSPEEDRy[1:0] = 10

•Capacitive load C = 30 pF

•Measurement points are done at CMOS levels: 0.5 ₓ VDD

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output

alternate function characteristics (CK,SD,FS).

Table 87. SAI characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCLK SAI Main clock output - - 50 MHz

fCK SAI clock frequency(2)

Master transmitter

2.7 ≤ VDD ≤ 3.6

Voltage Range 1

-18.5

MHz

Master transmitter

1.71 ≤ VDD ≤ 3.6

Voltage Range 1

-12.5

Master receiver

Voltage Range 1 -25

Slave transmitter

2.7 ≤ VDD ≤ 3.6

Voltage Range 1

-22.5

Slave transmitter

1.71 ≤ VDD ≤ 3.6

Voltage Range 1

-14.5

Slave receiver

Voltage Range 1 -25

Voltage Range 2 - 12.5

tv(FS) FS valid time

Master mode

2.7 ≤ VDD ≤ 3.6 -22

Master mode

1.71 ≤ VDD ≤ 3.6 -40

th(FS) FS hold time Master mode 10 - ns

tsu(FS) FS setup time Slave mode 1 - ns

th(FS) FS hold time Slave mode 2 - ns

tsu(SD_A_MR) Data input setup time Master receiver 2 - ns

tsu(SD_B_SR) Slave receiver 1.5 -

th(SD_A_MR) Data input hold time Master receiver 5 - ns

th(SD_B_SR) Slave receiver 2.5 -

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Figure 37. SAI master timing waveforms

tv(SD_B_ST) Data output valid time

Slave transmitter (after enable edge)

2.7 ≤ VDD ≤ 3.6 -22

Slave transmitter (after enable edge)

1.71 ≤ VDD ≤ 3.6 -34

th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 10 - ns

tv(SD_A_MT) Data output valid time

Master transmitter (after enable edge)

2.7 ≤ VDD ≤ 3.6 -27

Master transmitter (after enable edge)

1.71 ≤ VDD ≤ 3.6 -40

th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 10 - ns

1. Guaranteed by characterization results.

2. APB clock frequency must be at least twice SAI clock frequency.

Table 87. SAI characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

MS32771V1

SAI_SCK_X

SAI_FS_X

(output)

1/fSCK

SAI_SD_X

(transmit)

tv(FS)

Slot n

SAI_SD_X

(receive)

th(FS)

Slot n+2

tv(SD_MT) th(SD_MT)

Slot n

tsu(SD_MR) th(SD_MR)

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Figure 38. SAI slave timing waveforms

SDMMC characteristics

Unless otherwise specified, the parameters given in Table 88 for SDIO are derived from

tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 22: General operating conditions, with the following

configuration:

•Output speed is set to OSPEEDRy[1:0] = 11

•Capacitive load C = 30 pF

•Measurement points are done at CMOS levels: 0.5 ₓ VDD

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output

characteristics.

Table 88. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1)

Symbol Parameter Conditions Min Typ Max Unit

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDIO_CK/fPCLK2 frequency ratio - - - 4/3 -

tW(CKL) Clock low time fPP = 50 MHz 8 10 - ns

tW(CKH) Clock high time fPP = 50 MHz 8 10 - ns

CMD, D inputs (referenced to CK) in MMC and SD HS mode

tISU Input setup time HS fPP = 50 MHz 3.5 - - ns

tIH Input hold time HS fPP = 50 MHz 2.5 - - ns

CMD, D outputs (referenced to CK) in MMC and SD HS mode

tOV Output valid time HS fPP = 50 MHz - 12 13 ns

tOH Output hold time HS fPP = 50 MHz 10 - - ns

CMD, D inputs (referenced to CK) in SD default mode

tISUD Input setup time SD fPP = 50 MHz 3.5 - - ns

tIHD Input hold time SD fPP = 50 MHz 3 - - ns

MS32772V1

SAI_SCK_X

SAI_FS_X

(input)

SAI_SD_X

(transmit)

tsu(FS)

Slot n

SAI_SD_X

(receive)

tw(CKH_X) th(FS)

Slot n+2

tv(SD_ST) th(SD_ST)

Slot n

tsu(SD_SR)

tw(CKL_X)

th(SD_SR)

1/fSCK

CK D, CMD (mnpm) D, CMD (\nput) ‘mew L Won) ‘OH IX Msu” aMAES7

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Figure 39. SDIO high-speed mode

CMD, D outputs (referenced to CK) in SD default mode

tOVD Output valid default time SD fPP = 50 MHz - 2 3 ns

tOHD Output hold default time SD fPP = 50 MHz 0 - - ns

1. Guaranteed by characterization results.

Table 89. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V(1)(2)

1. Guaranteed by characterization results.

2. CLOAD = 20pF.

Symbol Parameter Conditions Min Typ Max Unit

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDIO_CK/fPCLK2 frequency ratio - - - 4/3 -

tW(CKL) Clock low time fPP = 50 MHz 8 10 - ns

tW(CKH) Clock high time fPP = 50 MHz 8 10 - ns

CMD, D inputs (referenced to CK) in eMMC mode

tISU Input setup time HS fPP = 50 MHz 0 - - ns

tIH Input hold time HS fPP = 50 MHz 1.5 - - ns

CMD, D outputs (referenced to CK) in eMMC mode

tOV Output valid time HS fPP = 50 MHz - 13.5 15 ns

tOH Output hold time HS fPP = 50 MHz 9 - - ns

Table 88. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Electrical characteristics STM32L462CE STM32L462RE STM32L462VE

182/210 DS11913 Rev 5

Figure 40. SD default mode

USB characteristics

The STM32L462xx USB interface is fully compliant with the USB specification version 2.0

and is USB-IF certified (for Full-speed device operation).

CAN (controller area network) interface

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (CAN_TX and CAN_RX).

ai14888

D, CMD

(output)

tOVD tOHD

Table 90. USB electrical characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDUSB USB transceiver operating voltage 3.0(2) -3.6V

Tcrystal_less USB crystal less operation temperature -15 - 85 °C

tSTARTUP(3) USB transceiver startup time - - 1.0 µs

RPUI Embedded USB_DP pull-up value during idle 900 1250 1600

RPUR Embedded USB_DP pull-up value during

reception 1400 2300 3200

ZDRV(3) Output driver impedance(4) Driving high

and low 28 36 44 Ω

1. TA = -40 to 125 °C unless otherwise specified.

2. The STM32L462xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics

which are degraded in the 2.7-to-3.0 V voltage range.

3. Guaranteed by design.

4. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching

impedance is already included in the embedded driver.

9: 41b T IIIIIII—r

DS11913 Rev 5 183/210

STM32L462CE STM32L462RE STM32L462VE Package information

206

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

7.1 LQFP100 package information

This LQFP is a 100-pin, 14 x 14 mm low-profile quad flat package.

Figure 41. LQFP100 - Outline

1. Drawing is not to scale.

Table 91. LQFP100 - Mechanical data

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630

A1 0.050 - 0.150 0.0020 - 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

IDENTIFICATION

PIN 1

GAUGE PLANE

0.25 mm

SEATING PLANE

ccc C

125

100

75 51

1L_ME_V5

EEEEEEE EEEEEE H% H". H". H". 7 EEEEEE EEEEEE

Package information STM32L462CE STM32L462RE STM32L462VE

184/210 DS11913 Rev 5

Figure 42. LQFP100 - Recommended footprint

1. Dimensions are expressed in millimeters.

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 - 0.200 0.0035 - 0.0079

D 15.800 16.000 16.200 0.6220 0.6299 0.6378

D1 13.800 14.000 14.200 0.5433 0.5512 0.5591

D3 - 12.000 - - 0.4724 -

E 15.800 16.000 16.200 0.6220 0.6299 0.6378

E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 - 12.000 - - 0.4724 -

e - 0.500 - - 0.0197 -

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -

k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°

ccc - - 0.080 - - 0.0031

1. Values in inches are converted from mm and rounded to four decimal digits.

Table 91. LQFP100 - Mechanical data (continued)

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

75 51

5076 0.5

0.3

16.7 14.3

100 26

12.3

1.2

16.7

ai14906c

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206

Device marking

The following figures give examples of topside marking orientation versus pin 1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 43. LQFP100 marking (package top view)

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST’s Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

MSv43807V1

YWW

Revision code

Product identification(1)

Date code

Pin 1

indentifier

STM32L462

VET6 B

Optional gate mark

P O Am 5“ mar“ area ‘7 4' >ooooooooo oooooooooooo 00000 00000 000 see 000 000 00 oo 00 + GO 000 000 000 000 00000 00000 e 0000000000069 000000000?” T .Ew museum‘s)

Package information STM32L462CE STM32L462RE STM32L462VE

186/210 DS11913 Rev 5

7.2 UFBGA100 package information

This UFBGA is a 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.

Figure 44. UFBGA100 -Outline

1. Drawing is not to scale.

Table 92. UFBGA100 - Mechanical data

Symbol

millimeters inches(1)

Min. Typ. Max. Min. Typ. Max.

A - - 0.600 - - 0.0236

A1 - - 0.110 - - 0.0043

A2 - 0.450 - - 0.0177 -

A3 - 0.130 - - 0.0051 0.0094

A4 - 0.320 - - 0.0126 -

b 0.240 0.290 0.340 0.0094 0.0114 0.0134

D 6.850 7.000 7.150 0.2697 0.2756 0.2815

D1 - 5.500 - - 0.2165 -

E 6.850 7.000 7.150 0.2697 0.2756 0.2815

E1 - 5.500 - - 0.2165 -

e - 0.500 - - 0.0197 -

Z - 0.750 - - 0.0295 -

A0C2_ME_V5

Seating plane

Øb (100 balls)

TOP VIEWBOTTOM VIEW

112

A1 ball

identifier

ddd Z

eee ZYX

fff

A1 ball

index area

DS11913 Rev 5 187/210

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206

Figure 45. UFBGA100 - Recommended footprint

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

ddd - - 0.080 - - 0.0031

eee - - 0.150 - - 0.0059

fff - - 0.050 - - 0.0020

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 93. UFBGA100 - Recommended PCB design rules (0.5 mm pitch BGA)

Dimension Recommended values

Pitch 0.5

Dpad 0.280 mm

Dsm 0.370 mm typ. (depends on the solder mask

registration tolerance)

Stencil opening 0.280 mm

Stencil thickness Between 0.100 mm and 0.125 mm

Table 92. UFBGA100 - Mechanical data (continued)

Symbol

millimeters inches(1)

Min. Typ. Max. Min. Typ. Max.

BGA_WLCSP_FT_V1

Dsm

Dpad

Package information STM32L462CE STM32L462RE STM32L462VE

188/210 DS11913 Rev 5

Figure 46. UFBGA100 marking (package top view)

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST’s Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

MSv43809V1

Product identification(1)

STM32L

462VEI6

WWY

Date code

Pin 1 identifier

HHMMMMMWM E i g E 1 :

DS11913 Rev 5 189/210

STM32L462CE STM32L462RE STM32L462VE Package information

206

7.3 LQFP64 package information

This LQFP is a 64-pin, 10 x 10 mm low-profile quad flat package.

Figure 47. LQFP64 - Outline

1. Drawing is not to scale.

Table 94. LQFP64 - Mechanical data

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630

A1 0.050 - 0.150 0.0020 - 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 - 0.200 0.0035 - 0.0079

D - 12.000 - - 0.4724 -

D1 - 10.000 - - 0.3937 -

D3 - 7.500 - - 0.2953 -

E - 12.000 - - 0.4724 -

E1 - 10.000 - - 0.3937 -

5W_ME_V3

SEATING PLANE

ccc C

IDENTIFICATION

PIN 1

116

GAUGE PLANE

0.25 mm

’ ,4444444,ﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂ HUD 4>+ UH ﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂ HHHHHHHHHHHHH unnnnnnnnnnnnnn E P H +

Package information STM32L462CE STM32L462RE STM32L462VE

190/210 DS11913 Rev 5

Figure 48. LQFP64 - Recommended footprint

1. Dimensions are expressed in millimeters.

Device marking

The following figure give examples of topside marking orientation versus pin 1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

E3 - 7.500 - - 0.2953 -

e - 0.500 - - 0.0197 -

K 0°3.5°7° 0°3.5°7°

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -

ccc - - 0.080 - - 0.0031

1. Values in inches are converted from mm and rounded to four decimal digits.

Table 94. LQFP64 - Mechanical data (continued)

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

64 17

116

1.2

0.3

10.3

12.7

10.3

0.5

7.8

12.7

ai14909c

"(1)

DS11913 Rev 5 191/210

STM32L462CE STM32L462RE STM32L462VE Package information

206

Figure 49. LQFP64 marking (package top view)

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST’s Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

MSv43811V1

Date code

Pin 1 identifier

STM32L462

RET6

Product identification(1)

Revision code

Y WW

mwOOOOOmwmw 00000000 0000000 OOOO+OOOO 00000000 00000000 awOOOOOOO $OOOOOOO

Package information STM32L462CE STM32L462RE STM32L462VE

192/210 DS11913 Rev 5

7.4 UFBGA64 package information

This UFBGA is a 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array

package.

Figure 50. UFBGA64 - Outline

1. Drawing is not to scale.

A019_ME_V1

Seating plane

Øb (64 balls)

TOP VIEWBOTTOM VIEW

ddd Z

eee Z Y X

fff

A1 ball

identifier

A1 ball

index area

Table 95. UFBGA64 - Mechanical data

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043

A2 0.400 0.450 0.500 0.0157 0.0177 0.0197

A3 0.080 0.130 0.180 0.0031 0.0051 0.0071

A4 0.270 0.320 0.370 0.0106 0.0126 0.0146

b 0.170 0.280 0.330 0.0067 0.0110 0.0130

D 4.850 5.000 5.150 0.1909 0.1969 0.2028

D1 3.450 3.500 3.550 0.1358 0.1378 0.1398

E 4.850 5.000 5.150 0.1909 0.1969 0.2028

E1 3.450 3.500 3.550 0.1358 0.1378 0.1398

e - 0.500 - - 0.0197 -

F 0.700 0.750 0.800 0.0276 0.0295 0.0315

DS11913 Rev 5 193/210

STM32L462CE STM32L462RE STM32L462VE Package information

206

Figure 51. UFBGA64 - Recommended footprint

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

ddd - - 0.080 - - 0.0031

eee - - 0.150 - - 0.0059

fff - - 0.050 - - 0.0020

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 95. UFBGA64 - Mechanical data (continued)

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

Table 96. UFBGA64 - Recommended PCB design rules (0.5 mm pitch BGA)

Dimension Recommended values

Pitch 0.5

Dpad 0.280 mm

Dsm 0.370 mm typ. (depends on the soldermask

registration tolerance)

Stencil opening 0.280 mm

Stencil thickness Between 0.100 mm and 0.125 mm

Pad trace width 0.100 mm

BGA_WLCSP_FT_V1

Dsm

Dpad

Package information STM32L462CE STM32L462RE STM32L462VE

194/210 DS11913 Rev 5

Figure 52. UFBGA64 marking (package top view)

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST’s Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

MSv43813V1

Product identification(1)

L462REI6

WWY

Date code

Pin 1 identifier

DS11913 Rev 5 195/210

STM32L462CE STM32L462RE STM32L462VE Package information

206

7.5 WLCSP64 package information

This WLCSP is a 64 balls, 3.357x3.657 mm 0.4 mm pitch wafer level chip scale package.

Figure 53. WLCSP64 - Outline

1. Dimensions are expressed in millimeters.

2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.

3. Bump position designation per JESD 95-1, SPP-010.

FORIENTATION

REFERENCE

Ge1

e2E

BOTTOM VIEW

BUMP SIDE

DETAIL A

SIDE VIEW

FRONT VIEW

TOP VIEW

WAFER BACK SIDE

DETAIL A

ROTATED 90

BUMP

A07P_ME_V1

Package information STM32L462CE STM32L462RE STM32L462VE

196/210 DS11913 Rev 5

Figure 54. WLCSP64 - Recommended footprint

1. Dimensions are expressed in millimeters.

Table 97. WLCSP64 - Mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Min Typ Max Min Typ Max

A 0.525 0.555 0.585 0.0207 0.0219 0.0230

A1 - 0.175 - - 0.0069 -

A2 - 0.380 - - 0.0150 -

A3 - 0.025 - - 0.0010 -

b(2)

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

0.220 0.250 0.280 0.0087 0.0098 0.0110

D 3.322 3.357 3.392 0.1308 0.1322 0.1335

E 3.622 3.657 3.692 0.1426 0.1440 0.1454

e - 0.400 - - 0.0157 -

e1 - 2.800 - - 0.1102 -

e2 - 2.800 - - 0.1102 -

F - 0.2785 - - 0.0110 -

G - 0.4285 - - 0.0169 -

aaa - - 0.100 - - 0.0039

bbb - - 0.100 - - 0.0039

ccc - - 0.100 - - 0.0039

ddd - - 0.050 - - 0.0020

eee - - 0.050 - - 0.0020

BGA_WLCSP_FT_V1

Dsm

Dpad

DS11913 Rev 5 197/210

STM32L462CE STM32L462RE STM32L462VE Package information

206

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 55. WLCSP64 marking (package top view)

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST’s Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

Table 98. WLCSP64 - Recommended PCB design rules (0.4 mm pitch)

Dimension Recommended values

Pitch 0.4 mm

Dpad 0.225 mm

Dsm 0.290 mm typ. (depends on the soldermask

registration tolerance)

Stencil opening 0.250 mm

Stencil thickness 0.100 mm

MSv43815V1

Product identification(1)

L462REY6

Date code

Pin 1 identifier

aNe mmmmmmm m WWWW J L_J mmmmmimmwmw i,i+i,i i WWWWW

Package information STM32L462CE STM32L462RE STM32L462VE

198/210 DS11913 Rev 5

7.6 LQFP48 package information

This LQFP is a 48 pins, 7 x 7 mm low-profile quad flat package

Figure 56. LQFP48 - Outline

1. Drawing is not to scale.

5B_ME_V2

PIN 1

IDENTIFICATION

ccc C

0.25 mm

GAUGE PLANE

SEATING

PLANE

DS11913 Rev 5 199/210

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206

Table 99. LQFP48 - Mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630

A1 0.050 - 0.150 0.0020 - 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 - 0.200 0.0035 - 0.0079

D 8.800 9.000 9.200 0.3465 0.3543 0.3622

D1 6.800 7.000 7.200 0.2677 0.2756 0.2835

D3 - 5.500 - - 0.2165 -

E 8.800 9.000 9.200 0.3465 0.3543 0.3622

E1 6.800 7.000 7.200 0.2677 0.2756 0.2835

E3 - 5.500 - - 0.2165 -

e - 0.500 - - 0.0197 -

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -

k 0°3.5°7° 0°3.5°7°

ccc - - 0.080 - - 0.0031

# mymmnnmnnﬂ /\ i”. ‘17 Oak

Package information STM32L462CE STM32L462RE STM32L462VE

200/210 DS11913 Rev 5

Figure 57. LQFP48 - Recommended footprint

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 58. LQFP48 marking (package top view)

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

9.70 5.80 7.30

0.20

7.30

1.20

5.80

9.70

0.30

1.20

0.50

ai14911d

1348

MSv67500V1

Date code

Pin 1 identifier

CET6

Product identification(1)

Revision code

Y WW

STM32L462

‘4—D‘ WT, ++

DS11913 Rev 5 201/210

STM32L462CE STM32L462RE STM32L462VE Package information

206

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST’s Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

7.7 UFQFPN48 package information

This UFQFPN is a 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 59. UFQFPN48 - Outline

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and

solder this back-side pad to PCB ground.

A0B9_ME_V3

Pin 1 identifier

laser marking area

Exposed pad

area

Detail Z

R 0.125 typ.

C 0.500x45°

pin1 corner

Seating

plane

ddd

Detail Y

47—» <74» nunnnnnnnnnn‘="" +h4="" dddddddu="" m="" “£2="" ;:nnnnnnnnnnnniﬁ="" +j—k="" ‘="" 54.74»="" dddddddddd?=""><74»>

Package information STM32L462CE STM32L462RE STM32L462VE

202/210 DS11913 Rev 5

Figure 60. UFQFPN48 - Recommended footprint

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier

location.

The printed markings may differ depending on the supply chain.

Table 100. UFQFPN48 - Mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020

D 6.900 7.000 7.100 0.2717 0.2756 0.2795

E 6.900 7.000 7.100 0.2717 0.2756 0.2795

D2 5.500 5.600 5.700 0.2165 0.2205 0.2244

E2 5.500 5.600 5.700 0.2165 0.2205 0.2244

L 0.300 0.400 0.500 0.0118 0.0157 0.0197

T - 0.152 - - 0.0060 -

b 0.200 0.250 0.300 0.0079 0.0098 0.0118

e - 0.500 - - 0.0197 -

ddd - - 0.080 - - 0.0031

7.30

0.20

0.30

0.55 0.50

5.80

6.20

5.60

5.80

0.75

A0B9_FP_V2

13 24

< *4.="" ‘17="" ngi="">

DS11913 Rev 5 203/210

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206

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 61. UFQFPN48 marking (package top view)

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST’s Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

MSv43817V1

Date code

Pin 1 identifier

462CEU6

Product identification(1)

Revision code

Y WW

STM32L

Package information STM32L462CE STM32L462RE STM32L462VE

204/210 DS11913 Rev 5

7.8 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated

using the following equation:

TJ max = TA max + (PD max x ΘJA)

Where:

•TA max is the maximum ambient temperature in °C,

•ΘJA is the package junction-to-ambient thermal resistance, in °C/W,

•PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),

•PINT max is the product of all IDDXXX and VDDXXX, expressed in Watts. This is the

maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:

PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH),

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the

application.

7.8.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

7.8.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Section 8: Ordering information.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at

maximum dissipation and, to a specific maximum junction temperature.

Table 101. Package thermal characteristics

Symbol Parameter Value Unit

ΘJA

Thermal resistance junction-ambient

LQFP100 - 14 × 14 mm / 0.5 mm pitch 56

°C/W

Thermal resistance junction-ambient

UFBGA100 - 7 × 7 mm / 0.5 mm pitch 75

Thermal resistance junction-ambient

LQFP64 - 10 × 10 mm / 0.5 mm pitch 58

Thermal resistance junction-ambient

UFBGA64 - 5 × 5 mm / 0.5 mm pitch 65

Thermal resistance junction-ambient

WLCSP64 3.357 x 3.657 / 0.4 mm pitch 53

Thermal resistance junction-ambient

LQFP48 7 x 7 / 0.5 mm pitch 55.7

Thermal resistance junction-ambient

UFQFPN48 - 7 × 7 mm / 0.5 mm pitch 29

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STM32L462CE STM32L462RE STM32L462VE Package information

206

As applications do not commonly use the STM32L462xx at maximum dissipation, it is useful

to calculate the exact power consumption and junction temperature to determine which

temperature range is best suited to the application.

The following examples show how to calculate the temperature range needed for a given

application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature TAmax = 75 °C (measured according to JESD51-2),

IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low

level with IOL = 8 mA, VOL = 0.4 V and maximum 8 I/Os used at the same time in output

at low level with IOL = 20 mA, VOL= 1.3 V

PINTmax = 50 mA × 3.5 V = 175 mW

PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

This gives: PINTmax = 175 mW and PIOmax = 272 mW:

PDmax = 175 + 272 = 447 mW

Using the values obtained in Table 101 TJmax is calculated as follows:

– For LQFP64, 58 °C/W

TJmax = 75 °C + (58 °C/W × 447 mW) = 75 °C + 25.926 °C = 100.926 °C

This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Section 8:

Ordering information.

In this case, parts must be ordered at least with the temperature range suffix 6 (see Part

numbering).

Note: With this given PDmax user can find the TAmax allowed for a given device temperature range

(order code suffix 6 or 3).

Suffix 6: TAmax = TJmax - (58°C/W × 447 mW) = 105-25.926 = 79.074 °C

Suffix 3: TAmax = TJmax - (58°C/W × 447 mW) = 130-25.926 = 104.074 °C

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient

temperatures with a low dissipation, as long as junction temperature TJ remains within the

specified range.

Assuming the following application conditions:

Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),

IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low

level with IOL = 8 mA, VOL = 0.4 V

PINTmax = 20 mA × 3.5 V = 70 mW

PIOmax = 20 × 8 mA × 0.4 V = 64 mW

This gives: PINTmax = 70 mW and PIOmax = 64 mW:

PDmax = 70 + 64 = 134 mW

Thus: PDmax = 134 mW

Package information STM32L462CE STM32L462RE STM32L462VE

206/210 DS11913 Rev 5

Using the values obtained in Table 101 TJmax is calculated as follows:

– For LQFP64, 58 °C/W

TJmax = 100 °C + (58 °C/W × 134 mW) = 100 °C + 7.772 °C = 107.772 °C

This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).

In this case, parts must be ordered at least with the temperature range suffix 3 (see

Section 8: Ordering information) unless we reduce the power dissipation in order to be able

to use suffix 6 parts.

Refer to Figure 62 to select the required temperature range (suffix 6 or 3) according to your

ambient temperature or power requirements.

Figure 62. LQFP64 PD max vs. TA

MSv45731V1

600

100

200

300

400

500

700

65 75 85 95 105 115 125 135

Suffix 6

PD (mW)

TA (°C)

Suffix 3

% STM32 : Arm®

DS11913 Rev 5 207/210

STM32L462CE STM32L462RE STM32L462VE Ordering information

209

8 Ordering information

For a list of available options (such as speed, package) or for further information on any

aspect of this device contact the nearest ST sales office.

Table 102. STM32L462xx ordering information scheme

Example: STM32 L 462 C E T 6 TR

Device family

STM32 = Arm® based 32-bit microcontroller

Product type

L = ultra-low-power

Device subfamily

462: STM32L462xx

Pin count

C = 48 pins

R = 64 pins

V = 100 pins

Flash memory size

E = 512 KB of Flash memory

Package

T = LQFP ECOPACK®2

U = QFN ECOPACK®2

I = UFBGA ECOPACK®2

Y = CSP ECOPACK®2

Temperature range

6 = Industrial temperature range, -40 to 85 °C (105 °C junction)

3 = Industrial temperature range, -40 to 125 °C (130 °C junction)

Packing

TR = tape and reel

xxx = programmed parts

Revision history STM32L462CE STM32L462RE STM32L462VE

208/210 DS11913 Rev 5

9 Revision history

Table 103. Document revision history

Date Revision Changes

21-Apr-2017 1 Initial release.

05-May-2017 2

Updated some power consumptions on cover page.

Added Table 4: Functionalities depending on the

working mode.

Updated Table 34: Current consumption in Stop 2 mode.

Updated Table 35: Current consumption in Stop 1 mode.

Updated Table 37: Current consumption in Standby

mode.

Updated Table 66: ADC characteristics.

Updated note below Table 30: Typical connection

diagram using the ADC.

26-May-2017 3

Added missing LPUART communication interface on

cover page.

Fixed OPAMP index in Table 3: STM32L462xx modes

overview.

Replaced RAM2 by SRAM2 in Section 3.9.3: Voltage

regulator and Section 3.9.4: Low-power modes.

Updated Section 3.7: Boot modes.

Added Table 9: DFSDM1 implementation.

Updated Table 60: I/O static characteristics.

Updated Section 7.2: UFBGA100 package information.

21-May-2018 4

Updated DAC terminology in all the document for

clarification: single DAC instance (= DAC1) with 2 output

channels.

Added ECOPACK2® information in Features.

Updated LPUART bullet in Features.

Updated Section 3.9.1: Power supply schemes.

Added Figure 3: Power-up/down sequence.

Added DFSDM1 in Table 5: STM32L462xx peripherals

interconnect matrix.

Updated Clock-out capability in Section 3.11: Clocks

and startup.

Updated Figure 4: Clock tree.

Updated Section 3.14.1: Nested vectored interrupt

controller (NVIC).

Removed a footnote in Table 15: STM32L462xx pin

definitions.

Updated Section 6.3.2: Operating conditions at power-

up / power-down.

Updated ACoeff in Table 25: Embedded internal voltage

reference.

Updated Table 40: Peripheral current consumption.

DS11913 Rev 5 209/210

STM32L462CE STM32L462RE STM32L462VE Revision history

209

21-May-2018 4

(continued)

Added Section 6.3.16: Extended interrupt and event

controller input (EXTI) characteristics.

Updated Table 60: I/O static characteristics.

Updated Table 72: DAC characteristics.

14-Oct-2020 5

Added LQFP48 Package.

Updated Energy benchmark.

Updated Table 1: STM32L462xx family device features

and peripheral counts.

Added Figure 11: STM32L462Cx LQFP48 pinout(1).

Updated Table 15: STM32L462xx pin definitions.

Updated Figure 13: STM32L462xx memory map.

Updated Table 22: General operating conditions.

Updated Table 49: MSI oscillator characteristics.

Updated Section 6.3.14: I/O port characteristics.

Updated Table 61: Output voltage characteristics.

Updated Figure 36: Quad SPI timing diagram - DDR

mode.

Updated Table 90: USB electrical characteristics.

Updated Section 7: Package information.

Added Section 7.6: LQFP48 package information.

Updated Table 101: Package thermal characteristics.

Table 103. Document revision history (continued)

Date Revision Changes

STM32L462CE STM32L462RE STM32L462VE

210/210 DS11913 Rev 5

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STM32L462 Datasheet by STMicroelectronics

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