TS4990 Datasheet by STMicroelectronics

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This is information on a product in full production.
January 2019 DocID9309 Rev 14 1/33
TS4990
1.2 W audio power amplifier with active-low standby mode
Datasheet - production data
Features
Operating range from VCC = 2.2 V to 5.5 V
1.2 W output power at VCC =5V, THD=1%,
F = 1 kHz, with 8 load
Ultra-low consumption in standby mode
(10 nA)
62 dB PSRR at 217 Hz in grounded mode
Near-zero pop and click
Ultra-low distortion (0.1%)
Unity gain stable
Available in 9-bump flip-chip, miniSO-8 and
DFN8 packages
Applications
Mobile phones (cellular / cordless)
Laptop / notebook computers
PDAs
Portable audio devices
Description
The TS4990 is designed for demanding audio
applications such as mobile phones to reduce the
number of external components.
This audio power amplifier is capable of delivering
1.2 W of continuous RMS output power into an
8 load at 5 V.
An externally controlled standby mode reduces
the supply current to less than 10 nA. It also
includes an internal thermal shutdown protection.
The unity-gain stable amplifier can be configured
by external gain setting resistors.
STANDBY
BYPASS
VIN+
VIN–
1
2
3
4
VOUT2
GND
VCC
VOUT1
6
8
7
5
Vin- GND BYPASS
VOUT2
VCC
Vin+
VOUT1 GND
STBY
Vin- GND BYPASS
VOUT2
VCC
Vin+
VOUT1 GND
STBY
STBY
BYPASS
VIN+
VIN- VOUT1
V
GND
VOUT2
1
2
3
4
8
5
7
6CC
STBY
BYPASS
VIN+
VIN- VOUT1
V
GND
VOUT2
1
2
3
4
8
5
7
6CC
TS4990EIJT - Flip-chip 9 bumps
TS4990IST - MiniSO-8
TS4990IQT - DFN8
TS4990IDT - SO-8
www.st.com
Contents TS4990
2/33 DocID9309 Rev 14
Contents
1 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3
2 Typical application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 BTL configuration principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Gain in a typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Low and high frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4 Power dissipation and efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5 Decoupling of the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 Wake-up time (tWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7 Standby time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8 Pop performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.9 Application example: differential input, BTL power amplifier . . . . . . . . . . 23
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Flip-chip package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 MiniSO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3 DFN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID9309 Rev 14 3/33
TS4990 Absolute maximum ratings and operating conditions
33
1 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
Symbol Parameter Value Unit
VCC Supply voltage (1) 6V
Vin Input voltage (2) GND to VCC V
Toper Operating free-air temperature range -40 to + 85 °C
Tstg Storage temperature -65 to +150 °C
TjMaximum junction temperature 150 °C
Rthja
Thermal resistance junction to ambient
Flip-chip (3)
MiniSO-8
DFN8
250
215
120
°C/W
Pdiss Power dissipation Internally limited
ESD HBM: Human body model (4)
MM: Machine model (5) 2
200 kV
V
Latch-up immunity 200 mA
Lead temperature (soldering, 10 sec)
Lead temperature (soldering, 10 sec) for lead-free version 250
260 °C
1. All voltage values are measured with respect to the ground pin.
2. The magnitude of the input signal must never exceed VCC + 0.3 V / GND - 0.3 V.
3. The device is protected in case of over temperature by a thermal shutdown active at 150° C.
4. Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kresistor
between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating.
5. Machine model: A 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the
device with no external series resistor (internal resistor < 5 ). This is done for all couples of connected pin combinations
while the other pins are floating.
Table 2. Operating conditions
Symbol Parameter Value Unit
VCC Supply voltage 2.2 to 5.5 V
Vicm Common mode input voltage range 1.2V to VCC V
VSTBY
Standby voltage input:
Device ON
Device OFF 1.35 V
STBY V
CC
GND VSTBY 0.4 V
RLLoad resistor 4
TSD Thermal shutdown temperature 150 °C
Rthja
Thermal resistance junction to ambient
Flip-chip (1)
MiniSO-8
DFN8 (2)
100
190
40
°C/W
1. This thermal resistance is reached with a 100 mm2 copper heatsink surface.
2. When mounted on a 4-layer PCB.
6—H
Typical application schematics TS4990
4/33 DocID9309 Rev 14
2 Typical application schematics
Figure 1. Typical application schematics
Table 3. Component descriptions
Component Functional description
Rin Inverting input resistor that sets the closed loop gain in conjunction with Rfeed. This
resistor also forms a high pass filter with Cin (Fc = 1 / (2 x Pi x Rin x Cin)).
Cin Input coupling capacitor that blocks the DC voltage at the amplifier input terminal.
Rfeed Feed back resistor that sets the closed loop gain in conjunction with Rin.
CsSupply bypass capacitor that provides power supply filtering.
CbBypass pin capacitor that provides half supply filtering.
Cfeed Low pass filter capacitor allowing to cut the high frequency (low pass filter cut-off
frequency 1/ (2 x Pi x Rfeed x Cfeed)).
AVClosed loop gain in BTL configuration = 2 x (Rfeed / Rin).
Exposed pad DFN8 exposed pad is electrically connected to pin 7. See DFN8 package
information on page 29 for more information.
Rfeed
Rin
Audio In
Cfeed Vcc
Cin
+
Cs
+
Cb
Standby
Control
Speaker
8Ohms
Bias
AV = -1
Vin-
Vin+
Bypass
Standby
VCC
GND
Vout 1
Vout 2
+
-
+
-
TS4990
DocID9309 Rev 14 5/33
TS4990 Electrical characteristics
33
3 Electrical characteristics
Table 4. Electrical characteristics when VCC = +5 V, GND = 0 V, Tamb = 25°C (unless
otherwise specified)
Symbol Parameter Min. Typ. Max. Unit
ICC Supply current
No input signal, no load 3.7 6 mA
ISTBY Standby current (1)
No input signal, VSTBY = GND, RL = 8 
1. Standby mode is active when VSTBY is tied to GND.
10 1000 nA
Voo Output offset voltage
No input signal, RL = 8 110mV
Pout Output power
THD = 1% max, F = 1 kHz, RL = 8 0.9 1.2 W
THD + N Total harmonic distortion + noise
Pout = 1Wrms, AV = 2, 20 Hz F 20 kHz, RL = 8 0.2 %
PSRR
Power supply rejection ratio (2)
RL = 8 AV = 2Vripple = 200mVpp, input grounded
F = 217 Hz
F = 1 kHz
2. All PSRR data limits are guaranteed by production sampling tests.
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon
VCC.
55
55 62
64
dB
tWU Wake-up time (Cb = 1 µF) 90 130 ms
tSTBY Standby time (Cb = 1 µF) 10 µs
VSTBYH Standby voltage level high 1.3 V
VSTBYL Standby voltage level low 0.4 V
MPhase margin at unity gain
RL = 8 , CL = 500 pF 65 Degrees
GM Gain margin
RL = 8 , CL = 500 pF 15 dB
GBP Gain bandwidth product
RL = 8 1.5 MHz
ROUT-GND
Resistor output to GND (VSTBY VSTBYL)
Vout1
Vout2
3
43 k
Electrical characteristics TS4990
6/33 DocID9309 Rev 14
Table 5. Electrical characteristics when VCC = +3.3 V, GND = 0 V, Tamb = 25°C (unless
otherwise specified)
Symbol Parameter Min. Typ. Max. Unit
ICC Supply current
No input signal, no load 3.3 6 mA
ISTBY Standby current (1)
No input signal, VSTBY = GND, RL = 8 
1. Standby mode is active when VSTBY is tied to GND.
10 1000 nA
Voo Output offset voltage
No input signal, RL = 8 110mV
Pout Output power
THD = 1% max, F = 1 kHz, RL = 8 375 500 mW
THD + N Total harmonic distortion + noise
Pout = 400 mWrms, AV = 2, 20 Hz F 20 kHz,
RL=8
0.1 %
PSRR
Power supply rejection ratio (2)
RL = 8 AV = 2Vripple = 200mVpp, input grounded
F = 217 Hz
F = 1 kHz
2. All PSRR data limits are guaranteed by production sampling tests.
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon
VCC.
55
55 61
63
dB
tWU Wake-up time (Cb = 1 µF) 110 140 ms
tSTBY Standby time (Cb = 1 µF) 10 µs
VSTBYH Standby voltage level high 1.2 V
VSTBYL Standby voltage level low 0.4 V
MPhase margin at unity gain
RL = 8 , CL = 500 pF 65 Degrees
GM Gain margin
RL = 8 , CL = 500 pF 15 dB
GBP Gain bandwidth product
RL = 8 1.5 MHz
ROUT-GND
Resistor output to GND (VSTBY V
STBYL)
Vout1
Vout2
4
44 k
DocID9309 Rev 14 7/33
TS4990 Electrical characteristics
33
Table 6. Electrical characteristics when VCC = 2.6V, GND = 0V, Tamb = 25°C (unless
otherwise specified)
Symbol Parameter Min. Typ. Max. Unit
ICC Supply current
No input signal, no load 3.1 6 mA
ISTBY Standby current (1)
No input signal, VSTBY = GND, RL = 8
1. Standby mode is active when VSTBY is tied to GND.
10 1000 nA
Voo Output offset voltage
No input signal, RL = 8 110mV
Pout Output power
THD = 1% max, F = 1 kHz, RL = 8 220 300 mW
THD + N Total harmonic distortion + noise
Pout = 200 mWrms, AV = 2, 20 Hz F 20 kHz,
RL=8
0.1 %
PSRR
Power supply rejection ratio (2)
RL = 8 AV = 2Vripple = 200 mVpp, input grounded
F = 217 Hz
F = 1 kHz
2. All PSRR data limits are guaranteed by production sampling tests.
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon
VCC.
55
55 60
62
dB
tWU Wake-up time (Cb = 1 µF) 125 150 ms
tSTBY Standby time (Cb = 1 µF) 10 µs
VSTBYH Standby voltage level high 1.2 V
VSTBYL Standby voltage level low 0.4 V
MPhase margin at unity gain
RL = 8 , CL = 500 pF 65 Degrees
GM Gain margin
RL = 8 , CL = 500 pF 15 dB
GBP Gain bandwidth product
RL = 8 1.5 MHz
ROUT-GND
Resistor output to GND (VSTBY VSTBYL)
Vout1
Vout2
6
46 k
Electrical characteristics TS4990
8/33 DocID9309 Rev 14
Figure 2. Open loop frequency response
VCC = 5 V Figure 3. Open loop frequency response
VCC = 3.3 V
0.1 1 10 100 1000 10000
-60
-40
-20
0
20
40
60
-200
-160
-120
-80
-40
0
Gain
Phase
Gain (dB)
Frequency (kHz)
Vcc = 5V
RL = 8Ω
Tamb = 25°C
Phase (°)
0.1 1 10 100 1000 10000
-60
-40
-20
0
20
40
60
-200
-160
-120
-80
-40
0
Gain
Phase
Gain (dB)
Frequency (kHz)
Vcc = 3.3V
RL = 8Ω
Tamb = 25°C
Phase (°)
Figure 4. Open loop frequency response
VCC = 2.6 V Figure 5. Open loop frequency response
CL = 560 pF
0.1 1 10 100 1000 10000
-60
-40
-20
0
20
40
60
-200
-160
-120
-80
-40
0
Gain
Phase
Gain (dB)
Frequency (kHz)
Vcc = 2.6V
RL = 8Ω
Tamb = 25°C
Phase (°)
0.1 1 10 100 1000 10000
-40
-20
0
20
40
60
80
100
-200
-160
-120
-80
-40
0
Gain
Phase
Gain (dB)
Frequency (kHz)
Vcc = 5V
CL = 560pF
Tamb = 25°C
Phase (°)
Figure 6. Open loop frequency response
VCC = 3.3 V, CL 560 PF Figure 7. Open loop frequency response
VCC = 2.6 V, CL 560 PF
0.1 1 10 100 1000 10000
-40
-20
0
20
40
60
80
100
-200
-160
-120
-80
-40
0
Gain
Phase
Gain (dB)
Frequency (kHz)
Vcc = 3.3V
CL = 560pF
Tamb = 25°C
Phase (°)
0.1 1 10 100 1000 10000
-40
-20
0
20
40
60
80
100
-200
-160
-120
-80
-40
0
Gain
Phase
Gain (dB)
Frequency (kHz)
Vcc = 2.6V
CL = 560pF
Tamb = 25°C
Phase (°)
DocID9309 Rev 14 9/33
TS4990 Electrical characteristics
33
Figure 8. PSRR vs. power supply Av = 2 Figure 9. PSRR vs. power supply Av = 10
100 1000 10000 100000
-70
-60
-50
-40
-30
-20
-10
0
Vcc :
2.2V
2.6V
3.3V
5V
Vripple = 200mVpp
Av = 2
Input = Grounded
Cb = Cin = 1
μ
F
RL >= 4
Ω
Tamb = 25
°
C
PSRR (dB)
Frequency (Hz)
Figure 10. PSRR vs. power supply Figure 11. PSRR vs. power supply Av = 5
100 1000 10000 100000
-80
-70
-60
-50
-40
-30
-20
-10
0
Vcc = 2.2, 2.6, 3.3, 5V
Vripple = 200mVpp
Rfeed = 22k
Ω
Input = Floating
Cb = 1
μ
F
RL >= 4
Ω
Tamb = 25
°
C
PSRR (dB)
Frequency (Hz)
Figure 12. PSRR vs. power supply Cb = 0.1 µF,
Cin = 1 µF Figure 13. PSRR vs. power supply
Rfeed = 22 k
100 1000 10000 100000
-60
-50
-40
-30
-20
-10
0
Vcc = 5, 3.3, 2.5 & 2.2V
Vripple = 200mVpp
Av = 2
Input = Grounded
Cb = 0.1
μ
F, Cin = 1
μ
F
RL >= 4
Ω
Tamb = 25
°
C
PSRR (dB)
Frequency (Hz)
Electrical characteristics TS4990
10/33 DocID9309 Rev 14
Figure 14. PSRR vs. DC output voltage Av = 2 Figure 15. PSRR vs. DC output voltage Av = 10
-5-4-3-2-1012345
-70
-60
-50
-40
-30
-20
-10
0
Vcc = 5V
Vripple = 200mVpp
RL = 8
Ω
Cb = 1
μ
F
AV = 2
Tamb = 25
°
C
PSRR (dB)
Differential DC Output Voltage (V)
-5-4-3-2-1012345
-50
-40
-30
-20
-10
0
Vcc = 5V
Vripple = 200mVpp
RL = 8
Ω
Cb = 1
μ
F
AV = 10
Tamb = 25
°
C
PSRR (dB)
Differential DC Output Voltage (V)
Figure 16. PSRR vs. DC output voltage Av = 5 Figure 17. PSRR vs. DC output voltage
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
-60
-50
-40
-30
-20
-10
0
Vcc = 3.3V
Vripple = 200mVpp
RL = 8
Ω
Cb = 1
μ
F
AV = 5
Tamb = 25
°
C
PSRR (dB)
Differential DC Output Voltage (V)
-5-4-3-2-1012345
-60
-50
-40
-30
-20
-10
0
Vcc = 5V
Vripple = 200mVpp
RL = 8
Ω
Cb = 1
μ
F
AV = 5
Tamb = 25
°
C
PSRR (dB)
Differential DC Output Voltage (V)
Figure 18. PSRR vs. DC output voltage
Cb = 1 µF Figure 19. PSRR vs. DC output voltage
Vcc = 3.3 V
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
-70
-60
-50
-40
-30
-20
-10
0Vcc = 3.3V
Vripple = 200mVpp
RL = 8
Ω
Cb = 1
μ
F
AV = 2
Tamb = 25
°
C
PSRR (dB)
Differential DC Output Voltage (V)
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
-50
-40
-30
-20
-10
0
Vcc = 3.3V
Vripple = 200mVpp
RL = 8
Ω
Cb = 1
μ
F
AV = 10
Tamb = 25
°
C
PSRR (dB)
Differential DC Output Voltage (V)
DocID9309 Rev 14 11/33
TS4990 Electrical characteristics
33
Figure 20. PSRR vs. DC output voltage
Vcc=2.6V Figure 21. PSRR vs. DC output voltage
Tamb = 25 °C
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
-70
-60
-50
-40
-30
-20
-10
0Vcc = 2.6V
Vripple = 200mVpp
RL = 8
Ω
Cb = 1
μ
F
AV = 2
Tamb = 25
°
C
PSRR (dB)
Differential DC Output Voltage (V)
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
-50
-40
-30
-20
-10
0Vcc = 2.6V
Vripple = 200mVpp
RL = 8
Ω
Cb = 1
μ
F
AV = 10
Tamb = 25
°
C
PSRR (dB)
Differential DC Output Voltage (V)
Figure 22. Output power vs. power supply
voltage Figure 23. PSRR vs. DC output voltage
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
THD+N=10%
RL = 4
Ω
F = 1kHz
BW < 125kHz
Tamb = 25
°
C
THD+N=1%
Output power (W)
Vcc (V)
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
-60
-50
-40
-30
-20
-10
0Vcc = 2.6V
Vripple = 200mVpp
RL = 8
Ω
Cb = 1
μ
F
AV = 5
Tamb = 25
°
C
PSRR (dB)
Differential DC Output Voltage (V)
Figure 24. PSRR at F = 217 Hz vs. bypass
capacitor Figure 25. Output power vs. power supply
voltage RL=8
0.1 1
-80
-70
-60
-50
-40
-30 Av=10
Vcc:
2.6V
3.3V
5V
Av=5
Vcc:
2.6V
3.3V
5V
Av=2
Vcc:
2.6V
3.3V
5V
Tamb=25
°
C
PSRR at 217Hz (dB)
Bypass Capacitor Cb ( F)
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
THD+N=10%
RL = 8
Ω
F = 1kHz
BW < 125kHz
Tamb = 25
°
C
THD+N=1%
Output power (W)
Vcc (V)
Electrical characteristics TS4990
12/33 DocID9309 Rev 14
Figure 26. Output power vs. power supply
voltage RL=16
Figure 27. Output power vs. load resistor
Vcc = 5 V
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
THD+N=10%
RL = 16
Ω
F = 1kHz
BW < 125kHz
Tamb = 25
°
C
THD+N=1%
Output power (W)
Vcc (V)
4 8 12 16 20 24 28 32
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
THD+N=10%
Vcc = 5V
F = 1kHz
BW < 125kHz
Tamb = 25
°
C
THD+N=1%
Output power (W)
Load Resistance ( )
Figure 28. Output power vs. load resistor
Vcc=2.6V Figure 29. Output power vs. power supply
voltage
4 8 12 16 20 24 28 32
0.0
0.1
0.2
0.3
0.4
0.5
0.6
THD+N=10%
Vcc = 2.6V
F = 1kHz
BW < 125kHz
Tamb = 25
°
C
THD+N=1%
Output power (W)
Load Resistance ( )
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
0.1
0.2
0.3
0.4
0.5
0.6
THD+N=10%
RL = 32
Ω
F = 1kHz
BW < 125kHz
Tamb = 25
°
C
THD+N=1%
Output power (W)
Vcc (V)
Figure 30. Output power vs. load resistor
Vcc=3.3V Figure 31. Power dissipation vs. Pout,
Vcc = 5 V
8 162432
0.0
0.2
0.4
0.6
0.8
1.0
THD+N=10%
Vcc = 3.3V
F = 1kHz
BW < 125kHz
Tamb = 25
°
C
THD+N=1%
Output power (W)
Load Resistance ( )
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
RL=16
Ω
RL=8
Ω
Vcc=5V
F=1kHz
THD+N<1% RL=4
Ω
Power Dissipation (W)
Output Power (W)
DocID9309 Rev 14 13/33
TS4990 Electrical characteristics
33
Figure 32. Power dissipation vs. Pout
Vcc=3.3V Figure 33. Power derating curves
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
RL=4
Ω
RL=8
Ω
Vcc=3.3V
F=1kHz
THD+N<1%
RL=16
Ω
Power Dissipation (W)
Output Power (W)
0 25 50 75 100 125 150
0.0
0.2
0.4
0.6
0.8
1.0
1.2
No Heat sink
Heat sink surface
≈
100mm
2
(See demoboard)
Flip-Chip Package Power Dissipation (W)
Ambiant Temperature ( C)
Figure 34. Clipping voltage vs. power supply
voltage and load resistor Figure 35. Power dissipation vs. Pout,
Vcc = 2.6 V
2.5 3.0 3.5 4.0 4.5 5.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7 Tamb = 25°C
RL = 16Ω
RL = 8Ω
RL = 4Ω
Vout1 & Vout2
Clipping Voltage Low side (V)
Power supply Voltage (V)
0.0 0.1 0.2 0.3 0.4
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
RL=4
Ω
RL=8
Ω
Vcc=2.6V
F=1kHz
THD+N<1%
RL=16
Ω
Power Dissipation (W)
Output Power (W)
Figure 36. Clipping voltage vs. power supply
voltage and load resistor Tamb = 25 °C Figure 37. Current consumption vs. power
supply voltage
2.5 3.0 3.5 4.0 4.5 5.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6 Tamb = 25
°
C
RL = 16
Ω
RL = 8
Ω
RL = 4
Ω
Vout1 & Vout2
Clipping Voltage High side (V)
Power supply Voltage (V)
012345
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0 No load
Tamb=25°C
Current Consumption (mA)
Power Supply Voltage (V)
mums
Electrical characteristics TS4990
14/33 DocID9309 Rev 14
Figure 38. Current consumption vs. standby
voltage @ VCC = 5 V Figure 39. Current consumption vs. standby
voltage @ VCC = 2.6 V
012345
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Vcc = 5V
No load
Tamb=25
°
C
Current Consumption (mA)
Standby Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0 Vcc = 2.6V
No load
Tamb=25°C
Current Consumption (mA)
Standby Voltage (V)
Figure 40. THD + N vs. output power
RL = 4
Figure 41. Current consumption vs. standby
voltage @ VCC = 3.3 V
1E-3 0.01 0.1 1
0.1
1
10
Vcc=5V
Vcc=3.3V
Vcc=2.6V
Vcc=2.2V
RL = 4Ω
F = 20Hz
Av = 2
Cb = 1μF
BW < 125kHz
Tamb = 25°C
THD + N (%)
Output Power (W)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0 Vcc = 3.3V
No load
Tamb=25°C
Current Consumption (mA)
Standby Voltage (V)
Figure 42. Current consumption vs. standby
voltage @ VCC = 2.2 V Figure 43. THD + N vs. output power
RL = 8
0.0 0.5 1.0 1.5 2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0 Vcc = 2.2V
No load
Tamb=25
°
C
Current Consumption (mA)
Standby Voltage (V)
1E-3 0.01 0.1 1
0.01
0.1
1
10
Vcc=5V
Vcc=3.3V
Vcc=2.6V
Vcc=2.2V
RL = 8
Ω
F = 20Hz
Av = 2
Cb = 1
μ
F
BW < 125kHz
Tamb = 25
°
C
THD + N (%)
Output Power (W)
S2
DocID9309 Rev 14 15/33
TS4990 Electrical characteristics
33
Figure 44. THD + N vs. output power RL = 16 Figure 45. THD + N vs. output power Av = 2
1E-3 0.01 0.1 1
0.01
0.1
1
10
Vcc=5V
Vcc=3.3V
Vcc=2.6V
Vcc=2.2V
RL = 16
Ω
F = 20kHz
Av = 2
Cb = 1
μ
F
BW < 125kHz
Tamb = 25
°
C
THD + N (%)
Output Power (W)
1E-3 0.01 0.1 1
0.01
0.1
1
10
Vcc=5V
Vcc=3.3V
Vcc=2.6V
Vcc=2.2V
RL = 8
Ω
F = 1kHz
Av = 2
Cb = 1
μ
F
BW < 125kHz
Tamb = 25
°
C
THD + N (%)
Output Power (W)
Figure 46. THD + N vs. output power F = 20 kHz Figure 47. THD + N vs. output power F = 1 kHz
1E-3 0.01 0.1 1
0.1
1
10
Vcc=5V
Vcc=3.3V
Vcc=2.6V
Vcc=2.2V
RL = 4Ω
F = 20kHz
Av = 2
Cb = 1μF
BW < 125kHz
Tamb = 25°C
THD + N (%)
Output Power (W)
1E-3 0.01 0.1 1
0.1
1
10
Vcc=5V
Vcc=3.3V
Vcc=2.6V
Vcc=2.2V
RL = 4Ω
F = 1kHz
Av = 2
Cb = 1μF
BW < 125kHz
Tamb = 25°C
THD + N (%)
Output Power (W)
Figure 48. THD + N vs. output power Cb = 1 µF Figure 49. THD + N vs. output power
1E-3 0.01 0.1 1
0.01
0.1
1
10
Vcc=5V
Vcc=3.3V
Vcc=2.6V
Vcc=2.2V
RL = 16
Ω
F = 1kHz
Av = 2
Cb = 1
μ
F
BW < 125kHz
Tamb = 25
°
C
THD + N (%)
Output Power (W)
1E-3 0.01 0.1 1
0.1
1
10
Vcc=5VVcc=3.3V
Vcc=2.6V
Vcc=2.2V
RL = 8Ω
F = 20kHz
Av = 2
Cb = 1μF
BW < 125kHz
Tamb = 25°C
THD + N (%)
Output Power (W)
Electrical characteristics TS4990
16/33 DocID9309 Rev 14
Figure 50. THD + N vs. output power Figure 51. THD + N vs. frequency
1E-3 0.01 0.1 1
0.01
0.1
1
10
Vcc=5V
Vcc=3.3V
Vcc=2.6V
Vcc=2.2V
RL = 16
Ω
F = 20kHz
Av = 2
Cb = 1
μ
F
BW < 125kHz
Tamb = 25
°
C
THD + N (%)
Output Power (W)
100 1000 10000
0.01
0.1
Vcc=2.2V, Po=130mW
Vcc=5V, Po=1W
RL=8
Ω
Av=2
Cb = 1
μ
F
Bw < 125kHz
Tamb = 25
°
C
20k20
THD + N (%)
Frequency (Hz)
Figure 52. SNR vs. power supply with
unweighted filter (20 Hz to 20 kHz) Figure 53. THD + N vs. frequency
Po = 1.3 W
2.5 3.0 3.5 4.0 4.5 5.0
80
85
90
95
100
105
110
Av = 2
Cb = 1
μ
F
THD+N < 0.7%
Tamb = 25
°
C
RL=16
Ω
RL=4
Ω
RL=8
Ω
Signal to Noise Ratio (dB)
Power Supply Voltage (V)
100 1000 10000
0.1
1
Vcc=2.2V, Po=150mW
Vcc=5V, Po=1.3W
RL=4Ω
Av=2
Cb = 1μF
Bw < 125kHz
Tamb = 25°C
20k20
THD + N (%)
Frequency (Hz)
Figure 54. THD + N vs. frequency
Po = 1.3 W Figure 55. SNR vs. power supply with
unweighted filter (20 Hz to 20 kHz)
100 1000 10000
0.01
0.1
Vcc=2.2V, Po=100mW
Vcc=5V, Po=0.55W
RL=16Ω
Av=2
Cb = 1μF
Bw < 125kHz
Tamb = 25°C
20k20
THD + N (%)
Frequency (Hz)
2.5 3.0 3.5 4.0 4.5 5.0
70
75
80
85
90
95
Av = 10
Cb = 1
μ
F
THD+N < 0.7%
Tamb = 25
°
C
RL=16
Ω
RL=4
Ω
RL=8
Ω
Signal to Noise Ratio (dB)
Power Supply Voltage (V)
cm, 1 A Rm mums cm, 1 A Rm mums
DocID9309 Rev 14 17/33
TS4990 Electrical characteristics
33
Figure 56. Signal to noise ratio vs. power
supply with a weighted filter Av = 2 Figure 57. Output noise voltage device ON
2.5 3.0 3.5 4.0 4.5 5.0
80
85
90
95
100
105
110
Av = 2
Cb = 1
μ
F
THD+N < 0.7%
Tamb = 25
°
C
RL=16
Ω
RL=4
Ω
RL=8
Ω
Signal to Noise Ratio (dB)
Power Supply Voltage (V)
246810
10
15
20
25
30
35
40
45 Vcc=2.2V to 5.5V
Cb=1
μ
F
RL=8
Ω
Tamb=25
°
C
A Weighted Filter
Unweighted Filter
Output Noise Voltage ( Vrms)
Closed Loop Gain
Figure 58. Signal to noise ratio vs. power
supply with a weighted filter Av = 10 Figure 59. Output noise voltage device in
standby
2.5 3.0 3.5 4.0 4.5 5.0
70
75
80
85
90
95
100
Av = 10
Cb = 1
μ
F
THD+N < 0.7%
Tamb = 25
°
C
RL=16
Ω
RL=4
Ω
RL=8
Ω
Signal to Noise Ratio (dB)
Power Supply Voltage (V)
246810
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Vcc=2.2V to 5.5V
Cb=1
μ
F
RL=8
Ω
Tamb=25
°
C
A Weighted Filter
Unweighted Filter
Output Noise Voltage ( Vrms)
Closed Loop Gain
Application information TS4990
18/33 DocID9309 Rev 14
4 Application information
4.1 BTL configuration principle
The TS4990 is a monolithic power amplifier with a BTL output type. BTL (bridge tied load)
means that each end of the load is connected to two single-ended output amplifiers. Thus,
we have:
Single-ended output 1 = Vout1 = Vout (V)
Single-ended output 2 = Vout2 = -Vout (V)
and Vout1 - Vout2 = 2Vout (V)
The output power is:
For the same power supply voltage, the output power in BTL configuration is four times
higher than the output power in single-ended configuration.
4.2 Gain in a typical application
The typical application schematics are shown in Figure 1 on page 4.
In the flat region (no Cin effect), the output voltage of the first stage is (in Volts):
For the second stage: Vout2 = -Vout1 (V)
The differential output voltage is (in Volts):
The differential gain named gain (Gv) for more convenience is:
Vout2 is in phase with Vin and Vout1 is phased 180 with Vin. This means that the positive
terminal of the loudspeaker should be connected to Vout2 and the negative to Vout1.
4.3 Low and high frequency response
In the low frequency region, Cin starts to have an effect. Cin forms with Rin a high-pass filter
with a -3 dB cut-off frequency. FCL is in Hz.
In the high frequency region, you can limit the bandwidth by adding a capacitor (Cfeed) in
parallel with Rfeed. It forms a low-pass filter with a -3 dB cut-off frequency. FCH is in Hz.
Pout
2VoutRMS

2
RL
------------------------------
=
Vout1 V–in

Rfeed
Rin
--------------
=
Vout2 Vout1
–2Vin
Rfeed
Rin
--------------
=
Gv
Vout2 Vout1
–
Vin
---------------------------------- 2Rfeed
Rin
--------------
==
FCL 1
2RinCin
------------------------
=
FCH 1
2RfeedCfeed
-------------------------------------
=
in feed
DocID9309 Rev 14 19/33
TS4990 Application information
33
The graph in Figure 60 shows an example of Cin and Cfeed influence.
Figure 60. Frequency response gain vs. Cin and Cfeed
4.4 Power dissipation and efficiency
Hypotheses:
Load voltage and current are sinusoidal (Vout and Iout).
Supply voltage is a pure DC source (VCC).
The load can be expressed as:
and
and
Therefore, the average current delivered by the supply voltage is:
The power delivered by the supply voltage is:
10 100 1000 10000
-25
-20
-15
-10
-5
0
5
10
Rin = Rfeed = 22kΩ
Tamb = 25°C
Cfeed = 2.2nF
Cfeed = 680pF
Cfeed = 330pF
Cin = 470nF
Cin = 82nF
Cin = 22nF
Gain (dB)
Frequency (Hz)
Vout = VPEAK sint (V)
Iout = Vout
RL
------------- (A)
Pout = VPEAK 2
2RL
------------------------- (W)
ICCAVG = 2VPEAK
RL
---------------------- (A)
Psupply VCC ICCAVG (W)=
2V 2 VC 0 p “F
Application information TS4990
20/33 DocID9309 Rev 14
Therefore, the power dissipated by each amplifier is:
Pdiss = Psupply - Pout (W)
and the maximum value is obtained when:
and its value is:
Note: This maximum value is only dependent on power supply voltage and load values.
The efficiency is the ratio between the output power and the power supply:
The maximum theoretical value is reached when VPEAK = VCC, so:
4.5 Decoupling of the circuit
Two capacitors are needed to correctly bypass the TS4990: a power supply bypass
capacitor Cs and a bias voltage bypass capacitor Cb.
Cs has particular influence on the THD+N in the high frequency region (above 7 kHz) and an
indirect influence on power supply disturbances. With a value for Cs of 1 µF, you can expect
THD+N levels similar to those shown in the datasheet.
In the high frequency region, if Cs is lower than 1 µF, it increases THD+N and disturbances
on the power supply rail are less filtered.
On the other hand, if Cs is higher than 1 µF, those disturbances on the power supply rail are
more filtered.
Cb has an influence on THD+N at lower frequencies, but its function is critical to the final
result of PSRR (with input grounded and in the lower frequency region).
If Cb is lower than 1 µF, THD+N increases at lower frequencies and PSRR worsens.
If Cb is higher than 1 µF, the benefit on THD+N at lower frequencies is small, but the benefit
to PSRR is substantial.
Note that Cin has a non-negligible effect on PSRR at lower frequencies. The lower the value
of Cin, the higher the PSRR.
Pdiss
22V
CC
RL
---------------------- Pout Pout
–=
Pdiss
Pout
------------------ = 0
Pdissmax
2VCC
2
2RL
--------------- (W)=
= Pout
Psupply
------------------- = VPEAK
4VCC
-----------------------
4
----- = 78.5%
mums
DocID9309 Rev 14 21/33
TS4990 Application information
33
4.6 Wake-up time (tWU)
When the standby is released to put the device ON, the bypass capacitor Cb is not charged
immediately. Because Cb is directly linked to the bias of the amplifier, the bias will not work
properly until the Cb voltage is correct. The time to reach this voltage is called wake-up time
or tWU and specified in the electrical characteristics tables with Cb=1µF.
If Cb has a value other than 1 µF, refer to the graph in Figure 61 to establish the wake-up
time.
Figure 61. Typical wake-up time vs. Cb
Due to process tolerances, the maximum value of wake-up time is shown in Figure 62.
Figure 62. Maximum wake-up time vs. Cb
Note: The bypass capacitor Cb also has a typical tolerance of +/-20%. To calculate the wake-up
time with this tolerance, refer to the graph above (considering for example for Cb=1 µF in
the range of 0.8 µF
Cb
1.2 µF).
4.7 Standby time
When the standby command is set, the time required to put the two output stages in high
impedance and the internal circuitry in standby mode is a few microseconds. In standby
mode, the bypass pin and Vin pin are short-circuited to ground by internal switches. This
allows a quick discharge of Cb and Cin capacitors.
1234
0
100
200
300
400
500
600
4.7
0.1
Tamb=25°C
Vcc=2.6V
Vcc=3.3V
Vcc=5V
Startup Time (ms)
Bypass Capacitor Cb ( F)
1234
0
100
200
300
400
500
600 Tamb=25
°
C
4.70.1
Vcc=5V
Vcc=3.3V
Vcc=2.6V
Max. Startup Time (ms)
Bypass Capacitor Cb ( F)
Application information TS4990
22/33 DocID9309 Rev 14
4.8 Pop performance
Pop performance is intimately linked with the size of the input capacitor Cin and the bias
voltage bypass capacitor Cb.
The size of Cin is dependent on the lower cut-off frequency and PSRR values requested.
The size of Cb is dependent on THD+N and PSRR values requested at lower frequencies.
Moreover, Cb determines the speed with which the amplifier turns ON. In order to reach
near zero pop and click, the equivalent input constant time,
in = (Rin + 2 k)xC
in (s) with Rin 5 k
must not reach the in maximum value as indicated in Figure 63 below.
Figure 63. in max. versus bypass capacitor
By following the previous rules, the TS4990 can reach near zero pop and click even with
high gains such as 20 dB.
Example:
With Rin =22k and a 20 Hz, -3 dB low cut-off frequency, Cin =361nF. So, C
in =390nF
with standard value which gives a lower cut-off frequency equal to 18.5 Hz. In this case,
(Rin +2k)xC
in = 9.36 ms. By referring to the previous graph, if Cb= 1 µF and VCC =5V,
we read 20 ms max. This value is twice as high as our current value, thus we can state that
pop and click will be reduced to its lowest value.
Minimizing both Cin and the gain benefits both the pop phenomenon, and the cost and size
of the application.
1234
0
40
80
120
160
Vcc=5V
Vcc=3.3V
Vcc=2.6V
Tamb=25
°
C
in max. (ms)
Bypass Capacitor Cb ( F)
4—H
DocID9309 Rev 14 23/33
TS4990 Application information
33
4.9 Application example: differential input, BTL power amplifier
The schematics in Figure 64 show how to configure the TS4990 to work in differential input
mode. The gain of the amplifier is:
In order to reach the best performance of the differential function, R1 and R2 should be
matched at 1% max.
Figure 64. Differential input amplifier configuration
The input capacitor Cin can be calculated by the following formula using the -3 dB lower
frequency required. (FL is the lower frequency required).
Note: This formula is true only if:
is 5 times lower than FL.
GVDIFF 2R2
R1
-------
=
R2
R1
Neg. Input
Vcc
Cin
+
Cs
+
Cb
Standby
Control
Speaker
8Ohms
Bias
AV = -1
Vin-
Vin+
Bypass
Standby
VCC
GND
Vout 1
Vout 2
+
-
+
-
TS4990
R1
Pos. Input
Cin
R2
Cin 1
2R1FL
--------------------- (F)
FCB 1
2R1R2
+CB
---------------------------------------- (Hz)=
Application information TS4990
24/33 DocID9309 Rev 14
Example bill of materials
The bill of materials in Table 7 is for the example of a differential amplifier with a gain of 2
and a -3 dB lower cut-off frequency of about 80 Hz.
Table 7. Bill of materials for differential input amplifier application
Pin name Functional description
R120k / 1%
R220k / 1%
Cin 100 nF
Cb=Cs1 µF
U1 TS4990
DocID9309 Rev 14 25/33
TS4990 Package information
33
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.1 Flip-chip package information
Figure 65. Flip-chip pinout (top view)
Figure 66. Marking (top view)
AC
B
1
2
3
Vin- GND BYPASS
VOUT2
VCC
Vin+
VOUT1 GND
STBY
AC
B
1
2
3
Vin- GND BYPASS
VOUT2
VCC
Vin+
VOUT1 GND
STBY
Vin- GND BYPASS
VOUT2
VCC
Vin+
VOUT1 GND
STBY
Balls are underneath
XXX
YWW
E
XXX
YWW
E
ST logo
Product and assembly code:
XXX
A90 from Tours
90S from Shenzhen
Three-digit datecode: YWW
E symbol for lead-free only
Symbol for
lead-free
Package information TS4990
26/33 DocID9309 Rev 14
Figure 67. Package mechanical data for 9-bump flip-chip package
Figure 68. Daisy chain mechanical data
The daisy chain sample features two-by-two pin connections. The schematics in Figure 68
illustrate the way pins connect to each other. This sample is used to test continuity on your
board. Your PCB needs to be designed the opposite way, so that pins that are unconnected
in the daisy chain sample, are connected on your PCB. If you do this, by simply connecting
an Ohmmeter between pin A1 and pin A3, the soldering process continuity can be tested.
Die size: 1.60 x 1.60 mm ±30µm
Die height (including bumps): 600µm
Bump diameter: 315µm ±50µm
Bump diameter before reflow: 300µm
±10µm
Bump height: 250µm ±40µm
Die height: 350µm ±20µm
Pitch: 500µm ±50µm
Coplanarity: 50µm max
1.60 mm
1.60 mm
0.5mm
0.5mm
0.25mm
1.60 mm
1.60 mm
0.5mm
0.5mm
0.25mm
600µm
100µm
600µm
100µm
AC
B
1
2
3
1.6mm
1.6mm
AC
B
1
2
3
1.6mm
1.6mm
DocID9309 Rev 14 27/33
TS4990 Package information
33
Figure 69. TS4990 footprint recommendations
Figure 70. Tape and reel specification (top view)
Device orientation
The devices are oriented in the carrier pocket with pin number A1 adjacent to the sprocket
holes.
Pad in Cu 18m with Flash NiAu (2-6m, 0.2m max.)
150m min.
500m
500m
500m
500m
=250m
=400m typ.
75µm min.
100m max.
Track
Non Solder mask opening
=340m min.
Pad in Cu 18m with Flash NiAu (2-6m, 0.2m max.)
150m min.
500m
500m
500m
500m
=250m
=400m typ.
75µm min.
100m max.
Track
Non Solder mask opening
=340m min.
User direction of feed
A
1
A
1
8
Die size X + 70µm
Die size Y + 70µm
41.5
4
All dimensions are in mm
User direction of feed
A
1
A
1
A
1
A
1
8
Die size X + 70µm
Die size Y + 70µm
41.5
4
All dimensions are in mm
wmammm V Ni
Package information TS4990
28/33 DocID9309 Rev 14
5.2 MiniSO-8 package information
Figure 71. MiniSO-8 package mechanical drawing
Table 8. MiniSO-8 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.1 0.043
A1 0 0.15 0 0.006
A2 0.75 0.85 0.95 0.030 0.033 0.037
b 0.22 0.40 0.009 0.016
c 0.08 0.23 0.003 0.009
D 2.80 3.00 3.20 0.11 0.118 0.126
E 4.65 4.90 5.15 0.183 0.193 0.203
E1 2.80 3.00 3.10 0.11 0.118 0.122
e 0.65 0.026
L 0.40 0.60 0.80 0.016 0.024 0.031
L1 0.95 0.037
L2 0.25 0.010
k0° 8°0° 8°
ccc 0.10 0.004
DocID9309 Rev 14 29/33
TS4990 Package information
33
5.3 DFN8 package information
Note: DFN8 exposed pad (E2 x D2) is connected to pin number 7. For enhanced thermal
performance, the exposed pad must be soldered to a copper area on the PCB, acting as a
heatsink. This copper area can be electrically connected to pin7 or left floating.
Figure 72. DFN8 3x3x0.90 mm package mechanical drawing (pitch 0.5 mm)
Table 9. DFN8 3x3x0.90 mm package mechanical data (pitch 0.5 mm)
Ref.
Dimensions
Millimeters Mils
Min. Typ. Max. Min. Typ. Max.
A 0.80 0.90 1.00 31.5 35.4 39.4
A1 0.02 0.05 0.8 2.0
A2 0.55 0.65 0.80 217 25.6 31.5
A3 0.20 7.9
b 0.18 0.25 0.30 7.1 9.8 11.8
D 2.85 3.00 3.15 112.2 118.1 124
D2 2.20 2.70 86.6 106.3
E 2.85 3.00 3.15 112.2 118.1 124
E2 1.40 1.75 55.1 68.9
e 0.50 19.7
L 0.30 0.40 0.50 11.8 15.7 19.7
ddd 0.08 3.1
ddd
D
D2
E
A3
A
e
C
C
E2
PLANE
SEATING
BOTTOM VIEW
b
58
1
A2
A1
L
234
67
0.15x45°
7426334_F
5mm; PLANE
Package information TS4990
30/33 DocID9309 Rev 14
5.4 SO-8 package information
Figure 73. SO-8 package mechanical drawing
Table 10. SO-8 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A1.750.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.010
D 4.80 4.90 5.00 0.189 0.193 0.197
H 5.80 6.00 6.20 0.228 0.236 0.244
E1 3.80 3.90 4.00 0.150 0.154 0.157
e 1.27 0.050
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
k1° 8°1° 8°
ccc 0.10 0.004
DocID9309 Rev 14 31/33
TS4990 Ordering information
33
6 Ordering information
Table 11. Order codes
Order code Temp. range Package Packing Marking
TS4990EIJT (1)
1. Lead-free Flip-chip part number
-40°C, +85°C
Flip-chip, 9 bumps Tape & reel 90
TS4990IST MiniSO-8 Tape & reel K990
TS4990IQT DFN8 Tape & reel K990
TS4990IDT SO-8 Tape & reel TS4990I
Revision history TS4990
32/33 DocID9309 Rev 14
7 Revision history
Table 12. Document revision history
Date Revision Changes
1-Jul-2002 1 First release.
4-Sep-2003 2 Update mechanical data.
1-Oct-2004 3 Order code for back coating on flip-chip.
2-Apr-2005 4 Typography error on page 1: Mini-SO-8 pin connection.
May-2005 5 New marking for assembly code plant.
1-Jul-2005 6 Error on Table 4 on page 5. Parameters in wrong column.
28-Sep-2005 7 Updated mechanical coplanarity data to 50 µm (instead of 60 µm) (see
Figure 67 on page 25).
14-Mar-2006 8 SO-8 package inserted in the datasheet.
21-Jul-2006 9 Update of Figure 66 on page 25. Disclaimer update.
11-May-2007 10
Corrected value of PSRR in Table 5 on page 6 from 1 to 61 (typical value).
Moved Table 3: Component descriptions to Section 2: Typical application
schematics on page 4.
Merged daisy chain flip-chip order code table into Table 11: Order codes
on page 31.
17-Jan-2008 11
Corrected pitch error in DFN8 package information. Actual pitch is 0.5mm.
Updated DFN8 package dimensions to correspond to JEDEC databook
definition (in previous versions of datasheet, package dimensions were as
in manufacturer’s drawing).
Corrected error in MiniSO-8 package information (L and L1 values were
inverted).
Reformatted package information.
21-May-2008 12 Corrected value of output resistance vs. ground in standby mode:
removed from Table 2, and added in Table 4, Table 5, and Table 6.
30-Aug-2011 13 Updated DFN8 package (Figure 72)
Updated ECOPACK® text in Section 5: Package information
17-Jan-2019 14 Updated Table 11: Order codes
DocID9309 Rev 14 33/33
TS4990
33
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