ICS570-01 Datasheet by Renesas Electronics America Inc.

40—4 ‘44

DATASHEET

PCI-EXPRESS GEN1 CLOCK SOURCE ICS557-01

IDT®

PCI-EXPRESS GEN1 CLOCK SOURCE 1

ICS557-01 REV P 072512

Description

The ICS557-01 is a clock chip designed for use in

PCI-Express Cards as a clock source. It provides a pair of

differential outputs at 100 MHz in a small 8-pin SOIC

package.

Using IDT’s patented Phase-Locked Loop (PLL)

techniques, the device takes a 25 MHz crystal input and

produces HCSL (Host Clock Signal Level) differential

outputs at 100 MHz clock frequency. LVDS signal levels can

also be supported via an alternative termination scheme.

Features

•Supports PCI-ExpressTM HCSL Outputs

0.7 V current mode differential pair

•Supports LVDS Output Levels

•Packaged in 8-pin SOIC

•RoHS 5 (green) or RoHS 6 (green and lead free)

compliant packaging

•Operating voltage of 3.3 V

•Low power consumption

•Input frequency of 25 MHz

•Short term jitter 100 ps (peak-to-peak)

•Output Enable via pin selection

•Industrial temperature range available

•For PCIe Gen2 applications, see the 5V41064

•For PCIe Gen3 applications, see the 5V41234

Block Diagram

Phase Lock

Loop

Clock

Buffer/

Crystal

Oscillator

VDD

GND

25 MHz

crystal /clock

CLK

RR(IREF)

Crystal Tuning Capacitors

jjjj EEC:

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PCI-EXPRESS GEN1 CLOCK SOURCE PCIE

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Pin Assignment

Pin Descriptions

VDD

IREF

GND

CLK

8 Pin (150 mil) SOIC

Number

Name

Type

Pin Description

1 OE Input Output Enable signal

(H = outputs are enabled, L = outputs are disabled/tristated).

Internal pull-up resistor.

2 X1 Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.

3 X2 XO Crystal Connection. Connect to a parallel mode crystal.

Leave floating if clock input.

4 GND Power Connect to ground.

5 IREF Output A 475Ω precision resistor connected between this pin and ground

establishes the external reference current.

6 CLK Output HCSL differential complementary clock output.

7 CLK Output HCSL differential clock output.

8 VDD Power Connect to +3.3 V.

ICS557-01

PCI-EXPRESS GEN1 CLOCK SOURCE PCIE

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Applications Information

External Components

A minimum number of external components are required for

proper operation.

Decoupling Capacitors

Decoupling capacitors of 0.01 μF should be connected

between VDD and the ground plane (pin 4) as close to the

VDD pin as possible. Do not share ground vias between

components. Route power from power source through the

capacitor pad and then into IDT pin.

Crystal

A 25 MHz fundamental mode parallel resonant crystal with

CL = 16 pF should be used. This crystal must have less than

300 ppm of error across temperature in order for the

ICS557-01 to meet PCI Express specifications.

Crystal Capacitors

Crystal capacitors are connected from pins X1 to ground

and X2 to ground to optimize the accuracy of the output

frequency.

CL= Crystal’s load capacitance in pF

Crystal Capacitors (pF) = (CL- 8) * 2

For example, for a crystal with a 16 pF load cap, each

external crystal cap would be 16 pF. (16-8)*2=16.

Current Source (Iref) Reference Resistor - RR

If board target trace impedance (Z) is 50Ω, then RR = 475Ω

(1%), providing IREF of 2.32 mA. The output current (IOH) is

equal to 6*IREF.

Output Termination

The PCI-Express differential clock outputs of the ICS557-01

are open source drivers and require an external series

resistor and a resistor to ground. These resistor values and

their allowable locations are shown in detail in the

PCI-Express Layout Guidelines section.

The ICS557-01can also be configured for LVDS compatible

voltage levels. See the LVDS Compatible Layout Guidelines

section

Output Structures

General PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

1. Each 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible.

2. No vias should be used between decoupling capacitor

and VDD pin.

3. The PCB trace to VDD pin should be kept as short as

possible, as should the PCB trace to the ground via.

Distance of the ferrite bead and bulk decoupling from the

device is less critical.

4. An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers (any ferrite beads and bulk decoupling capacitors can

be mounted on the back). Other signal traces should be

routed away from the ICS557-01.This includes signal traces

just underneath the device, or on layers adjacent to the

ground plane layer used by the device.

RR 475

6*IREF

=2.3 mA

IREF

See Output Termination

Sections - Pages 3 ~ 5

Common Reeoinmendniions for Differential Routing Dimension or anne Unit Figine Notes Rx RT Differential Routing on n Single PCB Dimension Ur VnIne Unit Figine Notes Dirreieniial Routing lo a PCI Expiess Connector Dimension Ur VnIne Unit Figine Notes

ICS557-01

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ICS557-01 REV P 072512

PCI-Express Layout Guidelines

Figure 1: PCI-Express Device Routing

Typical PCI-Express (HCSL) Waveform

Common Recommendations for Differential Routing Dimension or Value Unit Figure Notes

L1 length, Route as non-coupled 50 ohm trace. 0.5 max inch 1,2

L2 length, Route as non-coupled 50 ohm trace. 0.2 max inch 1,2

L3 length, Route as non-coupled 50 ohm trace. 0.2 max inch 1,2

RS 33 ohm 1,2

RT 49.9 ohm 1,2

Differential Routing on a Single PCB Dimension or Value Unit Figure Notes

L4 length, Route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch 1

L4 length, Route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch 1

Differential Routing to a PCI Express Connector Dimension or Value Unit Figure Notes

L4 length, Route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch 2

L4 length, Route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch 2

RTRT

PCI-Express

Load or

Connector

L1 L2

L3’

L1’ L2’

L4’

ICS557-01

Output

Cloc

0.175 V

0.52 V

0.175 V

0.52 V

tOR tOF

500 ps 500 ps

700 mV

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LVDS Compatible Layout Guidelines

Figure: LVDS Device Routing

Typical LVDS Waveform

Vdiff Vp-p Vcm R1 R2 R3 R4 Note

0.45v 0.22v 1.08 33 150 100 100

0.58 0.28 0.6 33 78.7 137 100

0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible

0.60 0.3 1.2 33 174 140 100 Standard LVDS

R1a = R1b = R1

R2a = R2b = R2

Alternative Termination for LVDS and other Common Differential Signals

HCSL Output Buffer

L1'

R1b

L2'

R1a

L4'

R2a R2b Down Device

REF_CLK Input

Figure 3

L3'

R3 R4

1150 mV

1250 mV

tOR tOF

500 ps 500 ps

1325 mV

1000 mV

1150 mV

1250 mV

ICS557-01

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Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS557-01. These ratings are stress

ratings only. Functional operation of the device at these or any other conditions above those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for

extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended

operating temperature range.

DC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C

1 Single edge is monotonic when transitioning through region.

2 Inputs with pull-ups/-downs are not included.

Item Rating

Supply Voltage, VDD, VDDA 5.5 V

All Inputs and Outputs -0.5 V to VDD+0.5 V

Ambient Operating Temperature (commercial) 0 to +70°C

Ambient Operating Temperature (industrial) -40 to +85°C

Storage Temperature -65 to +150°C

Junction Temperature 125°C

Soldering Temperature 260°C

ESD Protection (Input) 2000 V min. (HBM)

Parameter Symbol Conditions Min. Typ. Max. Units

Supply Voltage V 3.135 3.465

Input High Voltage1VIH 2.0 VDD +0.3 V

Input Low Voltage1VIL VSS-0.3 0.8 V

Input Leakage Current2IIL 0 < Vin < VDD -5 5 μA

Operating Supply Current IDD With 50Ω and 2 pF load 55 mA

IDDOE OE =Low 35 mA

Input Capacitance CIN Input pin capacitance 7 pF

Output Capacitance COUT Output pin capacitance 6 pF

Pin Inductance LPIN 5nH

Output Resistance Rout CLK outputs 3.0 kΩ

Pull-up Resistor RPUP OE 60 kΩ

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AC Electrical Characteristics - CLK/CLK

Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85°C

1 Test setup is RL=50 ohms with 2 pF, RR = 475Ω (1%).

2 Measurement taken from a single-ended waveform.

3 Measurement taken from a differential waveform.

4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.

5 CLKOUT pins are tri-stated when OE is low asserted. CLKOUT is driven differential when OE is high.

Thermal Characteristics (8-pin SOIC)

Parameter Symbol Conditions Min. Typ. Max. Units

Input Frequency 25 MHz

Output Frequency 100 MHz

Output High Voltage1,2 VOH 660 700 850 mV

Output Low Voltage1,2 VOL -150 0 27 mV

Crossing Point

Voltage1,2 Absolute 250 350 550 mV

Crossing Point

Voltage1,2,4 Variation over all edges 140 mV

Jitter, Cycle-to-Cycle1,3 80 ps

Rise Time1,2 tOR From 0.175 V to 0.525 V 175 332 700 ps

Fall Time1,2 tOF From 0.525 V to 0.175 V 175 344 700 ps

Rise/Fall Time

Variation1,2 125 ps

Duty Cycle1,3 45 55 %

Output Enable Time5All outputs 30 µs

Output Disable Time5All outputs 30 µs

Stabilization Time tSTABLE From power-up VDD=3.3 V 3.0 ms

Parameter Symbol Conditions Min. Typ. Max. Units

Thermal Resistance Junction to

Ambient

θJA Still air 150 °C/W

θJA 1 m/s air flow 140 °C/W

θJA 3 m/s air flow 120 °C/W

Thermal Resistance Junction to Case θJC 40 °C/W

ICS557-01

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Marking Diagram (ICS557M-01LF) Marking Diagram (ICS557MI-01LF)

Notes:

1. “LOT” is the lot code.

2. YYWW is the last two digits of the year, and the week number that the part was assembled.

3. “L” or “LF” designates Pb (lead) free packaging.

4. “I” denotes industrial temperature.

5. Bottom marking: (origin). Origin = country of origin if not USA.

557M01LF

LOT

YYWW

557MI01L

LOT

YYWW

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Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)

Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes

no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No

other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications

such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not

recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT

does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

Part / Order Number Marking Shipping Packaging Package Temperature

557M-01LF See Page 8 Tubes 8-pin SOIC 0 to +70° C

557M-01LFT Tape and Reel 8-pin SOIC 0 to +70° C

557MI-01LF Tubes 8-pin SOIC -40 to +85° C

557MI-01LFT Tape and Reel 8-pin SOIC -40 to +85° C

INDEX

AREA

1 2

SEATING

PLANE

- C -

.10 (.004) C

h x 45

*For reference only. Controlling dimensions in mm.

Millimeters Inches*

Symbol Min Max Min Max

A 1.35 1.75 .0532 .0688

A1 0.10 0.25 .0040 .0098

B 0.33 0.51 .013 .020

C 0.19 0.25 .0075 .0098

D 4.80 5.00 .1890 .1968

E 3.80 4.00 .1497 .1574

e 1.27 BASIC 0.050 BASIC

H 5.80 6.20 .2284 .2440

h 0.25 0.50 .010 .020

L 0.40 1.27 .016 .050

°8°0°8°

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