DAC5681/81z/82z EVM Guide Datasheet by Texas Instruments

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User's GuideSLAU236A – November 2007 – Revised October 2008
DAC5681/81z/82z EVM
Contents1 Overview ...................................................................................................................... 31.1 Purpose .............................................................................................................. 31.2 EVM Basic Functions............................................................................................... 31.3 Power Requirements ............................................................................................... 32 Software Installation ......................................................................................................... 42.1 Minimum Requirements ............................................................................................ 42.2 Installing the EVM Control Software ............................................................................. 42.3 Installing the DAC5681/81z/82z EVM Instrument Drivers ..................................................... 52.4 Installing the DAC5681/81z/82z EVM Hardware ............................................................... 53 DAC5681/81z/82z EVM Description ...................................................................................... 63.1 Texas Instruments Components on the DAC5681/81z/82z EVM ............................................ 64 DAC5681/81Z/82z EVM Hardware Description .......................................................................... 74.1 Jumper Settings ..................................................................................................... 74.2 Input/Output Connectors ........................................................................................... 84.3 USB Interface ....................................................................................................... 84.4 Power Management ................................................................................................ 84.5 Input Connector .................................................................................................... 84.6 Clock Configuration ................................................................................................. 94.7 Output Configurations .............................................................................................. 94.8 Reference Operation .............................................................................................. 115 DAC5681/81z/82z EVM Software ........................................................................................ 125.1 Software Functionality Overview ................................................................................ 125.2 EVM Home Area .................................................................................................. 135.3 DAC Register Configuration and Block Diagram .............................................................. 155.4 CDCM7005 Register Configuration ............................................................................. 175.5 TSW3100 Configuration and Pattern Generation ............................................................. 195.6 Help ................................................................................................................. 206 DAC5681/81z/82z Initial Power Up and Test ........................................................................... 216.1 Test Setup Block Diagram ....................................................................................... 216.2 Test Equipment .................................................................................................... 216.3 Calibration .......................................................................................................... 216.4 Typical Performance Measurements ........................................................................... 226.5 DAC5681/81z/82z Test Procedure .............................................................................. 237 PC Board Layouts, Bill of Materials and Schematics .................................................................. 247.1 Board Layouts ..................................................................................................... 247.2 Bill of Materials .................................................................................................... 34
7.3 Schematics ......................................................................................................... 36
List of Figures
1 EVM Installation Wizard..................................................................................................... 42 Windows USB Driver Warning ............................................................................................. 53 Hardware Device Manager ................................................................................................. 54 Basic Radio System ......................................................................................................... 6
Microsoft Windows is a trademark of Microsoft, Inc.
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5 DAC5682z Option Block Diagram ......................................................................................... 66 DAC5682Z DAC Output Resistor Configuration ....................................................................... 107 DAC5682z RF Output Resistor Configuration .......................................................................... 108 Response of Default Baseband Filter ................................................................................... 119 EVM Home Displaying EVM Status Settings ........................................................................... 1310 DAC Block Diagram and Register Configuration Settings ............................................................ 1511 The CDCM7005 and DAC5682 Register Configuration Settings .................................................... 1712 TSW3100 Pattern Generator and DAC Register Configuration Settings .......................................... 1913 DAC5682z EVM Driven by TSW3100 Pattern Generator ............................................................. 2114 DAC5681/81z/82z EVM Transformer Output With a Low IF at 30.72 MHz ........................................ 2215 DAC5682z EVM output at RF LO + low IF of 30.72M (6 dB lower than DAC output) ............................ 2316 Silkscreen (top) ............................................................................................................. 2417 Layer 2 ....................................................................................................................... 2518 Layer 3 ....................................................................................................................... 2619 Layer 4 ....................................................................................................................... 2720 Layer 5 ....................................................................................................................... 2821 Layer 6 ....................................................................................................................... 2922 Layer 7 ....................................................................................................................... 3023 Layer 8 ....................................................................................................................... 3124 Layer 9 ....................................................................................................................... 3225 Screen (Bottom) ............................................................................................................ 33
List of Tables
1 Jumper List ................................................................................................................... 7
2 Input and Output Connectors .............................................................................................. 8
3 Input Connector .............................................................................................................. 8
4 Software Main Menu Selections .......................................................................................... 12
5 Software Area Descriptions ............................................................................................... 12
6 EVM Home Software Functionality....................................................................................... 14
7 DAC Register Configuration Software Functionality ................................................................... 15
8 CDCM7005 Register Configuration Software Functionality ........................................................... 18
9 TSW3100 Configuration and Pattern Generation Functionality ...................................................... 19
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I TEXAS INSTRUMENTS DAC5681 DAC5681Z DACSGBZZ DAC5681 , SLLSBG4 DAC5681Z , SLLSBBSA DA05682Z , SLLSBSSB
1 Overview
1.1 Purpose
1.2 EVM Basic Functions
1.3 Power Requirements
1.3.1 Voltage Limits
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Overview
The DAC5681/81z/82z EVM provides a platform for evaluating the DAC5681 ,DAC5681z and DAC5682zfamily of 16-bit, 1GSPS digital-to-analog converters (DAC) under various signal, reference, and supplyconditions. The evaluation module allows designers using the DAC5682z to analyze either atransformer-coupled output from the DAC or an RF-modulated output using Texas Instruments TRF3703analog quadrature modulator. The DAC5681 and DAC5681z options only allow the use of atransformer-coupled output. Use this document with the EVM schematic diagram and the correspondingdevice datasheet ( DAC5681 - SLLS864 ,DAC5681z - SLLS865A , and DAC5682z - SLLS853B ).
Digital inputs to the DAC can be provided with LVDS level signals up to 1 GSPS through a SEMTEKconnector compatible with various pattern generation solutions. The analog outputs from the DAC areavailable via SMA connectors. Because of its flexible design the analog outputs of the DAC device can beconfigured to drive a 50- Ωterminated cable using a 4:1 or 1:1 impedance ratio transformer, orsingle-ended referred to AVDD. The EVM also allows for an option to use Texas Instrument’s TRF3703analog quadrature modulator to mix the DAC outputs to RF. This option is only available when using theDAC5682z.
The EVM also includes a Texas Instrument’s CDCM7005 clock distribution device to clock the system.The CDCM7005 can be used in conjunction with an on-board VCXO for full PLL functionality or with anexternal signal source in which case the CDCM7005 functions as a buffer.
Power connections to the EVM are via banana jack sockets. In addition to the internal bandgap referenceprovided by the DAC devices, the EVM allows an external reference to be provided to the DAC.
The DAC5681/81z/82z EVM allows the user to program the DAC and CDCM7005 registers through aUSB port. The interface allows read and write access to all the DAC registers and write-only access to theCDCM7005 registers.
The DAC5681/81z/82z EVM requires 1.8-Vdc and 3.3-Vdc supplies for normal operation. An additional5-Vdc supply is required to power up the TRF3703 for RF measurements.
CAUTION
Exceeding the maximum input voltages can damage EVM components.Undervoltage may cause improper operation of some or all of the EVMcomponents.
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2 Software Installation
2.1 Minimum Requirements
2.2 Installing the EVM Control Software
Software Installation
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The DAC5681/81z/82z EVM comes with a software package that allows the user to configure the DACand CDCM7005 registers, save and load register settings to/from text files, and visualize the data paththrough the DAC. Communication with the EVM is achieved through a USB port on the host PC. Once thesoftware is installed, the GUI is accessible from Start > All Programs > Texas Instruments DACs >DAC5682z EVM Control.
Before installing the software, verify that the PC meets the following requirements:
•Microsoft Windows™ 2000 or later operating system•1024 x 768 screen resolution for optimal viewing•USB 1.1 or later compatible input port
Other configurations may work; however, they remain untested.
Double-click the setup.exe file located on the installation CD. The EVM Installation Wizard will open(Figure 1 ).
Figure 1. EVM Installation Wizard
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2.3 Installing the DAC5681/81z/82z EVM Instrument Drivers
2.4 Installing the DAC5681/81z/82z EVM Hardware
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Software Installation
As part of the Install Wizard, the EVM instrument drivers are installed automatically. Because the USBdevice driver is unsigned by Windows, the warning in Figure 2 appears. Press Continue Anyway tocomplete the installation.
Figure 2. Windows USB Driver Warning
To finalize the installation, the Installation Wizard asks the user to restart the computer. The system mustbe rebooted prior to running the software.
After installing the EVM control software and drivers, connect the DAC5681/81z/82z EVM to a spare USBport of the host PC. If this is the first time connecting to the device, the Windows Found New HardwareWizard guides you through the final setup steps. If the Hardware Wizard does not start, ensure that thecable is connected properly.
Instruct the Hardware Wizard to find the software automatically. If Windows is unable to find the driversautomatically, point it to the DAC5682 program folder. The default folder is C:\Program Files\TexasInstruments\DAC5682z\DAC5682z Drivers. A warning indicating that the drivers are unsigned by Windowsappears. Press Continue Anyway to complete the setup.
To verify a complete installation, open Windows Hardware Device Manager and observe that theDAC5682 EVM is listed under the USB controllers list as shown in Figure 2 .
Figure 3. Hardware Device Manager
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3 DAC5681/81z/82z EVM Description
3.1 Texas Instruments Components on the DAC5681/81z/82z EVM
3.1.1 DAC5681/81z/82z
DAC5681/81z/82z EVM Description
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The DAC5681/81z/82z EVM provides a robust and flexible evaluation system for the 16-bit, 1GSPSDAC5681/DAC5681z/DAC5682z DAC family. In addition to the DAC, the EVM includes a CDCM7005 forclock distribution and in the DAC5682z option a TRF3703 analog quadrature modulator path for RFmeasurements. For a complete hardware description, consult the schematics and layout sections at theend of this guide. See the DAC5681, DAC5681z, DAC5682z, CDCM7005, and TRF3703 data sheets formore information on each device.
A basic radio system block diagram is shown in Figure 4 . The dashed-line box illustrates where the EVMfits in the system.
Figure 4. Basic Radio System
The block diagram of the DAC5682z EVM option is shown in Figure 5 . As illustrated on the block diagram,the DAC5682z EVM option includes three Texas Instruments components that make the entire solution anexcellent choice for radio systems.
Figure 5. DAC5682z Option Block Diagram
The DAC5681/81z/82z is a family of high-performance, 16-bit, 1.0-GSPS DACs with wideband LVDS datainput and internal voltage reference. The family integrates a wideband LVDS port with on-chip termination.An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control fot the LVDS inputdata clock.
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3.1.2 CDCM7005
3.1.3 TRF3703
4 DAC5681/81Z/82z EVM Hardware Description
4.1 Jumper Settings
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DAC5681/81Z/82z EVM Hardware Description
The DAC5681and DAC5681z are single-channel devices while the DAC5682z supports two-channels. TheDAC5681z and DAC5682z include 2x/4x interpolation filters and on-board clock multiplier with superiorphase noise performance. Each interpolation FIR is configurable in either Low-Pass or High-Pass mode,allowing selection of a higher order output spectral image.
The DAC5682z is the only member of the family that allows a complex output. An optional Fs/4 coarsemixer in complex mode provides coarse frequency upconversion and the dual DAC output produces acomplex Hilbert Transform pair. An external RF quadrature modulator then performs the final singlesideband up-conversion.
The CDCM7005 is a high-performance, low-phase noise and low-skew clock synchronizer thatsynchronizes a VCXO (voltage-controlled crystal oscillator) or VCO (voltage-controlled oscillator)frequency to a reference clock. The CDCM7005 is used to generate and synchronize the clock outputs tothe system. The device has five outputs which can be configured to LVPECL or LVCMOS levels and canbe divided down by 1, 2, 3, 4, 6, 8, and 16. The divide by 16 can be replaced with a divide by 4 or 8 with a90 °phase shift.
The TRF3703 is a very-low-noise direct quadrature modulator, capable of converting complex modulatedsignals from baseband or IF directly up to RF-based on the LO frequency.
The DAC5681/81z/82z EVM can be set up in a variety of configurations to accommodate a specific modeof operation. Before starting evaluation, the user should decide on the configuration and make theappropriate connections or changes. The demonstration board comes with the following factory-setconfiguration:
•No VCXO installed. CDCM7005 in buffer mode which requires an input single-ended clock signal toSMA connector J6.•On the DAC5682z EVM outputs are set by default to drive the TRF3703. The DAC5681 andDAC5681z output is connected to J3.•The converter is set to operate with internal reference. Jumper JP8 EXTLO is installed between pins 2and 3.•Full-scale output current set to 20mA through RBIAS resistor R18.
The DAC5681/81z/82z EVM has onboard jumpers that allow the user to modify the board configuration.Table 1 explains the functionality of the jumpers.
Table 1. Jumper List
Jumper Label Function Condition Default
JP8 EXTLO Internal (GND) or external (3.3V) voltage reference GND Pin 2-3
JP10 VFUSE Factory use only. Connect to 1.8VDD for normal operation. 1.8 VDD Pin 1-2
JP12 CDC_PD Low active power down of CDCM7005 3.3 VCLK Pin 1-2
JP13 VCXOB Choose internal VCXO or external VCXO INB External VCXO Pin 2-3
JP14 VCXO_P Choose internal VCXO or external VCXO positive input External VCXO Pin 2-3
JP15 VCXO_N Choose CDCM7005 or external VBB CDCM7005 Pin 1-2
JP16 REF_CLK Choose internal 10-MHz ref or external ref Internal Ref Pin 2-3
JP17 +3.3V_IN Main or TP3 3.3 voltage source for CDCM7005 and USB Main Pin 1-2
JP19 +3.3VCLK VCXO power down 3.3 VCLK Pin 1-2
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4.2 Input/Output Connectors
4.3 USB Interface
4.4 Power Management
4.5 Input Connector
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Table 2 lists the input and output connectors on the EVM.
Table 2. Input and Output Connectors
Reference
Label Connector Type DescriptionDesignator
DACB transformer output. Optional IOUTB2 output. Not populatedJ1 IOUTB2 SMA
on DAC5681/81z.
J2 IOUTB1 SMA Optional IOUTB1 output. Not populated on DAC5681/81z.
J3 IOUTA2 SMA DACA transformer output. Optional IOUTA2 output.
J4 IOUTA1 SMA Optional IOUTA1 output.
J5 SEMTEK Input LVDS data to DAC. Output clock to data source.
J6 EXT_VCXO_P SMA External main clock input.
J7 EXT_VCXO_N SMA External VCXO negative connection. Not required.
J8 Y2A_CLK SMA Optional CDCM7005 clock output.
J9 EXT_REF_CLK SMA External reference clock input.
J10 Y2B_CLK SMA Optional CDCM7005 clock output.
J13 USB_CONN USB USB connector for software communication.
J14/J15 +1.8V_IN Banana Plug +1.8V connection pair.
J16 RFOUT SMA RF output from TRF3703.
J17/J18 +3.3V_IN Banana Plug +3.3V connection pair.
J19/J20 +5VA_IN Banana Plug +5V connection pair. Required only for RF measurements.
J23 RF_LO_IN SMA TRF3703 LO source input. Not populated on DAC5681/81z.
The DAC5681/81z/82z EVM has a 4-pin USB port connector that interfaces to a USB 1.1 (or later)compliant USB port. Programming of the CDCM7005 and DAC is accomplished through this port.
The DAC5681/81z/82z EVM requires 1.8-V and 3.3-V supplies for normal operation. An additional 5-Vsupply is required supply power up the TRF3073 for RF measurements.
The DAC5681/81z/82z EVM accepts LVDS inputs through a SEMTEK connector. These inputs driveDCLK, SYNC and D15-D0 LVDS pairs on the DAC device. An LVDS clock signal from the CDCM7005 isalso output through this connector. This output clock is useful for synchronization with the patterngeneration source.
Table 3. Input Connector
Pin Description Pin Description
47 D15P 101 D7P
49 D15N 103 D7N
53 D14P 107 D6P
55 D14N 109 D6N
59 D13P 113 D5P
61 D13N 115 D5N
65 D12P 119 D4P
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4.6 Clock Configuration
4.6.1 Buffer Mode
4.6.2 PLL Mode
4.7 Output Configurations
4.7.1 DAC Outputs
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DAC5681/81Z/82z EVM Hardware Description
Table 3. Input Connector (continued)
Pin Description Pin Description
67 D12N 121 D4N
71 D11P 125 D3P
73 D11N 127 D3N
77 D10P 131 D2P
79 D10N 133 D2N
83 D9P 137 D1P
85 D9N 139 D1N
89 D8P 143 D0P
91 D8N 145 D0N
95 DCLKP 155 SYNCP
97 DCLKN 157 SYNCN
Synchronizing Positive LVDS 161,162,163,164,165,166,167,1696 GNDoutput clock 8,169,170,171,172
Synchronizing Negative LVDS98 All others Unusedoutput clock
The CDCM7005 requires a VCXO or external clock source to derive its output clock signals.
The DAC5681/81z/82z EVM does not come populated with a VCXO and requires an external sine wavesource with a 1-Vrms, 0-V offset on SMA J6. Under this setup, the CDCM7005 operates as a buffer. Toselect this mode, the following changes need to be made:
1. JP13 and JP14 need to be set in position 2-3.2. If a VCXO is installed, it is recommended to disable it by removing jumper JP19.
A VCXO can be installed in U6 to operate the CDCM7005 as a PLL. The following changes need to bemade:
1. JP13 and JP14 need to be in the 1-2 position.2. Install jumper JP19.3. A frequency reference (internal or external) needs to be provided.
The DAC5681 and DAC5681z options are configured such that the single DAC output drives a a doublyterminated 50- Ωcable using a 4:1 impedance ratio transformer with the center tap of the transformerconnected to +3.3 V. The output signal is found at SMA connector J3.
The DAC5682z EVM option has a resistor network that can be configured such that the DAC outputs arerouted to the TRF3703 for an RF measurement or routed to the transformer path for a DAC measurement.The default setup on the board is for RF output.
To configure the DAC5682z EVM to evaluate the DAC outputs, the following changes need to be done tothe board:
1. R137, R153, R155 and R156 need to be uninstalled
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4.7.2 RF Output
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2. R109, R134, R135 and R136 need to be installed
Figure 6. DAC5682Z DAC Output Resistor Configuration
If the board is configured for DAC outputs, the TRF3703 modulator is not used and the 5-Vdc supply isunnecessary. The DAC outputs in this setup are in J1 and J3.
To configure the DAC5682z EVM to evaluate the RF output (default setup), the following changes need tobe done to the board:
1. R137, R153, R155 and R156 need to be installed2. R109, R134, R135 and R136 need to be uninstalled
Figure 7. DAC5682z RF Output Resistor Configuration
If the board is configured for RF output, the 5-Vdc must be applied to power up the modulator. The outputin this setup is in J16.
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4.7.2.1 TRF3703 LO Source
4.7.2.2 DAC-to-Modulator Interface
4.8 Reference Operation
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DAC5681/81Z/82z EVM Hardware Description
The DAC5682z EVM requires an external local oscillator (LO) source to drive the onboard TRF3703modulator. This external LO input needs to be connected to the SMA connector J23. The signal level ofthe LO source must comply with the requirements in the TRF3703 data sheet (SLWS184), but typically anLO power around 6-to-8 dBm is adequate.
The TRF3703 quadrature modulator requires a common-mode dc voltage of approximately 3.3 V. In orderto use the dc-offset adjustment capabilities of the DAC5682z for carrier suppression, it is imperative tomaintain a dc path from the DAC output to the modulator input. The common-mode voltage for themodulator is maintained with a passive resistor network that is designed to provide the proper operationpoint for the DAC5682z and the TRF3703 modulator.
The DAC5682z EVM is configured with enough pads to provide a specific fifth-order differential passiveLC filter. By default, it is only populated with a simple LC low-pass filter to attenuate the higher clockharmonics. The 3-dB corner of this filter is approximately 300 MHz.
Figure 8. Response of Default Baseband Filter
The DAC5682z EVM also includes a pi pad network on the modulator output to provide some matching orfiltering, if desired. In its default state, the pad is not used and a series capacitor is used on the RF output.
The DAC5681/81z/82z full-scale output current is set by applying an external resistor (R18) between theBIASJ pin of the device and ground. The full-scale output current can be adjusted from 20 mA down to 2mA by varying this resistor. The full-scale output current, IOUTFS, is defined as follows:
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5 DAC5681/81z/82z EVM Software
5.1 Software Functionality Overview
DAC5681/81z/82z EVM Software
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where V
EXTIO
is the voltage at pin EXTIO. This voltage is 1.2 V when using the internally providedbandgap reference voltage source. The internal reference can be disabled and overridden by an externalreference by connecting a voltage source to EXTIO and connecting EXTLO to +3.3 VA (JP8 EXTLOconnected between pins 1 and 2). The specified range for external reference voltages must be observed.
The EVM Control Software is started by accessing the Windows start →All Programs →Texas Instruments DACs cascading menus.
The DAC EVM application helps you to:•Configure the DAC and CDCM7005 registers.•Save and load these register settings using text files.•Visualize the data path through the DAC•Download a pattern to a TSW3100 Pattern Generator System (link to TSW3100 EVM folder).
This section provides you an overview of the software settings and functionality for the entire DACGraphical User Interface. The software has five groups of settings that help you modify the functionality ofthe active panels. You can switch between these settings by selecting one of the Menu items described inTable 4 .
Table 4. Software Main Menu Selections
Menu Item Top Panel Bottom Panel Section
Example ScreenFunctionality Reference
EVM Home EVM and DAC serial information. not applicable Section 5.2EVM communication status Figure 9Table 6
DAC5682z DAC Register Configuration DAC data path under the current Section 5.3Diagram register settings Figure 10Table 7
Register Config DAC Register Configuration CDCM7005 Register Section 5.4Configuration Figure 11Table 8
TSW3100 Config DAC Register Configuration TSW3100 Configuration Section 5.5Pattern Generator display Figure 12Table 9
Help DAC Register Configuration DAC data path and help window Section 5.6
The DAC software interface controls are divided into areas. The functionality of these areas is described inSection 5.2 through Section 5.6 .
Table 5. Software Area Descriptions
Area Description
Menu Switch between the main functionality settings described in Table 4 .
DAC5682Z Home Displays DAC part serial information and EVM status.
USB and Readback buttons Reset the USB port to begin a new data session. Disable DAC read capabilities (simulationmode).
DAC5682z Register Table Displays DAC register settings in binary and hexadecimal formats.
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5.2 EVM Home Area
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DAC5681/81z/82z EVM Software
Table 5. Software Area Descriptions (continued)
Area Description
DAC5682z Register Configuration Read/Write DAC register configuration.
CDCM7005 Register Configuration Write CDCM7005 register configuration (no read capability)
DAC5682z Diagram Graphical representation of the DAC data path under current register configuration.
TSW3100 Configuration Controls TSW3100 pattern generation system (See TSW3100 User's Guide SLLU101 formore information)
Help Information about specific DAC register configuration GUI controls
Figure 9 through Figure 12 displays some of the Menu software areas.
The EVM Home Area includes these GUI controls:•Menu—switches between the major functionality listed in Table 4 and displayed in Figure 9 .•Home—displays DAC part information and EVM status.•USB/Readback—reset the USB port to begin a new data session. Disable DAC read capabilities(simulation mode).•DAC5682z Register Table—displays DAC register settings in binary and hexadecimal formats(Figure 10 -Regs).
Note: The numbers on Figure 9 through Figure 12 correspond to the numbered graphical userinterface subareas (X), described in each table for the DAC EVM software functionality.
Figure 9. EVM Home Displaying EVM Status Settings
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Table 6. EVM Home Software Functionality
InputSubarea Name DescriptionOutput
Menu Area (1)
EVM Home Input DAC EVM Home area - part number information and EVM status messages
DAC5682z Diagram Input DAC Register Configuration and DAC5682z Diagram areas
Register Config Input . DAC and CDCM7005 Register Configuration areas
TSW3100 Config Input DAC Register Configuration and TSW3100 Configuration areas
Help Input Help area
DAC5682z EVM Home Area (2)
Functionality Output DAC device
Version Output Chip version
Wafer number Output DAC wafer number
Column (x) Output DAC column position
Row (y) Output DAC row position
Lot Number Output DAC lot number
Fab Output Fabrication facility where the DAC was manufactured
EVM Serial Number Output Serial number for this EVM
Status Messages Output Displays the status of the communication session.
USB / Readback Area (3)
Reset USB Port Input Begins a new USB session. Click this button if you see a status error message.
Readback Input/Output Disables DAC register reads (simulation mode)
DAC5682z Register Table Area (See Figure 10 ,Figure 11 , and Figure 12 )
Displays the DAC register configuration in binary and hexadecimal formats for all menuRegister Table Output
settings.
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5.3 DAC Register Configuration and Block Diagram
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DAC5681/81z/82z EVM Software
Figure 10. DAC Block Diagram and Register Configuration Settings
Table 7. DAC Register Configuration Software Functionality
InputSubarea Name Description of Functionality (GUI Setting)Output
PLL Settings (1)
PLL Input/Output Phased-locked Loop (PLL) is bypassed ( disabled)
PLL Sleep Input/Output PLL is put into sleep mode ( selected)
PLL Lock Output Internal PLL is locked ( Green)
PLL loop filter is pulled down to 0V ( set).PLL Reset Input/Output
Toggle to restart the PLL if an over-speed lock-up occurs.
PLL clock output is one-half the PLL VCO frequency ( 2x).VCO Frequency Input/Output Runs the VCO at twice the needed clock frequency to reduce phase noise for lower input clockrates.
PLL Gain (MHz/V) Input/Output Adjust the PLL Voltage Controlled Oscillator (VCO) gain.
PLL Range (MHz) Input/Output Sets the PLL VCO frequency range.
M value Input/Output M portion of the M/N divider of the PLL.
N portion of the M/N divider of the PLL. This value should be chosen to divide down the input CLK
INN value Input/Output
to maintain a maximum PFD of 160 MHz.
DLL Settings (2)
Delay lock loop (DLL) is bypassed and LVDS data source provides correct setup and hold timingDLL Input/Output
(disabled)
DLL Sleep Input/Output DLL is put into sleep mode ( selected)
DLL is restarted automatically when DLL settings change, so there is no need to press the DLLAuto-DLL Input
restart control ( selected).
DLL Lock Output Internal DLL is locked ( Green)
DLL restart Input/Output Restarts the DLL manually
DLL Delay (deg.) Input/Output Manually adjust the DLL delay ±from the DLL fixed current delay.
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DAC5681/81z/82z EVM Software
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Table 7. DAC Register Configuration Software Functionality (continued)
InputSubarea Name Description of Functionality (GUI Setting)Output
DLL fixed current Adjusts the DLL delay line bias current. Used in conjunction with the DLL inv clock to selectInput/Outputdelay (ps/ µA) appropriate delay range for a given DCLK frequency
Inverts the internal DLL clock to force convergence to a different solution. Used when the DLL delayDLL inv clock Input/Output
adjustment has exceeded the limits of its range.
Input Settings (3)
format Input/Output Select 2’s complement or offset binary format.
reverse bus Input/Output Reverses the LVDS input data bus so that the MSB to LSB order is swapped ( enabled)
swap data Input/Output A/B data paths are swapped prior to routing to the DACA and DACB outputs ( enabled)
same data Input/Output Data routed to DACA is also routed to DACB ( enabled)
Sets the FIFO’s output pointer location, allowing the input pointer to be shifted –4 to +3 positionsFIFO offset Input/Output
upon SYNC. Default offset is 0and is updated upon each sync event.
Digital Settings (4)
digital logic Input/Output Uses the interpolation filters ( enabled)
interpolation Input/Output Selects the interpolation rate.
Determines the mode of FIR0 and CMIX0 blocks. Since CMIX0 is located between FIR0 and FIR1,CM0 mode Input/Output
its output is half-rate. Settings apply to both A and B channels.
CM1 mode Input/Output Determines the mode of FIR1 and final CMIX1 blocks. Settings apply to both A and B channels.
DAC data delay adjustment (0–3 periods of the DAC clock). Used to adjust system level outputdigital delay Input/Output
timing. The same delay is applied to both DACA and DACB data paths.
Changes the number of buffers that the input clock goes through. This allows some adjustment ofclock delay Input/Output
the setup/hold of the handoff between the receivers and the digital section.
DAC Settings (5)
DAC mode Input/Output Selects dual DAC mode or single DAC mode. Used to select input interleaved data ( dual DAC).
DACA Sleep Input/Output DACA is put into sleep mode ( selected)
DACB is put into sleep mode ( selected). DACB is not automatically set into sleep mode whenDACB Sleep Input/Output configured for single DAC mode. Use this control with single DAC mode to get the lowest powerconfiguration for DACA output only.
DACA Gain Input/Output Scales the DACA output current in 16 equal steps.
DACB Gain Input/Output Scales the DACB output current in 16 equal steps.
Offset A and Offset B values are summed into the DACA and DACB data paths ( enabled). ProvidesOffset Input/Output
a system-level offset adjustment capability that is independent of the input data.
Transfers the Offset A and Offset B values to the registers used in the DACA and DACB offsetoffset sync Input/Output
calculations. This control is enabled automatically for any change in the Offset A or Offset B values.
Offset A Input/Output Offset adjustment value for the A data path.
Offset B Input/Output Offset adjustment value for the B data path.
95 kHz low pass filter corner on the DACA current source bias ( enabled). Uses a 472 Hz filterDAC A LPF Input/Output
corner ( disabled).
95 kHz low pass filter corner on the DACB current source bias ( enabled). Uses a 472 Hz filterDAC B LPF Input/Output
corner ( disabled).
Error Settings (6)
SLFST Error Input/Output Masks out SLFTST Errors.
FIFO Error Input/Output Masks out FIFO Errors.
Setup/Hold Error Input/Output Masks out Setup/Hold Errors.
SLFST error reset Input/Output Asserted when the Digital Self Test (SLFTST) fails. Clear to reset a SLFST error.
Asserted when the FIFO pointers overrun each other, causing a sample to be missed. Clear to resetFIFO error reset Input/Output
a FIFO error.
Any received data pattern other than 0xAAAA or 0x5555 causes this bit to be set. Clear to reset aSetup/Hold error reset Input/Output
Setup/Hold error.
SDO Input/Output Selects the signal polarity on the SDO pin ( normal or inverted)
SYNC Settings (7)
serial interface Input/Output Selects 3-pin or 4-pin serial interface mode.
16 DAC5681/81z/82z EVM SLAU236A – November 2007 – Revised October 2008Submit Documentation Feedback
TEXAS INSTRUMENTS c, numb (w {mum mcssszz EVM {w nus Mn mu WWW- W 0 mm mm mm HM. W, mm , W . I w , mm“, M v mu v mmzuw w . ”m" “M ‘ WWW" V a w» “mums; v w“ v when" :k V ”W” M“ ' “w W” V WW W ~' " MW vilvw . yaw mum « 5“” Humw emu a ' “Wm M new . mum... . N“ mum (m. n ”aw“ (”WNW v mum“ . NW Regs Wm mm W V M . V 5; “mm “3" (WWWW- out“, 1 MMWMMW. : misc: 2:: 2 5mm; 17:73 5 mm m ”1;; "3M 5 mm" W min; mm W. WV. 4 San»! n my: wwam n “ . w W.
5.4 CDCM7005 Register Configuration
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DAC5681/81z/82z EVM Software
Table 7. DAC Register Configuration Software Functionality (continued)
InputSubarea Name Description of Functionality (GUI Setting)Output
Selects the synchronization signal source. If soft sync is selected the software sync control is usedsync source Input/Output
as the only synchronization input and the LVDS external SYNC input pins ( hard sync) are ignored.
Substitute for the LVDS external SYNC input pins for both synchronization and transmit enablesoftware sync Input/Output
control.
hold sync Input/Output Enables the sync to the FIFO output HOLD block.
clk div sync Input/Output Enables the clock divider sync.
FIFO sync Input/Output Enables the FIFO offset sync.
self test Input/Output Enables a Digital Self Test (SLFTST) of the core logic.
FA002 Input/Output Keep disabled. Used only for factory test purposes.
Fuse A Input/Output Keep disabled. Used only for factory test purposes.
Fuse B Input/Output Keep disabled. Used only for factory test purposes.
ATEST Input/Output Keep disabled. Used only for factory test purposes.
SEND/SAVE Button Settings (8)
Send All Input Writes all registers to the DAC device.
Reads all registers from the DAC device. It is rarely necessary to use this as the registers are readRead All Input
every time a DAC control changes.
Loads a DAC register configuration from a text file. Files need to consist of a single column with theLoad Regs Input
register values in hexadecimal format.
Save Regs Input Saves a DAC register configuration to a text file.
Figure 11. The CDCM7005 and DAC5682 Register Configuration Settings
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 17Submit Documentation Feedback
TEXAS INSTRUMENTS {SCAS793
DAC5681/81z/82z EVM Software
www.ti.com
Table 8. CDCM7005 Register Configuration Software Functionality
InputSubarea Name DescriptionOutput
General Settings (1)
Output Settings Input Switches the display between the CDCM7005 output settings and advanced settings.
Select Buffer Mode when there is no VCXO installed or the VCXO is enabled. In this case theCDCM7005 Operation Input CDCM7005 operates as a buffer. Select PLL Mode when a VCXO is being used by theCDCM7005.
PLL Settings (2)
(Auto) M and N divider values are calculated automatically based on Reference and VCXOM & N Selection Input
frequencies.
Ref. Freq. (MHz) Input Frequency of the reference oscillator given to the CDCM7005.
VCXO Freq. (MHz) Input Frequency of the VCXO used.
M Divider Input/Output M divider value.
N Divider Input/Output N divider value.
FB_MUX Input/Output Feedback MUX select.
Phase Shift Input Phase shift select.
Output frequency of the CDCM7005 based on the Reference and VCXO frequencies, and M andOutput Freq (MHz) Output
N values. If Output Freq differs from VCXO Freq, Output Freq displays using a red text.
Output Settings (3)
Y0-Y4 Dividers Input Selects the output dividers of the CDCM7005 outputs.
Y0-Y4 Levels Input Selects between CMOS or LVPECL levels of the CDCM7005 outputs.
Y0-Y4 States Input Selects the operating state of the CDCM7005 outputs.
SEND/SAVE Button Settings (4)
Send All Input Writes all registers to the DCDM7005 device.
Loads a DCDM7005 register configuration from a text file. Files need to consist of a singleLoad Regs Input
column with the register values in hexadecimal format.
Save Regs Input Saves a DCDM7005 register configuration to a text file.
Advanced Settings (not shown)
Input CDCM7005 advanced registers. See the CDCM7005 data sheet (SCAS793 ) for moreAdvanced Registers
information about these registers.
18 DAC5681/81z/82z EVM SLAU236A – November 2007 – Revised October 2008Submit Documentation Feedback
TEXAS INSTRUMENTS SLLU101 mu: ‘ m Dncssa EVM mm nxmflwmwm my n mm." mm: .WM mm . We Mm . o m. mam V mm m . Mm m». We, imam - WW: E E ”W 4 umwb v E—uauu m y :mm ‘ v m V Mama mm ~ mm was v a ‘ - MN “MW w ~ 0 m “mum” . Mu.) v ”mum m V mm mm v 111mm .W . “MW“ ,, ‘ m A WWW ,5 or v ”mam "W . ”(a g. 2 . 4..» “ ~ Mm mm mm v mm m v “mm m V “mm“, “m ' WWI; mm m . W —_"' Wum Mrflwm . mm mm v N V :Hum a A smmmm.» V W” ~ mm W V mnz a.“ v M! a c S‘Mgg‘fi: g “Mum, . mum . MW mm (man V wwmmu 0 mm, we, v m. mm v sum Regs m 1, v mm "M v w mm v avisv imam v m: m. m my mm H. mm w 1‘ ym m mm m 2 3 m mum :an ’~*W“'"‘ ”“5 “ mmmm 4 m mm w ”Mm, “Wm . m mmnnm non rum" w mm M mm .um. \zn : ' v musk.“ a (SLLU101 {SLLUIDI
5.5 TSW3100 Configuration and Pattern Generation
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DAC5681/81z/82z EVM Software
The TSW3100 can be loaded with a custom pattern file using the GUI options. For further details on thefile format of the custom pattern, see the TSW3100 Users Guide (SLLU101 ).
Figure 12. TSW3100 Pattern Generator and DAC Register Configuration Settings
Table 9. TSW3100 Configuration and Pattern Generation Functionality
InputSubarea Name DescriptionOutput
Pattern Selection (1)
Selects Binary and 16-bit signed Integer format. If Binary is selected, the file must comply withthe requirements described on the TSW3100 (SLLU101 ) documentation. If integer format isFile Format Input
selected, the file must consist of a single column for a real signal or two columns for atwo-channel or complex signal.
Browse Button Input Navigate to the folder containing the input pattern file name. Select the file to use.
Output Mode (2)
Column Delimiter Input Column separator used in the two-channel or complex integer input file. (Not displayed)
Output Level Input LVDS or CMOS outputs. Only LVDS is available for the DAC5682z.
Data Format Input 2's complement or offset binary format.
IP Address Input Specify final digit (1, 2, 3, or 4) of the IP address for the TSW3100 pattern generator.
Master or Slave mode. The default state is Master mode. See TSW3100 (SLLU101 )TSW3100 State Input
documentation for more information.
Command Buttons (3)
Load and Start Input Load a pattern file and start the TSW3100.
Stop Pattern Input Stop the pattern transfer.
Re-start Pattern Input Re-start the pattern. A pattern must be loaded in memory for this command to work.
Pattern Generation Results (4)
Command Output Shows sequence of commands sent to the TSW3100.
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 19Submit Documentation Feedback
TEXAS INSTRUMENTS
5.6 Help
DAC5681/81z/82z EVM Software
www.ti.com
Table 9. TSW3100 Configuration and Pattern Generation Functionality (continued)
InputSubarea Name DescriptionOutput
Status Output Status of the TSW3100 transaction.
Bytes loaded Output Number of bytes loaded to the TSW3100.
When you select the the Help menu item, the DAC Diagram screen (Figure 10 ) and a detached, pop-upHelp text window display. As you move the cursor over the DAC Diagram GUI controls, thecontext-sensitive help text changes in the pop-up window.
DAC5681/81z/82z EVM20 SLAU236A – November 2007 – Revised October 2008Submit Documentation Feedback
INSTRUMENTS § .muu YSWJHD Pan-m Us mu: Gun-mu
6 DAC5681/81z/82z Initial Power Up and Test
6.1 Test Setup Block Diagram
6.2 Test Equipment
6.3 Calibration
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DAC5681/81z/82z Initial Power Up and Test
The recommended test setup for the EVM is shown in Figure 13 . In this setup the Texas InstrumentsTSW3100 pattern generator solution is used to supply the LVDS input data.
Figure 13. DAC5682z EVM Driven by TSW3100 Pattern Generator
The test equipment listed below is required to evaluate the EVM. Other equipment may be substituted,however results may vary due to instrument limitations.•Power supplies—1.8 V (DAC digital), 3.3 V (DAC analog), and 5 V (RF modulator)•Spectrum Analyzer—Rhode & Schwarz FSU, FSQ, or equivalent. This is necessary to measure thenoise floor ACPR greater than 70 dBm with the noise correction option.•Pattern generator—TSW3100 using LVDS mode, or some other LVDS capable generator.•Oscilloscope—probe clock and data lines for troubleshooting.•Digital volt meter—verify signal levels.
To measure the proper output power, the insertion loss of the analyzer cable must be calibrated. Measurea calibrated 0 dBm source to see how much loss is in the cable at the frequency of interest.
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 21Submit Documentation Feedback
I TEXAS INSTRUMENTS
6.4 Typical Performance Measurements
Ref -12 dBm Att 10 dB
*
*
*
A
NOR
RBW 30 kHz
VBW 300 kHz
SWT 2 s
*
Center 30.72 MHz Span 25.5 MHz2.55 MHz/
*1 RM
CLRWR
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
Tx Channel W-CDMA 3GPP FWD
Bandwidth 3.84 MHz Power -8.02 dBm
Adjacent Channel
Bandwidth 3.84 MHz Lower -81.73 dB
Spacing 5 MHz Upper -81.65 dB
Alternate Channel
Bandwidth 3.84 MHz Lower -82.95 dB
Spacing 10 MHz Upper -82.74 dB
DAC5681/81z/82z Initial Power Up and Test
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The DAC5681, DAC5681z and DAC5682z measurements at the transformer outputs J1 and J3 will havebetter performance than the RF output at low output frequencies. The RF output is typically limited by theperformance of the RF parts. In this case the DAC output at 0 IF or low IF is several dB better than thenoise floor of the modulator output at J16.
Figure 14. DAC5681/81z/82z EVM Transformer Output With a Low IF at 30.72 MHz
22 DAC5681/81z/82z EVM SLAU236A – November 2007 – Revised October 2008Submit Documentation Feedback
I TEXAS INSTRUMENTS ®
A
Ref -13.2 dBm Att 5 dB
*
*
*
*1 RM
CLRWR
RBW 30 kHz
VBW 300 kHz
SWT 2 s
NOR
*
Center 2.53072 GHz Span 25.5 MHz2.55 MHz/
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
Tx Channel W-CDMA 3GPP FWD
Bandwidth 3.84 MHz Power -8.95 dBm
Adjacent Channel
Bandwidth 3.84 MHz Lower -75.79 dB
Spacing 5 MHz Upper -75.42 dB
Alternate Channel
Bandwidth 3.84 MHz Lower -78.44 dB
Spacing 10 MHz Upper -77.21 dB
6.5 DAC5681/81z/82z Test Procedure
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DAC5681/81z/82z Initial Power Up and Test
Figure 15. DAC5682z EVM output at RF LO + low IF of 30.72M (6 dB lower than DAC output)
The steps described in this section show how to connect and configure the DAC5681/81z/82z EVM forevaluation under the default settings.
1. Connect the DAC5681/81z/82z EVM SEMTEK connector to a digital test pattern generator thatsupports this interface such as Texas Instruments TSW3100.2. Connect the 1.8-V (J14/J15) and 3.3-V (J17/J18) power supplies. If using the modulator the 5-V(J19/J20) supply also needs to be connected. Ensure that each supply is not drawing more than 1-A ofcurrent.
3. Provide a single-ended, 1-Vrms, 0-V, offset sine-wave signal to the EVM EXT_VCXO_P (J6) SMAconnector. LED D1 should illuminate indicating that a signal has been detected. If not, verify that thecorrect signal is being provided.4. If testing at RF (DAC5682z EVM option) provide a 6-dBm LO signal to the RF_LO_IN (J23) SMAconnector.
5. Connect one end of the supplied USB cable to an available USB port on the host PC. Connect theother end of the cable to J13 on the EVM.6. Open the DAC5682z EVM software. The DAC software detects if the USB port is active and if it iscapable of reading the EVM serial number. The EVM Home menu (Figure 9 and Table 6 ) of theDAC8652z GUI software provides this status information.7. Program the CDCM7005 and DAC registers as necessary. An example configuration file is includedunder the installation folder: C:\Program Files\Texas Instruments\DAC5682z\DAC5682z ConfigurationFiles\
8. Program and run the pattern generator. If using the TSW3100, see the user's guide for moreinformation on how to set up a digital pattern.9. Analyze the DAC or RF output using an spectrum analyzer.
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 23Submit Documentation Feedback
INSTRUMENTS ’3 :NST?4N[N ’[XAS )AL758EL LVW + V ) SILKSCREEN TOP
7 PC Board Layouts, Bill of Materials and Schematics
7.1 Board Layouts
PC Board Layouts, Bill of Materials and Schematics
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This section contains the PC-board layouts, bill of materials and schematics for the DAC5681/81z/82zEVM.
Figure 16. Silkscreen (top)
24 DAC5681/81z/82z EVM SLAU236A – November 2007 – Revised October 2008Submit Documentation Feedback
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PC Board Layouts, Bill of Materials and Schematics
Figure 17. Layer 2
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 25Submit Documentation Feedback
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PC Board Layouts, Bill of Materials and Schematics
www.ti.com
Figure 18. Layer 3
26 DAC5681/81z/82z EVM SLAU236A – November 2007 – Revised October 2008Submit Documentation Feedback
YAS HS WV H? L ,X N LII
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PC Board Layouts, Bill of Materials and Schematics
Figure 19. Layer 4
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 27Submit Documentation Feedback
‘ ego, econ
PC Board Layouts, Bill of Materials and Schematics
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Figure 20. Layer 5
28 DAC5681/81z/82z EVM SLAU236A – November 2007 – Revised October 2008Submit Documentation Feedback
YAS HS rLV \
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PC Board Layouts, Bill of Materials and Schematics
Figure 21. Layer 6
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 29Submit Documentation Feedback
YAS HS WV 22 :XN
PC Board Layouts, Bill of Materials and Schematics
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Figure 22. Layer 7
30 DAC5681/81z/82z EVM SLAU236A – November 2007 – Revised October 2008Submit Documentation Feedback
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www.ti.com
PC Board Layouts, Bill of Materials and Schematics
Figure 23. Layer 8
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 31Submit Documentation Feedback
'XA‘, N‘,WL,\"\ 5 mm W
PC Board Layouts, Bill of Materials and Schematics
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Figure 24. Layer 9
32 DAC5681/81z/82z EVM SLAU236A – November 2007 – Revised October 2008Submit Documentation Feedback
SILKSCREEN BOTTOM
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PC Board Layouts, Bill of Materials and Schematics
Figure 25. Screen (Bottom)
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 33Submit Documentation Feedback
TEXAS INSTRUMENTS
7.2 Bill of Materials
PC Board Layouts, Bill of Materials and Schematics
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QTY. Part Reference Value PCB Footprint MFR. Name MFR. Part Number Note
12 C1 C2 C5 C8 C56 C70 0.01 µF 0603 Panasonic ECJ-1VB1C103KC76 C79 C84 C87C121 C124
1 C3 0.15 µF 0402 Murata GRM36X5R154K10H520
6 C4 C29 C48 C104 1000 pF 0402 Panasonic ECJ-0EB1E102KC106 C127
38 C6 C7 C9-C15 C17 0.1 µF 0402 Panasonic ECJ-0EB1C104KC18 C20 C23-C25 C27C33 C38-C47 C50-C52C57 C61 C94 C95C107 C114 C130 C131
16 C16 C21 C32 C36 C53 10 µF tant_a Kermet T494A106M016ASC54 C71 C74 C80 C82C88 C93 C97 C98C120 C126
0 C19 C26 C28 C30 0.01 µF 0603 Panasonic ECJ-1VB1C103K_DNI DNI
1 C22 560 pF 0402 Panasonic ECJ-0EB1H561K
2 C31 C113 100 pF 0402 Panasonic ECJ-0EB1E101K
8 C34 C69 C75 C78 C83 1 µF 0603 Panasonic ECJ-1V41E105MC86 C122 C125
1 C35 0.47 µF 0603 Murata GRM188R71C474KA88D
3 C49 C128 C129 0.01 µF 0402 Panasonic ECJ-0EB1E103K
3 C58 C108 C115 4.7 µF tant_a AVX TAJA475K020R
2 C59 C60 47 pF 0603 Panasonic ECJ-1VC1H470J
7 C72 C77 C81 C85 C89 47 µF tant_b Kemet T494B476M010ASC119 C123
0 C73 C100 C101 C116 4.7 pF 0603 Panasonic ECJ-1VC1H047C_DNI DNI
2 C99 C109 3.3 pF 0402 Murata GRM1555C1H3R3CZ01D
2 C102 C103 22 pF 0402 Panasonic ECJ-0EC1H220J
0 C105 C112 2.2 pF 0603 AVX 06035A2R2CAT2A_DNI DNI
2 C110 C111 2.7 pF 0603 AVX 06035A2R7CAT2A
0 C117 C118 0.01 µF 0402 Panasonic ECJ-0EB1E103K_DNI DNI
3 D1-D3 LED green LED_0805 Panasonic LNJ306G5UUX
3 D12-D14 MBRB2515L DIODE_MBRB2515L ON Semiconductor MBRB2515LT4G
13 FB1-FB13 68 Ωat 100 MHz 1206 Panasonic EXC-ML32A680U
4 J1-J4 SMA_PCB_THVT SMA_THVT_312x312 Johnson Components 142-0701-201
7 J6-J10 J16 J23 SMA_END_JACK_RND SMA_SMEL_218x247_096 Johnson Components 142-0761-801
1 J13 USB_B_S_F_B_TH CON_THRT_USB_B_F SAMTEC USB-B-S-F-B-TH
3 J14 J17 J20 BANANA_JACK_RED CON_THVT_BANANA_JACK_250DIA SPC Technology 845-R
3 J15 J18 J19 BANANA_JACK_BLK CON_THVT_BANANA_JACK_250DIA SPC Technology 845-B
1 J5 ASP-122952-01 CON_SMVT_160POS_ASP_122952 SAMTEC ASP-122952-01
4 JP8 JP13 JP14 JP16 Jumper_1x3_100_430L HDR_THVT_1x3_100_M SAMTEC HMTSW-103-07-G-S-.230 (SHUNT 2-3)
4 JP10 JP12 JP15 JP17 Jumper_1x3_100_430L HDR_THVT_1x3_100_M SAMTEC HMTSW-103-07-G-S-.230 (SHUNT 1-2)
1 JP19 Jumper_1x2_100_430L HDR_THVT_1x2_100_M SAMTEC HMTSW-102-07-G-S-.230
0 L6 L7 56 nH IND_0603 Panasonic ELJ-RE56NJF3_DNI DNI
4 L8 L9 L14 L15 10 nH IND_0603 Coilcraft 0603CS-10NXLU
4 L10-L13 68 nH 0603 Coilcraft 0603CS-68NXJL
0 R1 R2 R4 R5 R12 R14 1K 0402 Panasonic ERJ-2RKF1001X_DNI DNIR17 R19
10 R3 R7 R13 R21 R26 100 0402 Panasonic ERJ-2RKF1000XR80 R82 R90 R93 R96
0 R6 R9 R15 R20 R23 0 0603 Panasonic ERJ-3GEY0R00V_DNI DNIR27 R109 R134-R136
5 R8 R22 R44 R49 R62 0 0402 Panasonic ERJ-2GE0R00X
1 R10 93.1 0402 Panasonic ERJ-2RKF93R1X
0 R11 R24 R132 R133 60.4 0603 Yageo RC0603FR-0760R4L_DNI DNI
0 R16 100 0603 Panasonic ERJ-3EKF1000V_DNI DNI
1 R18 953 0402 Panasonic ERJ-2RKF9530X
1 R25 1K 0402 Panasonic ERJ-2RKF1001X
3 R28-R30 750 0402 Panasonic ERJ-2RKF7500X
8 R31-R34 R42 R43 R66 130 0402 Panasonic ERJ-2RKF1300XR67
34 DAC5681/81z/82z EVM SLAU236A – November 2007 – Revised October 2008Submit Documentation Feedback
TEXAS INSTRUMENTS
www.ti.com
PC Board Layouts, Bill of Materials and Schematics
QTY. Part Reference Value PCB Footprint MFR. Name MFR. Part Number Note
8 R36-R39 R46 R47 R69 82.5 0402 Panasonic ERJ-2RKF82R5XR70
2 R40 R116 150 0402 Panasonic ERJ-2RKF1500X
2 R41 R150 90.9 0603 Panasonic ERJ-3EKF90R9V
0 R45 R51 R122 R123 0 0402 Panasonic ERJ-2GE0R00X_DNI DNI
0 R48 R54 130 0402 Panasonic ERJ-2RKF1300X_DNI DNI
9 R50 R56 R78 R79 R81 22.1 0402 Panasonic ERJ-2RKF22R1XR84 R89 R95 R97
0 R52 R57 R110 R111 150 0402 Panasonic ERJ-2RKF1500X_DNI DNI
0 R53 R58 82.5 0402 Panasonic ERJ-2RKF82R5X_DNI DNI
0 R55 49.9 0402 Panasonic ERJ-2RKF49R9X_DNI DNI
7 R59-R61 R64 R108 10K 0402 Panasonic ERJ-2RKF1002XR113 R114
1 R63 162 0402 Panasonic ERJ-2RKF1620X
1 R65 4.75K 0402 Panasonic ERJ-2RKF4751X
1 R92 100 0603 Panasonic ERJ-3EKF1000V
18 R137 R140-R142 R145 0 0603 Panasonic ERJ-3GEY0R00VR153 R155 R156R159-R168
4 R138 R151 R152 R154 60.4 0603 Yageo RC0603FR-0760R4L
1 R139 49.9 0402 Panasonic ERJ-2RKF49R9X
4 R143 R144 R147 R148 634 0603 Yageo RC0603FR-07634RL
4 R146 R149 R157 R158 115 0603 Yageo RC0603FR-07115RL
1 SW1 SW RESET SW_SMVT_RESET C & K KT11P3JM
2 T1 T2 ADT4-1T TFMR_6_250x340_100 Mini-Circuits ADT4-1T
8 TP1-TP8 Testloop_Black TP_THVT_060_RND Components Corporation TP-105-01-00
1 U1 DAC5681/81Z/82Z QFN_64_360x360_0p50mm_pwrpad Texas Instruments DAC5681,81Z,82Z TI
1 U2 CDCM7005 QFN_48_281x281_0p50mm_pwrpad Texas Instruments CDCM7005RGZT TI
1 U3 OSC-VECTRON OSC_4_SM_460x386 Vectron VTD3-J0BC-10M000 TI
1 U5 FT245RL SSOP_28_413x220_26 FTDI Chip FT245RL
0 U6 2115-491.52MHZ VCXO_6 Toyocom TCO-2111-491.52_DNI DNI
1 U8 TRF3703-33 QFN_24_163x163_0p50mm_pwrpad Texas Instruments TRF3703-33IRGET TI
1 U10 SN74AHC541PW TSSOP_20_260x177_26 Texas Instruments SN74AHC541PW TI
1 U11 SN74HC241PW TSSOP_20_260x177_26 Texas Instruments SN74HC241PW TI
4 Z_SCREW1- SCREW PANHEAD Building Fasteners PMS 440 0038 PH SCREW FORZ_SCREW4 4-40 x 3/8 STANDOFF
8 Z_SH-H1-Z_SH-H6 SHUNT-HEADER Keltron MJ-5.97-G SHUNT FORZ_SH-H9 Z_SH-H10 HEADER
4 Z_STANDOFF1- STANDOFF ALUM Keystone 2203 STANDOFFZ_STANDOFF4 HEX 4-40 x 0.500
Notes:
1. DNI = DO NOT INSTALL
2. SHUNT 2-3
3. SHUNT 1-2
4. SCREW FOR STANDOFF
5. SHUNT FOR HEADER
6. STANDOFF
SLAU236A – November 2007 – Revised October 2008 DAC5681/81z/82z EVM 35Submit Documentation Feedback
TEXAS INSTRUMENTS
7.3 Schematics
PC Board Layouts, Bill of Materials and Schematics
www.ti.com
The DAC5681/81z/82z schematics are appended to the end of this document.
36 DAC5681/81z/82z EVM SLAU236A – November 2007 – Revised October 2008Submit Documentation Feedback
n EVCLK Hi— NOTES: 1) DNI = DO NOT INSTALL 2) FOR DACSSSl/EIZ OPTION: SHEET 1 R109,R134,R135,R136 ARE INSTALLED R7 AND R13 = 0 OMS RE,C7,T1,J1,J2 = DNI SHEET 5 5H2 SYNC ALL COMPONENTS ARE DNI 5H2 SYNCN 5H2 D‘SP 5H2 DISN 5H2 DMF 5H2 DNN 5H2 m3»: 5H2 DlaN 5H2 m2»: 5H2 mm 0128 8H2 EXTiDCLKP> H .OIuF navu 5H2 DHP 41L Rfi 5H2 DIIN 41L (35 BM 5H2 DmP 41L > H “‘22 5H2 DION 42% 5H3 \N‘LDCLKF 5H2 DSP U‘I‘F Rm 0 5H2 '79” i ' u m DNI 5H2 DEF 42L DNI 5H2 DaN 42L navu R92 R16 s 100 100 3;: j J. ‘0? m 3:: 4L 5H3 INT DCLKN ) 5H2 D5P 1‘ 7 H —3L .UIuF m9 D?“ 5H2 DSN 1K DNI 0129 8H2 EXTiDCLKN> H .OIuF 5H2 DAP 5H2 DAN 5H2 D3P 5H2 DCIN 5H2 D2P 5H2 D2N 5H2 Du: 5H2 DIN 5H2 DDP 5H2 DUN ¢33VA +1 BVD D1 1 F' DI IN DI DP DI UN DSF' DSN DEF DEN DCLKF‘ DCLKN D7F' D7N DEF' DEN DSF' D5N R1 1K DNI (:1 H {CLKINC 5H3 n2 .0un 1K R3 navcm DNI 100 N ism 1K *3 aw _ DNI (:2 H (CLKIN 5H3 R . 1 F aavA I: 0 U ‘ “3 DNI 0 R3 DNI R9 0 0 mo 03 DNI 6 T‘ V n EVCLK 93“ 0.15uF I 0‘ ri>>womsz SHE \ 2 E w v” V (:95 * cs7 W o a F IUuF 100on 7>>mm fig 4 10v éfiéééfigfl‘égggég L W W" :‘7 H __l noooooognnaa EOE V em 07 PWRPAD a H avm Hm DNI -‘“F “‘5 LFF 2‘ DVDD o AVDD 5 UN. R13 V IOUTBI 5‘ ‘00 IOUTBZ 5“ AVDD 9 ‘ JFK EXTLD U1 ms 53 EXTLO +3.3VA *3 aw DAcsemImZ/azz “SJ 5 M JJ EXT‘D \ cs mm: IE AVDD II c *3 (WA AVDD “ V? \g 35:2? l ‘ (SHUNTZ-a; 7 ‘ AVDD n21 DVDD “ HESETB 13 L “‘35 100 KICIVA H20 1‘ EVD‘ +3 EVA 0 DNI R133 ”22 so» u .H>\OUTA2 SHE ‘ . U o o 3 é 1 55m _ l o o l .—>>\OUTA‘ SHE DNI / cm a «count: :35 R24 Ann-1 <7 cm="" r136="" dni="" 9‘0="" +3="" eva="" "“f="" r27="" 0="" r23="" duni="" dni="" sdenb="" 5h4="" '00="" c="" sclk="" 5h4="" _="" smo="" 5h4="" a="" vd="" .="" sdo="" 5h4="" ‘33="" a="" jpid="" 1lbvd="" vfuse="" ggvm="" ap="" 1p8="" 44%;}="" 1i}="" texas="" instruments="" da="" c55822="" e="" vm="" size="" document="" number="" b="" dac="" ale:="" or="" wlednesday.="" august="" 08.="" 2008="" sheet="" 1="" ‘="">
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3.3VA +1.8VD
+1.8VD1
+3.3VA
+3.3VA
+1.8VD1
+1.8VD
+3.3VA
+3.3VA
+3.3VA
+3.3VA
+3.3VA
+3.3VA
+3.3VA
+1.8VCLK
+1.8VD
+1.8VD
+1.8VCLK
+1.8VCLK
+1.8VD
+1.8VD
+3.3VA
+1.8VD1
RESET SH3,4
SDENB SH4
SCLK SH4
SDIO SH4
SDO SH4
D2PSH2 D2NSH2
D3PSH2 D3NSH2
D4PSH2 D4NSH2
D5PSH2 D5NSH2
D6PSH2 D6NSH2
D7PSH2 D7NSH2
D0PSH2
D1PSH2
D0NSH2
D1NSH2
D10PSH2 D10NSH2
D11PSH2 D11NSH2
D12PSH2 D12NSH2
D13PSH2 D13NSH2
D14PSH2 D14NSH2
D15PSH2 D15NSH2
D8PSH2
D9PSH2
D8NSH2
D9NSH2
CLKINC SH3
CLKIN SH3
SYNCPSH2 SYNCNSH2
EXT_DCLKPSH2
INT_DCLKPSH3
EXT_DCLKNSH2
INT_DCLKNSH3
IOUTA2 SH6
IOUTA1 SH6
IOUTB1 SH6
IOUTB2 SH6
Title
Size Document Number Rev
Date: Sheet of
DAC
D
DAC5682Z EVM
B
16Wednesday, August 06, 2008
Title
Size Document Number Rev
Date: Sheet of
DAC
D
DAC5682Z EVM
B
16Wednesday, August 06, 2008
Title
Size Document Number Rev
Date: Sheet of
DAC
D
DAC5682Z EVM
B
16Wednesday, August 06, 2008
NOTES:
1) DNI = DO NOT INSTALL
2) FOR DAC5681/81Z OPTION:
R109,R134,R135,R136 ARE INSTALLED
R7 AND R13 = 0 OHMS
R8,C7,T1,J1,J2 = DNI
ALL COMPONENTS ARE DNI
SHEET 1
SHEET 6
M
S
A
J3
IOUTA2
M
S
A
J3
IOUTA2
1
2345
R9
0
DNI
R9
0
DNI
JP8
EXTLO
(SHUNT 2-3)
JP8
EXTLO
(SHUNT 2-3)
1
3
2
R109
0
DNI
R109
0
DNI
R122
0
DNI
R122
0
DNI
R134
0
DNI
R134
0
DNI
C128
.01uF
C128
.01uF
U1
DAC5681/81Z/82Z
U1
DAC5681/81Z/82Z
D11P
17
D11N
18
D10P
19
D10N
20
D9P
21
D9N
22
D8P
23
D8N
24
DCLKP
25
DCLKN
26
D7P
27
D7N
28
D6P
29
D6N
30
D5P
31
D5N
32
D4P
33
D4N
34
D3P
35
D3N
36
D2P
37
D2N
38
DVDD
39
D1P
40
D1N
41
D0P
42
D0N
43
VFUSE
44
SDO
45
SDIO
46
SCLK
47
SDENB
48
RESETB 49
DVDD 50
AVDD 51
IOUTA1 52
IOUTA2 53
AVDD 54
AVDD 55
EXTIO 56
BIASJ 57
EXTLO 58
AVDD 59
IOUTB2 60
IOUTB1 61
AVDD 62
DVDD 63
LPF 64
CLKVDD 1
CLKIN 2
CLKINC 3
GND 4
SYNCP 5
SYNCN 6
D15P 7
D15N 8
IOVDD 9
DVDD 10
D14P 11
D14N 12
D13P 13
D13N 14
D12P 15
D12N 16
PWRPAD 65
C129
.01uF
C129
.01uF
R6
0
DNI
R6
0
DNI
C14
.1uF
C14
.1uF
R3
100
R3
100
C8
.01uF
C8
.01uF
R92
100
R92
100
R123
0
DNI
R123
0
DNI
M
S
A
J2
IOUTB1
M
S
A
J2
IOUTB1
1
2345
R1
1K
DNI
R1
1K
DNI
C20
.1uF
C20
.1uF
T1
ADT4-1T
T1
ADT4-1T
3
2
16
5
4
C10
.1uF
C10
.1uF
C127
1000pF
C127
1000pF R24
60.4
DNI
R24
60.4
DNI
C12
.1uF
C12
.1uF
R22
0
R22
0
R21
100
R21
100
R19
1K
DNI
R19
1K
DNI
TP8
SDO
TP8
SDO
R132
60.4
DNI
R132
60.4
DNI
C3
0.15uF
C3
0.15uF
R136
0
DNI
R136
0
DNI
C94
.1uF
C94
.1uF
+
C16
10uF
10V
+
C16
10uF
10V
M
S
A
J4
IOUTA1
M
S
A
J4
IOUTA1
1
2345
C18
.1uF
C18
.1uF
C9 .1uFC9 .1uF
C7
.1uF
C7
.1uF
R133
60.4
DNI
R133
60.4
DNI
R135
0
DNI
R135
0
DNI
R27
0
DNI
R27
0
DNI
R4
1K
DNI
R4
1K
DNI
R10
93.1
R10
93.1
R13
100
R13
100
+
C98
10uF
10V
+
C98
10uF
10V
R12
1K
DNI
R12
1K
DNI
R25
1K
R25
1K
+
C93
10uF
10V
+
C93
10uF
10V
+
C97
10uF
10V
+
C97
10uF
10V
R14
1K
DNI
R14
1K
DNI
R23
0
DNI
R23
0
DNI
C13
.1uF
C13
.1uF
C95
.1uF
C95
.1uF
C1
.01uF
C1
.01uF
L7
56nH
DNI
L7
56nH
DNI
12
C4
1000pF
C4
1000pF
T2
ADT4-1T
T2
ADT4-1T
3
2
16
5
4
C11
.1uF
C11
.1uF
R8
0
R8
0
R11
60.4
DNI
R11
60.4
DNI
C2
.01uF
C2
.01uF
R26
100
R26
100
R20
0
DNI
R20
0
DNI
R7
100
R7
100
SW1
SW RESET
RESET
SW1
SW RESET
RESET
1
2
3
4
L6
56nH
DNI
L6
56nH
DNI
12
R5
1K
DNI
R5
1K
DNI
R15
0
DNI
R15
0
DNI
R2
1K
DNI
R2
1K
DNI
R18 953R18 953
C6
.1uF
C6
.1uF
C17
.1uF
C17
.1uF
C5
.01uF
C5
.01uF
C15
.1uF
C15
.1uF
M
S
A
J1
IOUTB2
M
S
A
J1
IOUTB2
1
2345
R16
100
DNI
R16
100
DNI
R17
1K
DNI
R17
1K
DNI
JP10
VFUSE
(SHUNT 1-2)
JP10
VFUSE
(SHUNT 1-2)
1
3
2
Sm Sm Sm Sm Sm Sm Sm Sm Sm Sm Sm Sm Sm Sm Sm Sm Sm EXTiDCLKF' 5m EX‘LDCLKN D‘SP DISN DNP DMN D‘SP 012w D‘ZP DIZN m w DIIN DmP DION DSP DSN DEP BEN 33: PGAJDLKOUTF' 5H3 PGAfiLKouTN 8H3 5m 5m 5m 5m 5m 5m 5m 5m 5m 5m 5m 5m 5m 5m 5m 5m 5m 5m D7? D7N DEF DGN DSP BEN 04? DdN DEF DSN DZP D2N m P DIN DDP DON SYNCF SYNCN 1"} TEXAS INSTRUMENTS NIB DA C55822 EVM Size Documem Number ev B INTERFACE CONWOL D ale: Manda ,Augusl 04. 2008 Sheet 2 o!
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
D15PSH1
D14PSH1
D15NSH1
D14NSH1
D13PSH1 D13NSH1
D12PSH1 D12NSH1
D11PSH1 D11NSH1
D10PSH1 D10NSH1
D9PSH1 D9NSH1
D8PSH1 D8NSH1
D5PSH1 D5NSH1
D4PSH1 D4NSH1
D3PSH1 D3NSH1
D2PSH1 D2NSH1
D1PSH1 D1NSH1
D0PSH1 D0NSH1
D7PSH1
D6PSH1
D7NSH1
D6NSH1
EXT_DCLKPSH1 EXT_DCLKNSH1 SYNCPSH1 SYNCNSH1
FPGA_CLKOUTP SH3
FPGA_CLKOUTN SH3
Title
Size Document Number Rev
Date: Sheet of
INTERFACE CONTROL
D
DAC5682Z EVM
B
26Monday, August 04, 2008
Title
Size Document Number Rev
Date: Sheet of
INTERFACE CONTROL
D
DAC5682Z EVM
B
26Monday, August 04, 2008
Title
Size Document Number Rev
Date: Sheet of
INTERFACE CONTROL
D
DAC5682Z EVM
B
26Monday, August 04, 2008
J5C
ASP-122952-01
J5C
ASP-122952-01
GND 170
GND
169
GND 172
GND
171
102 102
104 104
106 106
108 108
110 110
112 112
114 114
116 116
118 118
120 120
122 122
124 124
126 126
128 128
130 130
132 132
134 134
136 136
138 138
140 140
142 142
144 144
146 146
148 148
150 150
152 152
154 154
156 156
158 158
160 160
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
145
147
147
149
149
151
151
153
153
155
155
157
157
159
159
J5B
ASP-122952-01
J5B
ASP-122952-01
GND 166
GND
165
GND 168
GND
167
42 42
44 44
46 46
48 48
50 50
52 52
54 54
56 56
58 58
60 60
62 62
64 64
66 66
68 68
70 70
72 72
74 74
76 76
78 78
80 80
82 82
84 84
86 86
88 88
90 90
92 92
94 94
96 96
98 98
100 100
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
J5A
ASP-122952-01
J5A
ASP-122952-01
GND 162
GND
161
GND 164
GND
163
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
NOTES: 1) DNI = DO NOT INSTALL V +3 SVCLK éfiiTfiLiLE 3H4 V CTHL ill AV vcxo 1/ m LEDgIeen +3, REF 1/ ‘33va D LED glean ' R3 750 LOCK 1/ JP19 — V V —DTN—EEb—green Sam/cm H31 H32 130 130 Pm 1—. ‘—4 023 navcm 680HM@100MH2 (£1F “1F 10v — “0% R34 13v navcm 130 JP13 vcxoa H36 H37 v CTHL ‘ i 32.5 82.5 g CLKINC SHI U6 0 R116 *3 CELCLK CLKIN SHI v CTRL vcc _ ‘50 NE cum 4 SHUNT23 U2 gun/cm GND OUT 2115-49L52MH JPN R40 R42 DNI vcxoip 150 130 02A ‘ 3 RM g H g; INTiDCLKN SHI ° FMS JuF (SHUNTZ-a) - INTiDCLKF' Sm gm AVCC %
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
V_CTRL
V_CTRL
+3.3VCLK
+3.3VCLK AVCC
+3.3VCLK
+3.3VCLK +3.3VCLK
+3.3VCLK
AVCC
+3.3VCLK +3.3VCLK
+3.3VCLK
+3.3VCLK
+3.3VCLK
+3.3VCLK
+3.3VCLK
+3.3VCLK
CTRL_DATA SH4
CTRL_LE SH4
CTRL_CLK SH4
RESET SH1,4
FPGA_CLKOUTN SH2
FPGA_CLKOUTP SH2
CLKINC SH1
CLKIN SH1
INT_DCLKN SH1
INT_DCLKP SH1
Title
Size Document Number Rev
Date: Sheet of
CDC
D
DAC5682Z EVM
B
36Wednesday, August 06, 2008
Title
Size Document Number Rev
Date: Sheet of
CDC
D
DAC5682Z EVM
B
36Wednesday, August 06, 2008
Title
Size Document Number Rev
Date: Sheet of
CDC
D
DAC5682Z EVM
B
36Wednesday, August 06, 2008
1) DNI = DO NOT INSTALL
NOTES:
R55
49.9
DNI
R55
49.9
DNI
D2 LED green
REF
D2 LED green
REF
SMA
END
J10
Y2B_CLKC
SMA
END
J10
Y2B_CLKC
1
5234
SMA
END
J7
EXT_VCXO_N
SMA
END
J7
EXT_VCXO_N
1
5234
R164
0
R164
0
C34
1uF
20%
25V
C34
1uF
20%
25V
R51
0
DNI
R51
0
DNI
R44
0
R44
0
R48
130
DNI
R48
130
DNI
R65
4.75K
R65
4.75K
C45
.1uF
C45
.1uF
JP15
VCXO_N
(SHUNT 1-2)
JP15
VCXO_N
(SHUNT 1-2)
1
32
R42
130
R42
130
C42
.1uF
C42
.1uF
R67
130
R67
130
JP13
VCXOB
(SHUNT 2-3)
JP13
VCXOB
(SHUNT 2-3)
1
32
+
C36
22uF
20%
10V
+
C36
22uF
20%
10V
12
R53
82.5
DNI
R53
82.5
DNI
C44
.1uF
C44
.1uF
C23
.1uF
10%
16V
C23
.1uF
10%
16V
R37
82.5
R37
82.5
R47
82.5
R47
82.5
JP19
+3.3VCLK
JP19
+3.3VCLK
1 2
C29
1000pF
10%
25V
C29
1000pF
10%
25V
C43
.1uF
C43
.1uF
R69
82.5
R69
82.5
R33
130
R33
130
C22
560pF
10%
50V
C22
560pF
10%
50V
R163
0
R163
0
JP12
CDC_PD
(SHUNT 1-2)
JP12
CDC_PD
(SHUNT 1-2)
1
3
2
R50
22.1
R50
22.1
R36
82.5
R36
82.5
R40
150
R40
150
R111
150
DNI
R111
150
DNI
R52
150
DNI
R52
150
DNI
R61
10K
R61
10K
R162
0
R162
0
68 ohm @ 100MHz
FB3
68 ohm @ 100MHz
FB3
C24
.1uF
C24
.1uF
68 OHM @ 100MHz
FB1
68 OHM @ 100MHz
FB1
C50
.1uF
C50
.1uF
C47
.1uF
C47
.1uF
R38
82.5
R38
82.5
U6
2115-491.52MHZ
DNI
U6
2115-491.52MHZ
DNI
V_CTRL
1
NC
2
GND
3OUT 4
OUTB 5
VCC 6
JP14
VCXO_P
(SHUNT 2-3)
JP14
VCXO_P
(SHUNT 2-3)
1
32
R34
130
R34
130
+
C21
10uF
10V
+
C21
10uF
10V
R45
0
DNI
R45
0
DNI
C31
100pF
C31
100pF
C51
.1uF
C51
.1uF
D3 LED green
LOCK
D3 LED green
LOCK
C46
.1uF
C46
.1uF
JP16
REF_CLK
(SHUNT 2-3)
JP16
REF_CLK
(SHUNT 2-3)
1
32
R66
130
R66
130
R161
0
R161
0
C48
.001uF
C48
.001uF
D1 LED green
VCXO
D1 LED green
VCXO
C52
.1uF
C52
.1uF
SMA
END
J8
Y2A_CLK
SMA
END
J8
Y2A_CLK
1
5234
R49
0
R49
0
+
C53
10uF
10V
+
C53
10uF
10V
C49
.01uF
C49
.01uF
R63
162
R63
162
R32
130
R32
130
R54
130
DNI
R54
130
DNI
+
C32
10uF
10V
+
C32
10uF
10V
C27
.1uF
10%
16V
C27
.1uF
10%
16V
R64
10K
R64
10K
R31
130
R31
130
SMA
END
J9
EXT_REF_CLK
SMA
END
J9
EXT_REF_CLK
1
5234
R60
10K
R60
10K
R70
82.5
R70
82.5
R39
82.5
R39
82.5
C41
.1uF
C41
.1uF
R62
0
R62
0
R43
130
R43
130
R46
82.5
R46
82.5
R29 750R29 750
R160
0
R160
0
C40
.1uF
C40
.1uF
68 OHM @ 100MHz
FB2
68 OHM @ 100MHz
FB2
R28 750R28 750
C39
.1uF
C39
.1uF
R58
82.5
DNI
R58
82.5
DNI
TP1
REF_ADJ
TP1
REF_ADJ
C25
.1uF
C25
.1uF
R110
150
DNI
R110
150
DNI
R30 750R30 750
C38
.1uF
C38
.1uF
+
C54
10uF
10V
+
C54
10uF
10V
R59
10K
R59
10K
R57
150
DNI
R57
150
DNI
R116
150
R116
150
U3
OSC-VECTRON
U3
OSC-VECTRON
REF
1
GND 4
VDD
8OUT 5
C35
.47uF
10%
16V
C35
.47uF
10%
16V
U2
CDCM7005
U2
CDCM7005
VCC 13
Y2B 8
Y2A 7
VCC 6
VCC 5
VCC_CP
33
AVCC
32
NC
34
Y3B 12
Y3A 11
VCC 10
VCC 9
VCC 19
REF_SEL
35
AVCC
39
AVCC
38
SEC_REF
37
PRI_REF
36
VCXO_IN
43
VCXO_INB
42
VCC
41
VBB
40
/RESET or /HOLD 14
VCC 15
Y4A 16
Y4B 17
VCC 18
/PD 1
VCC 2
Y1A 3
Y1B 4
VCC 20
VCC 21
STATUS_VCXO or I_REF_CP 22
STATUS_REF or PRI_SEC_CLK 23
GND 24
PLL_LOCK 25
CTRL_DATA 26
AVCC
27
CTRL_CLK
28 CTRL_LE
29
AVCC
30 CP_OUT
31
VCC
44 VCC
45 Y0A
46 Y0B
47 VCC
48
PWRPAD 49
SMA
END
J6
EXT_VCXO_P
SMA
END
J6
EXT_VCXO_P
1
5234
C33
.1uF
C33
.1uF
R159
0
R159
0
R56
22.1
R56
22.1
J13 USE CONN eNm vcc 4* IDnF -DATA +DATA GNDZ GND USE 7 E 7 5 7 F 7 E 7 T H 059 47pF FBA i 580HM@100MH1 056 658 «3.3V7L0516 +3 3V7LDGIC 4.7m: __ 20v . R113 R114 10K 10K UH U5 1 10E vcc ‘AI 20E u vcc Du 1 R78 22.1 2 m2 m (SW) SW ‘AB 1V2 ‘5 USBDM D1 “5‘ 22" 11 1A4 1v: 2A1 1V4 ‘ USBDP D2 R54 22" 2A2 2V1 2A3 2V2 “ vccwo D3 4‘ m 2A4 2v: GND 2w R89 22.1 L NC‘ D4 <7 n7ahczm="" ‘l="" reset="" de="" 9="" r79="" 22.1="" 2l="" n02="" de="" 10="" r97="" 22.1="" 2l="" 055‘="" d7="" 5="" r95="" 22.1="" 2l="" osco="" rxf="" j3="" ‘="" svaou'r="" txe="" 42="" agnd="" rd="" 43="" +3.3v7logic="" ,,="" gnd="" 7,="" “="" 2mg="" wn="" a“="" 13.3v7log‘c="" fl="" 5="" test="" pwren="" 42="" fi’zasrl="" r108=""><7><7 10k="" uid="" l="" :="" sclk="" shi="" ‘="" )="" cmgcm="" 3h3="" )="" sdenb="" shi="" :="" )="" cthlidata="" 5h3="" cthlile="" 3h3="" sm="" 300)="" _,/="" s="" 74ahc54|="" 1i}="" texas="" instruments="" nib="" da="" c55822="" e="" vm="" size="" document="" number="" b="" u55="" interface="" ale:="" wlednesday.="" august="" 08.="" 2008="" sheet="" 4="" of="">
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3.3V_LOGIC +3.3V_LOGIC
+3.3V_LOGIC
+3.3V_LOGIC
SDIO SH1
SDOSH1
SDENB SH1
CTRL_CLK SH3
CTRL_DATA SH3
CTRL_LE SH3
SCLK SH1
Title
Size Document Number Rev
Date: Sheet of
USB INTERFACE
D
DAC5682Z EVM
B
46Wednesday, August 06, 2008
Title
Size Document Number Rev
Date: Sheet of
USB INTERFACE
D
DAC5682Z EVM
B
46Wednesday, August 06, 2008
Title
Size Document Number Rev
Date: Sheet of
USB INTERFACE
D
DAC5682Z EVM
B
46Wednesday, August 06, 2008
R113
10K
R113
10K
R78 22.1R78 22.1
R81 22.1R81 22.1
R93 100R93 100
R80 100R80 100
R89 22.1R89 22.1
R82 100R82 100
C131
.1uF
C131
.1uF
R97 22.1R97 22.1
U5
FT245RL
U5
FT245RL
USBDM
16
USBDP
15
VCCIO
4
NC1
8
RESET
19
NC2
24
OSCI
27
OSCO
28
3V3OUT
17
AGND
25
GND
7
GND
18
GND
21
TEST
26 PWREN 12
WR 14
D1 5
D7 6
D5 9
D6 10
TXE 22
D4 2
D3 11
RXF 23
D0 1
RD 13
VCC
20
D2 3
68 OHM @ 100MHz
FB4
68 OHM @ 100MHz
FB4
R114
10K
R114
10K
R95 22.1R95 22.1
R96 100R96 100
U11
SN74HC241PW
U11
SN74HC241PW
2Y4 3
1A1
2
1A2
4
1A3
6
1A4
8
2A1
11
2A2
13
2A3
15
2A4
17
GND
10 2Y3 5
2Y2 7
2Y1 9
1Y4 12
1Y3 14
1Y2 16
1Y1 18
2OE 19
1OE
1VCC 20
J13
USB_B_S_F_B_TH
USB_CONN
J13
USB_B_S_F_B_TH
USB_CONN
VCC 1
-DATA 2
+DATA 3
GND 4
GND1
5
GND2
6
R108
10K
R108
10K
C59
47pF
C59
47pF
C56
10nF
C56
10nF
R90 100R90 100
R84 22.1R84 22.1
C130
.1uF
C130
.1uF
+
C58
4.7uF
20V
+
C58
4.7uF
20V
R79 22.1R79 22.1
U10
SN74AHC541PW
U10
SN74AHC541PW
Y8 11
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
GND
10 Y7 12
Y6 13
Y5 14
Y4 15
Y3 16
Y2 17
Y1 18
OE2 19
OE1
1VCC 20
C57
.1uF
C57
.1uF
C61
.1uF
C61
.1uF
C60
47pF
C60
47pF
H.8VD .mw IN ‘ ,_, C72 . (:71 C70 +__ 47m: 012 IUuF :: .010}: /\ 20% MBRBZSISL "W ‘W EANANAJACK ELK V7 V7 J15 GND +I,8VJN H.8VCLK T F37 " 1_r” es OHM @ IDDMHz C78 cm ‘ (:80 NF C79 *__ 47uF IUuF 20% .010}: /\ 20% 10v 25v 10v +I,8VJN H.8VD‘ T F313 " ._/ i 65 OHM @ lDDMHz ; V V +3.3VA EANANAJACK RED Fes " J17 .3.3v IN ,_, wax/4N ._ , es OHM @ IDDMHz C75 (:77 . cu 10F (:70 +__ 47m: IUuF 20% :: .010}: f-\ 20% 10v 25v 10v K BL < 7="">< 7="" jp17="" gnd="" 2="" aviw="" +33="" _="" oewc="" ‘="" f38="" t="" el="" 0="" h="" a="" _="" (shunti-z)="" ;=""><7><7 +3="" exclk="" 1_r”="" hf="" \lla="" v="" v="" da="" 656822="" evm="" size="" document="" numbel="" ev="" 3="" power="" distribu770n="" d="" ale:="" mlonda="" .="" august="" 04.="" 2008="" sheet="" 5="" a!="" 3="" ‘st="" eananajack="" red="" f312="" 420="" mm="" w="" ,_,="" *5vajn="" ._,="" dh="" mbrbzsisl="" ‘9="" zistandoffi="" anquf="" a="" i="" i="" i="" l="" i="" i="" 4:="" i="" 1p4="" tps="" tps="" gnd="" gnd="" gnd="" gnd="" 31373737="" ziscrewa="" e="" scnzw="" “wan="" mn="" x="" 3/9="" e="" zistandoffz="" zistandoffa="" zistando="" [e]="" 1"}="" texas="" instruments="">
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3.3V_IN
+1.8V_IN +5VA_IN
+3.3VA
+1.8VCLK+1.8V_IN
+1.8VD +5VA
+1.8VD1+1.8V_IN
+3.3VCLK
+3.3V_LOGIC
Title
Size Document Number Rev
Date: Sheet of
POWER DISTRIBUTION
D
DAC5682Z EVM
B
56Monday, August 04, 2008
Title
Size Document Number Rev
Date: Sheet of
POWER DISTRIBUTION
D
DAC5682Z EVM
B
56Monday, August 04, 2008
Title
Size Document Number Rev
Date: Sheet of
POWER DISTRIBUTION
D
DAC5682Z EVM
B
56Monday, August 04, 2008
D14
MBRB2515L
D14
MBRB2515L
1
2
34
68 OHM @ 100MHz
FB7
68 OHM @ 100MHz
FB7
Z_STANDOFF1
STANDOFF ALUM HEX 4-40 x .500
Z_STANDOFF1
STANDOFF ALUM HEX 4-40 x .500
C79
.01uF
C79
.01uF
J15
BANANA_JACK_BLK
GND
J15
BANANA_JACK_BLK
GND
C87
.01uF
C87
.01uF
68 OHM @ 100MHz
FB12
68 OHM @ 100MHz
FB12
Z_STANDOFF2
STANDOFF ALUM HEX 4-40 x .500
Z_STANDOFF2
STANDOFF ALUM HEX 4-40 x .500
TP4
GND
TP4
GND
C70
.01uF
C70
.01uF
+
C77
47uF
10V
20%
+
C77
47uF
10V
20%
+
C71
10uF
10V
+
C71
10uF
10V
JP17
+3.3V_IN
(SHUNT 1-2)
JP17
+3.3V_IN
(SHUNT 1-2)
1
32
J20
BANANA_JACK_RED
+5VA_IN
J20
BANANA_JACK_RED
+5VA_IN
C75
1uF
20%
25V
C75
1uF
20%
25V
Z_SCREW3
SCREW PANHEAD 4-40 x 3/8
Z_SCREW3
SCREW PANHEAD 4-40 x 3/8
C84
.01uF
C84
.01uF
TP6
GND
TP6
GND
TP5
GND
TP5
GND
+
C74
10uF
10V
+
C74
10uF
10V
D12
MBRB2515L
D12
MBRB2515L
1
2
34
+
C80
10uF
10V
+
C80
10uF
10V
Z_STANDOFF3
STANDOFF ALUM HEX 4-40 x .500
Z_STANDOFF3
STANDOFF ALUM HEX 4-40 x .500
+
C72
47uF
10V
20%
+
C72
47uF
10V
20%
+
C88
10uF
10V
+
C88
10uF
10V
C76
.01uF
C76
.01uF
Z_STANDOFF4
STANDOFF ALUM HEX 4-40 x .500
Z_STANDOFF4
STANDOFF ALUM HEX 4-40 x .500
TP2
GND
TP2
GND
+
C81
47uF
10V
20%
+
C81
47uF
10V
20%
68 OHM @ 100MHz
FB8
68 OHM @ 100MHz
FB8
TP7
GND
TP7
GND
Z_SCREW4
SCREW PANHEAD 4-40 x 3/8
Z_SCREW4
SCREW PANHEAD 4-40 x 3/8
+
C89
47uF
10V
20%
+
C89
47uF
10V
20%
68 OHM @ 100MHz
FB13
68 OHM @ 100MHz
FB13
C121
.01uF
C121
.01uF
J14
BANANA_JACK_RED
+1.8V_IN
J14
BANANA_JACK_RED
+1.8V_IN
J17
BANANA_JACK_RED
+3.3V_IN
J17
BANANA_JACK_RED
+3.3V_IN
C122
1uF
20%
25V
C122
1uF
20%
25V
68 OHM @ 100MHz
FB6
68 OHM @ 100MHz
FB6
C83
1uF
20%
25V
C83
1uF
20%
25V
C78
1uF
20%
25V
C78
1uF
20%
25V
J19
BANANA_JACK_BLK
GND
J19
BANANA_JACK_BLK
GND
+
C123
47uF
10V
20%
+
C123
47uF
10V
20%
C86
1uF
20%
25V
C86
1uF
20%
25V
D13
MBRB2515L
D13
MBRB2515L
1
2
34
+
C119
47uF
10V
20%
+
C119
47uF
10V
20%
68 OHM @ 100MHz
FB9
68 OHM @ 100MHz
FB9
Z_SCREW1
SCREW PANHEAD 4-40 x 3/8
Z_SCREW1
SCREW PANHEAD 4-40 x 3/8
+
C126
10uF
10V
+
C126
10uF
10V
+
C120
10uF
10V
+
C120
10uF
10V
C124
.01uF
C124
.01uF
+
C85
47uF
10V
20%
+
C85
47uF
10V
20%
J18
BANANA_JACK_BLK
GND
J18
BANANA_JACK_BLK
GND
TP3
+3.3V_IN
TP3
+3.3V_IN
68 OHM @ 100MHz
FB5
68 OHM @ 100MHz
FB5
C125
1uF
20%
25V
C125
1uF
20%
25V
Z_SCREW2
SCREW PANHEAD 4-40 x 3/8
Z_SCREW2
SCREW PANHEAD 4-40 x 3/8
C69
1uF
20%
25V
C69
1uF
20%
25V
+
C82
10uF
10V
+
C82
10uF
10V
1"} TEXAS INSTRUMENTS NOTES: €31; 1) DNI = DO NOT INSTALL . 2) FOR DAcsssl/Blz OPTION ALL 019 COMPONENTS ON SHEET 6 ARE DNI Rue H R149 "5 .OluFHDNI "5 SHI IOUTE‘ > Run “‘55 L12 R138 65m ° 0 60.4 i 6100 Lu AJDF anH DNI c112 (2110 ’ 22p: :: 2.7m: DNI RM 903 H L15 H anH SH! |0u152> F"53 mes L13 R151 r 0 0 68nH 60.4 i nus R147 634 63‘ nus Rm 0 o «SVA FBID 680bm®100MHz c115 AJuF qu ,: 999 mm :7 v rag cws esohm@ Dwuzmuu .qu 1000pF 20v <82--zz &="">o 00 —‘— N01 E vcm ‘“ m CHE GND GND ‘ CH3 5m [fin || A H 93;, \ \ ' " W H +§yA \ \ \ \ H168 SHI IOUTA‘ ) i \ \ H H167 SHI IDUTA2> ‘ NIB DA C55822 E VM 3 Size Document Number ev B MODULA TOR D I ate: Frliday. August 22. 2005 Sheet 6 a!
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+5VA
+5VA
+5VA
+5VA
IOUTB2SH1
IOUTB1SH1
IOUTA2SH1
IOUTA1SH1
Title
Size Document Number Rev
Date: Sheet of
MODULATOR
D
DAC5682Z EVM
B
66Friday, August 22, 2008
Title
Size Document Number Rev
Date: Sheet of
MODULATOR
D
DAC5682Z EVM
B
66Friday, August 22, 2008
Title
Size Document Number Rev
Date: Sheet of
MODULATOR
D
DAC5682Z EVM
B
66Friday, August 22, 2008
1) DNI = DO NOT INSTALL
NOTES:
2) FOR DAC5681/81Z OPTION ALL
COMPONENTS ON SHEET 6 ARE DNI
R158
115
R158
115
R166
0
R166
0
R168
0
R168
0
R165
0
R165
0
R143
634
R143
634
R41
90.9
R41
90.9
R137
0
R137
0
R141
0
R141
0
C114
.1uF
C114
.1uF
68 ohm @ 100MHz
FB10
68 ohm @ 100MHz
FB10
R145
0
R145
0
L8
10nH
L8
10nH
1 2
C106
1000pF
C106
1000pF
C113
100pF
C113
100pF
C73
4.7pF
DNI
C73
4.7pF
DNI
C19
.01uF DNI
C19
.01uF DNI
C116
4.7pF
DNI
C116
4.7pF
DNI
68 ohm @ 100MHz
FB11
68 ohm @ 100MHz
FB11
U8
TRF3703-33
U8
TRF3703-33
NC1
1
GND
2
LOP
3
LON
4
GND
5
NC2
6
NC3
7
GND
8
QN
9
QP
10
GND
11
GND
12
VCCI 18
GND 17
RFOUT 16
NC5 15
GND 14
NC4 13
GND 19
GND 20
IP 21
IN 22
GND 23
VCC2 24
PWRPAD 25
R149
115
R149
115
R152
60.4
R152
60.4
R157
115
R157
115
SMA
END
J23
RF_LO_IN
SMA
END
J23
RF_LO_IN
1
5234
R147
634
R147
634
R153
0
R153
0
R142
0
R142
0
C102
22pF
C102
22pF
L10
68nH
L10
68nH
1 2
C118
.01uF
DNI
C118
.01uF
DNI
R138
60.4
R138
60.4
C112
2.2pF
DNI
C112
2.2pF
DNI
C28
.01uF DNI
C28
.01uF DNI
R144
634
R144
634
R167
0
R167
0
R156
0
R156
0
R146
115
R146
115
C103
22pF
C103
22pF
L15
10nH
L15
10nH
1 2
R155
0
R155
0
R151
60.4
R151
60.4
L12
68nH
L12
68nH
1 2
R140
0
R140
0
L13
68nH
L13
68nH
1 2
L11
68nH
L11
68nH
1 2
L9
10nH
L9
10nH
1 2
C107
.1uF
C107
.1uF
R150
90.9
R150
90.9
C111
2.7pF
C111
2.7pF
C99
3.3pF
C99
3.3pF
L14
10nH
L14
10nH
1 2
+
C108
4.7uF
20V
+
C108
4.7uF
20V
+
C115
4.7uF
20V
+
C115
4.7uF
20V
C110
2.7pF
C110
2.7pF
R148
634
R148
634
C100
4.7pF
DNI
C100
4.7pF
DNI
SMA
END
J16
RFOUT
SMA
END
J16
RFOUT
1
5234
C105
2.2pF
DNI
C105
2.2pF
DNI
R154
60.4
R154
60.4
C104
1000pF
C104
1000pF
C101
4.7pF
DNI
C101
4.7pF
DNI
C109
3.3pF
C109
3.3pF
C117
.01uF
DNI
C117
.01uF
DNI
R139
49.9
R139
49.9
C26
.01uF DNI
C26
.01uF DNI
C30
.01uF DNI
C30
.01uF DNI
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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must haveelectronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be completein terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmentalmeasures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit doesnot fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.
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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radiofrequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which aredesigned to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments maycause interference with radio communications, in which case the user at his own expense will be required to take whatever measures maybe required to correct this interference.
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 1.8 V to 5.0 V and the output voltage range of 0.0 V to 3.3 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questionsconcerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 60 °C. The EVM is designed to operateproperly with certain components above 60 °C as long as the input and output ranges are maintained. These components include but arenot limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identifiedusing the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2008, Texas Instruments Incorporated
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