TS80C31X2, AT80C31X2 Datasheet by Microchip Technology

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A IIIEI. 41m
Features
•
80C31 Compatible
•
8031 pin and instruction compatible
•
Four 8-bit I/O ports
•
Two 16-bit timer/counters
•
128 bytes scratchpad RAM
•
High-Speed Architecture
•
40 MHz @ 5V, 30MHz @ 3V
•
X2 Speed Improvement capability (6 clocks/machine cycle)
•
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V)
•
Dual Data Pointer
•
Asynchronous port reset
•
Interrupt Structure with
•
5 Interrupt sources,
•
4 priority level interrupt system
•
Full duplex Enhanced UART
•
Framing error detection
•
Automatic address recognition
•
Power Control modes
•
Idle mode
•
Power-down mode
•
Power-off Flag
•
Once mode (On-chip Emulation)
•
Power supply: 4.5-5.5V, 2.7-5.5V
•
Temperature ranges: Commercial (0 to 70
o
C) and Industrial (-40 to 85
o
C)
•
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1 (13.9 footprint)
1. Description
TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS
single chip 8-bit microcontroller.
The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM,
a 5-source, 4 priority level interrupt system, an on-chip oscilator and two
timer/counters.
In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and a X2 speed improvement
mechanism.
The fully static design of the TS80C31X2 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
The TS80C31X2 has 2 software-selectable modes of reduced activity for further
reduction in power consumption. In the idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In the power-down mode the
RAM is saved and all other functions are inoperative.
8-bit CMOS
Microcontroller
ROMless
TS80C31X2
AT80C31X2
4428E–8051–02/08
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2. Block Diagram
Timer 0 INT
RAM
128x8
T0
T1
RxD
TxD
WR
RD
EA
PSEN
ALE/
XTAL2
XTAL1
EUART
CPU
Timer 1
INT1
Ctrl
INT0
(1)
(1)
C51
CORE
(1) (1) (1) (1)
Port 0
P0
Port 1 Port 2 Port 3
Parallel I/O Ports & Ext. Bus
P1
P2
P3
IB-bus
RESET
PROG
(1)(1)
(1): Alternate function of Port 3
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4. SFR Mapping
The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3
• Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• Power and clock control registers: PCON
• Interrupt system registers: IE, IP, IPH
• Others: CKCON
Table 4-1. All SFRs with their address and their reset value
Bit
addressable Non Bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h FFh
F0h B
0000 0000 F7h
E8h EFh
E0h ACC
0000 0000 E7h
D8h DFh
D0h PSW
0000 0000 D7h
C8h CFh
C0h C7h
B8h IP
XXX0 0000
SADEN
0000 0000 BFh
B0h P3
1111 1111
IPH
XXX0 0000 B7h
A8h IE
0XX0 0000
SADDR
0000 0000 AFh
A0h P2
1111 1111
AUXR1
XXXX XXX0 A7h
98h SCON
0000 0000
SBUF
XXXX XXXX 9Fh
90h P1
1111 1111 97h
88h TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
CKCON
XXXX XXX0 8Fh
80h P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Reserved
A IIIEL .I:I:I:I:I:I:I:I:I:I:I_ 1 1_u_n_n_n_u_u_n_n_u_u_t nnnnjnn 7 Dunn .LF:I:L.LF:L.LF:I:L.LF:I:I:LF:I:I:L
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5. Pin Configuration
5 4 3 2 1 6 44 43 42 41 40
P1.4
P1.0
P1.1
P1.3
P1.2
VSS1/NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE
PSEN
EA
NIC*
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
43 42 41 40 3944 38 37 36 35 34
P1.4
P1.0
P1.1
P1.3
P1.2
VSS1/NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE
PSEN
EA
NIC*
P2.7/A15
P2.5/A13
P2.6/A14
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
NIC*
NIC*
*NIC: No Internal Connection
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
PLCC44
33
32
31
30
29
28
27
26
25
24
23
PQFP44
1
2
3
4
5
6
7
8
9
10
11
18 19 20 21 22 23 24 25 26 27 28
12 13 14 15 16 17 18 19 20 21 22
VQFP44VQFP44
P1.7
RST
P3.0/RxD
P3.1/TxD
P1.3
1
P1.5
P3.2/INT0
P3.3/INT1
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS P2.0 / A8
P2.1 / A9
P2.2 / A10
P2.3 / A11
P2.4 / A12
P0.4 / A4
P0.6 / A6
P0.5 / A5
P0.7 / A7
ALE/PROG
PSEN
EA/VPP
P2.7 / A15
P2.5 / A13
P2.6 / A14
P1.0 / T2
P1.1 / T2EX
VCC
P0.0 / A0
P0.1 / A1
P0.2 / A2
P0.3 / A3
PDIL/
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CDIL40
P1.6
P1.4
P1.2
P3.4/T0
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Mnemonic
Pin Number
Type Name And FunctionDIL LCC VQFP 1.4
V
SS
20 22 16 I Ground: 0V reference
Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection.
V
CC
40 44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down
operation
P0.0-P0.7 39-
32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high impedance inputs. Port 0 pins must be
polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0
is also the multiplexed low-order address and data bus during access to external
program and data memory. In this application, it uses strong internal pull-up when
emitting 1s.
P1.0-P1.7 1-8 2-9 40-44
1-3
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current
because of the internal pull-ups.
P2.0-P2.7 21-
28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current
because of the internal pull-ups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
P3.0-P3.7 10-
17 11,
13-19
5,
7-13
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 family, as listed below.
10 11 5 I RXD (P3.0): Serial input port
11 13 7 O TXD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): External interrupt 0
13 15 9 I INT1 (P3.3): External interrupt 1
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External data memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe
Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to V
SS
permits a power-on reset using
only an external capacitor to V
CC.
ALE 30 33 27 O (I) Address Latch Enable: Output pulse for latching the low byte of the address during
an access to external memory. In normal operation, ALE is emitted at a constant
rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external
timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory.
PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
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EA 31 35 29 I External Access Enable: EA must be externally held low to enable the device to
fetch code from external program memory locations.
XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier
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6. TS80C31X2 Enhanced Features
In comparison to the original 80C31, the TS80C31X2 implements some new features, which
are
:
• The X2 option.
• The Dual Data Pointer.
• The 4 level interrupt priority system.
• The power-off flag.
• The ONCE mode.
• Enhanced UART
6.1 X2 Feature
The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2”
provides the following advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically operating frequency by 2 in operating and
idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-
nal and the main clock input of the core (phase generator). This divider may be disabled by
software.
6.1.1 Description
The clock for the whole circuit and peripheral is first divided by two before being used by the
CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2
mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to
60%. Figure 6-1. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 ris-
ing edge to avoid glitches when switching from X2 to STD mode. Figure 6-2. shows the mode
switching waveforms.
Figure 6-1. Clock Generation Diagram
XTAL1 2
CKCON reg
X2
state machine: 6 clock cycles.
CPU control
F
OSC
F
XTAL
0
1
XTAL1:2
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Figure 6-2. Mode Switching Waveforms
The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per
instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD
mode). Setting this bit activates the X2 feature (X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that
all peripherals using clock frequency as time reference (UART, timers) will have their time refer-
ence divided by two. For example a free running timer generating an interrupt every 20 ms will
then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.
Reset Value = XXXX XXX0b
Not bit addressable
For further details on the X2 feature, please refer to ANM072 available on the web
(http://www.atmel-wm.com)
Table 6-1. CKCON Register
CKCON - Clock Control Register (8Fh)
7 6 5 4 3 2 1 0
- - - - - - - X2
Bit
Number
Bit
Mnemonic Description
7 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 X2
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, F
OSC
=F
XTAL
/2).
Set to select 6 clock periods per machine cycle (X2 mode, F
OSC
=F
XTAL
).
/ /’ 41m
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AT/TS80C31X2
7. Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size in a
number of ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that address the external memory, and a
single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer
to Figure 7-1).
Figure 7-1. Use of Dual Pointer
Reset Value = XXXX XXX0
Not bit addressable
Table 7-1. AUXR1: Auxiliary Register 1
7 6 5 4 3 2 1 0
- -3 - - - - - DPS
Bit
Number
Bit
Mnemonic Description
7 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 DPS
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
External Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
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8. Application
Software can take advantage of the additional data pointers to both increase speed and reduce
code size, for example, block operations (copy, compare, search ...) are well served by using
one data pointer as a ’source’ pointer and the other one as a "destination" pointer.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000 MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6 JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR.
However, note that the INC instruction does not directly force the DPS bit to a particular state,
but simply toggles it. In simple routines, such as the block move example, only the fact that DPS
is toggled in the proper sequence matters, not its actual value. In other words, the block move
routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc-
tion (INC AUXR1), the routine will exit with DPS in the opposite state.
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9. TS80C31X2 Serial I/O Port
The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31.
It provides both synchronous and asynchronous communication modes. It operates as an Uni-
versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2
and 3). Asynchronous transmission and reception can occur simultaneously and at different
baud rates
Serial I/O port includes the following enhancements:
• Framing error detection
• Automatic address recognition
9.1 Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1).
Figure 9-1. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
9-3.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 9-
2. and Figure 9-3.).
Figure 9-2. UART Timings in Mode 1
1,11 11F b 1,11 10cm
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AT/TS80C31X2
Figure 9-3. UART Timings in Modes 2 and 3
9.2 Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor commu-
nication feature by allowing the serial port to examine the address of each incoming command
frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON
register to generate an interrupt. This ensures that the CPU is not interrupted by command
frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configu-
ration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received
command frame address matches the device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broad-
cast address.
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2
bit in SCON register in mode 0 has no effect).
9.3 Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register
is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given
address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The
following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR 0101 0110b
SADEN 1111 1100b
Given 0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A: SADDR 1111 0001b
SADEN 1111 1010b
Given 1111 0X0Xb
Slave B: SADDR 1111 0011b
SADEN 1111 1001b
Given 1111 0XX1b
A]: r: A]: r: A]: r: 1,11 1013b 1,11 10: b 1,11 11C,b E
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Slave C: SADDR 1111 0010b
SADEN 1111 1101b
Given 1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate
with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves
B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111
0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1
clear, and bit 2 clear (e.g. 1111 0001b).
9.4 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with
zeros defined as don’t-care bits, e.g.:
SADDR 0101 0110b
SADEN 1111 1100b
Broadcast =SADDR OR SADEN 1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most
applications, a broadcast address is FFh. The following is an example of using broadcast
addresses:
Slave A: SADDR 1111 0001b
SADEN 1111 1010b
Broadcast 1111 1X11b,
Slave B: SADDR 1111 0011b
SADEN 1111 1001b
Broadcast 1111 1X11B,
Slave C: SADDR= 1111 0010b
SADEN 1111 1101b
Broadcast 1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of
the slaves, the master must send an address FFh. To communicate with slaves A and B, but not
slave C, the master can send and address FBh.
9.5 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast
addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any
address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not
support automatic address recognition.
Reset Value = 0000 0000b
Not bit addressable
Table 9-1. SADEN - Slave Address Mask Register (B9h)
7 6 5 4 3 2 1 0
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Reset Value = 0000 0000b
Not bit addressable
Table 9-2. SADDR - Slave Address Register (A9h)
7 6 5 4 3 2 1 0
SMD 5M1 Mode Descnglwon Baud Rate E
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AT/TS80C31X2
Reset Value = 0000 0000b
Bit addressable
Table 9-3. SCON Register -- SCON - Serial Control Register (98h)
7 6 5 4 3 2 1 0
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number
Bit
Mnemonic Description
7 FE
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
6 SM1
Serial port Mode bit 1
SM0 SM1 Mode Description Baud Rate
0 0 0 Shift Register F
XTAL
/12 (/6 in X2 mode)
0 1 1 8-bit UART Variable
1 0 2 9-bit UART F
XTAL
/64 or F
XTAL
/32 (/32, /16 in X2 mode)
1 1 3 9-bit UART Variable
5 SM2
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be
cleared in mode 0.
4 REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3 TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2 RB8
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1 TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes.
0 RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 9-2. and Figure 9-3. in the other modes.
41m
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Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect
the value of this bit.
Table 9-4. PCON Register -- PCON - Power Control Register (87h)
7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number
Bit
Mnemonic Description
7 SMOD1 Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 POF
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
3 GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2 GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1 PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0 IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
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10. Interrupt System
The TS80C31X2 has a total of 5 interrupt vectors: two external interrupts (INT0 and INT1), two
timer interrupts (timers 0 and 1) and the serial port interrupt. These interrupts are shown in Fig-
ure 10-1.
Figure 10-1. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register (See Table 10-2.Table 10-3.). This register also contains a global
disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by
setting or clearing a bit in the Interrupt Priority register (See Table 10-3.) and in the Interrupt Pri-
ority High register (See Table 10-4.). shows the bit values and priority levels associated with
each combination.
Table 10-1. Priority Level Bit Values
IE1
0
3
High priority
interrupt
Interrupt
polling
sequence, decreasing
from high to low priority
Low priority
interrupt
Global DisableIndividual Enable
TI
RI
TF0
INT0
INT1
TF1
IPH, IP
IE0
0
3
0
3
0
3
0
3
IPH.x IP.x Interrupt Level Priority
0 0 0 (Lowest)
011
102
1 1 3 (Highest)
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A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-
ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of
higher priority level is serviced. If interrupt requests of the same priority level are received simul-
taneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence.
Table 10-2. IE Register -- IE - Interrupt Enable Register (A8h)
Reset Value = 0XX0 0000b
Bit addressable
76543210
EA - - ES ET1 EX1 ET0 EX0
Bit
Number
Bit
Mnemonic Description
7 EA
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its
own interrupt enable bit.
6 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 ES
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
3 ET1
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2 EX1
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
1 ET0
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0 EX0
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
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Table 10-3. IP Register -- IP - Interrupt Priority Register (B8h)
Reset Value = XXX0 0000b
Bit addressable
7 6 5 4 3 2 1 0
- - - PS PT1 PX1 PT0 PX0
Bit
Number
Bit
Mnemonic Description
7 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 PS Serial port Priority bit
Refer to PSH for priority level.
3 PT1 Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2 PX1 External interrupt 1 Priority bit
Refer to PX1H for priority level.
1 PT0 Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0 PX0 External interrupt 0 Priority bit
Refer to PX0H for priority level.
E u E Pnumty Level w m Pnumty Level M u Pnumty Level m U Pnumty Level M m Pnumty Level
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Table 10-4. IPH Register -- IPH - Interrupt Priority High Register (B7h)
Reset Value = XXX0 0000b
Not bit addressable
7 6 5 4 3 2 1 0
- - - PSH PT1H PX1H PT0H PX0H
Bit
Number
Bit
Mnemonic Description
7 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 PSH
Serial port Priority High bit
PSH PS Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
3 PT1H
Timer 1 overflow interrupt Priority High bit
PT1H PT1 Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
2 PX1H
External interrupt 1 Priority High bit
PX1H PX1 Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
1 PT0H
Timer 0 overflow interrupt Priority High bit
PT0H PT0 Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
0 PX0H
External interrupt 0 Priority High bit
PX0H PX0 Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
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11. Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into
the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the
interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack
Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain
their data during Idle. The port pins hold the logical states they had at the time Idle was acti-
vated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0
to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and follow-
ing RETI the next instruction to be executed will be the one following the instruction that put the
device into idle.
The flag bits GF0 and GF1 can be used to give and indication if an interrupt occured during nor-
mal operation or during an Idle. For example, an instruction that activates Idle can also set one
or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can exam-
ine the flag bits.
The over way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is
still running, the hardware reset needs to be held active for only two machine cycles (24 oscilla-
tor periods) to complete the reset.
11.1 Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to Table 9-4.,
PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down
mode is the last instruction executed. The internal RAM and SFRs retain their value until the
power-down mode is terminated. V
CC
can be lowered to save further power. Either a hardware
reset or an external interrupt can cause an exit from power-down. To properly terminate power-
down, the reset or external interrupt should not be executed before V
CC
is restored to its normal
operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt
must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed
in Figure 11-1. When both interrupts are enabled, the oscillator restarts as soon as one of the
two inputs is held low and power down exit will be completed when the first input will be
released. In this case the higher priority interrupt service routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one fol-
lowing the instruction that put TS80C31X2 into power-down mode.
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AT/TS80C31X2
Figure 11-1. Power-Down Exit Waveform
Exit from power-down by reset redefines all the SFRs, exit from power-down by external inter-
rupt does no affect the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM
content.
Note: NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is
unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is
not entered.
Table 11-1. The state of ports during idle and power-down modes
Mode
Program
Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle External 1 1 Floating Port Data Address Port Data
Power Down External 0 0 Floating Port Data Port Data Port Data
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12. ONCE
TM
Mode (ON Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using TS80C31X2 without remov-
ing the circuit from the board. The ONCE mode is invoked by driving certain pins of the
TS80C31X2; the following sequence must be exercised:
• Pull ALE low while the device is in reset (RST high) and PSEN is high.
• Hold ALE low as RST is deactivated.
While the TS80C31X2 is in ONCE mode, an emulator or test CPU can be used to drive the cir-
cuit Table 26. shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 12-1. External Pin Status during ONCE Mode
ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1/2
Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up Active
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13. Power-Off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”
reset.
A cold start reset is the one induced by V
CC
switch-on. A warm start reset occurs while V
CC
is still
applied to the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (See Table 13-1.). POF is set by hardware
when V
CC
rises from 0 to its nominal voltage. The POF can be set or cleared by software allow-
ing the user to determine the type of reset.
The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading
POF bit will return indeterminate value.
Table 13-1. PCON Register -- PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit addressable
7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number
Bit
Mnemonic Description
7 SMOD1 Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 POF
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when V
CC
rises from 0 to its nominal voltage. Can also be set by software.
3 GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2 GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1 PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0 IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
41m
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14. Electrical Characteristics
14.1 Absolute Maximum Ratings
(1)
Ambiant Temperature Under Bias:
C = commercial0°C to 70°C
I = industrial -40°C to 85°C
Storage Temperature-65°C to + 150°C
Voltage on V
CC
to V
SS
-0.5 V to + 7 V
Voltage on V
PP
to V
SS
-0.5 V to + 13 V
Voltage on Any Pin to V
SS
-0.5 V to V
CC
+ 0.5 V
Power Dissipation1 W
(2)
Note: 1.
S
tresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rating conditions may affect device
reliability.
2. This value is based on the maximum allowable die temperature and the thermal resistance of
the package.
14.2 Power consumption measurement
Since the introduction of the first C51 devices, every manufacturer made operating Icc measure-
ments under reset, which made sense for the designs were the CPU was running under reset. In
Atmel Wireless & Microcontrollers new devices, the CPU is no more active during reset, so the
power consumption is very low but is not really representative of what will happen in the cus-
tomer system. That’s why, while keeping measurements under Reset, Atmel Wireless &
Microcontrollers presents a new way to measure the operating Icc:
Using an internal test ROM, the following code is executed:
Label: SJMP Label (80 FE)
Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not con-
nected and XTAL1 is driven by the clock.
This is much more representative of the real operating Icc.
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14.3 DC Parameters for Standard Voltage
T
A
= 0°C to +70°C; V
SS
= 0 V; V
CC
= 5 V ± 10%; F = 0 to 40 MHz.
T
A
= -40°C to +85°C; V
SS
= 0 V; V
CC
= 5 V ± 10%; F = 0 to 40 MHz.
Table 14-1. DC Parameters in Standard Voltage
Symbol Parameter Min Typ Max Unit Test Conditions
V
IL
Input Low Voltage -0.5 0.2 V
CC
- 0.1 V
V
IH
Input High Voltage except XTAL1, RST 0.2 V
CC
+ 0.9 V
CC
+ 0.5 V
V
IH1
Input High Voltage, XTAL1, RST 0.7 V
CC
V
CC
+ 0.5 V
V
OL
Output Low Voltage, ports 1, 2, 3
(6)
0.3
0.45
1.0
V
V
V
I
OL
= 100 µA
(4)
I
OL
= 1.6 mA
(4)
I
OL
= 3.5 mA
(4)
V
OL1
Output Low Voltage, port 0
(6)
0.3
0.45
1.0
V
V
V
I
OL
= 200 µA
(4)
I
OL
= 3.2 mA
(4)
I
OL
= 7.0 mA
(4)
V
OL2
Output Low Voltage, ALE, PSEN
0.3
0.45
1.0
V
V
V
I
OL
= 100 µA
(4)
I
OL
= 1.6 mA
(4)
I
OL
= 3.5 mA
(4)
V
OH
Output High Voltage, ports 1, 2, 3
V
CC
- 0.3
V
CC
- 0.7
V
CC
- 1.5
V
V
V
I
OH
= -10 µA
I
OH
= -30 µA
I
OH
= -60 µA
V
CC
= 5 V ± 10%
V
OH1
Output High Voltage, port 0
V
CC
- 0.3
V
CC
- 0.7
V
CC
- 1.5
V
V
V
I
OH
= -200 µA
I
OH
= -3.2 mA
I
OH
= -7.0 mA
V
CC
= 5 V ± 10%
V
OH2
Output High Voltage,ALE, PSEN
V
CC
- 0.3
V
CC
- 0.7
V
CC
- 1.5
V
V
V
I
OH
= -100 µA
I
OH
= -1.6 mA
I
OH
= -3.5 mA
V
CC
= 5 V ± 10%
R
RST
RST Pulldown Resistor 50 90
(5)
200 kΩ
I
IL
Logical 0 Input Current ports 1, 2 and 3 -50 µA Vin = 0.45 V
I
LI
Input Leakage Current ±10 µA 0.45 V < Vin < V
CC
I
TL
Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 µA Vin = 2.0 V
C
IO
Capacitance of I/O Buffer 10 pF Fc = 1 MHz
T
A
= 25°C
I
PD
Power Down Current 20
(5)
50 µA 2.0 V < V
CC <
5.5 V
(3)
I
CC
under
RESET
Power Supply Current Maximum values, X1
mode:
(7)
1 + 0.4 Freq
(MHz)
@12MHz 5.8
@16MHz 7.4 mA V
CC
= 5.5 V
(1)
I
CC
operating
Power Supply Current Maximum values, X1
mode:
(7)
3 + 0.6 Freq
(MHz)
@12MHz 10.2
@16MHz 12.6
mA V
CC
= 5.5 V
(8)
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14.4 DC Parameters for Low Voltage
T
A
= 0°C to +70°C; V
SS
= 0 V; V
CC
= 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz.
T
A
= -40°C to +85°C; V
SS
= 0 V; V
CC
= 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz.
Table 14-2. DC Parameters for Low Voltage
Note: 1. I
CC
under reset is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns (see Figure 14-5.), V
IL
= V
SS
+ 0.5 V,
I
CC
idle
Power Supply Current Maximum values, X1
mode:
(7)
0.25+0.3 Freq
(MHz)
@12MHz 3.9
@16MHz 5.1
mA V
CC
= 5.5 V
(2)
Symbol Parameter Min Typ Max Unit Test Conditions
Symbol Parameter Min Typ Max Unit Test Conditions
V
IL
Input Low Voltage -0.5 0.2 V
CC
- 0.1 V
V
IH
Input High Voltage except XTAL1, RST 0.2 V
CC
+ 0.9 V
CC
+ 0.5 V
V
IH1
Input High Voltage, XTAL1, RST 0.7 V
CC
V
CC
+ 0.5 V
V
OL
Output Low Voltage, ports 1, 2, 3
(6)
0.45 V I
OL
= 0.8 mA
(4)
V
OL1
Output Low Voltage, port 0, ALE, PSEN
(6)
0.45 V I
OL
= 1.6 mA
(4)
V
OH
Output High Voltage, ports 1, 2, 3 0.9 V
CC
V I
OH
= -10 µA
V
OH1
Output High Voltage, port 0, ALE, PSEN 0.9 V
CC
V I
OH
= -40 µA
I
IL
Logical 0 Input Current ports 1, 2 and 3 -50 µA Vin = 0.45 V
I
LI
Input Leakage Current ±10 µA 0.45 V < Vin < V
CC
I
TL
Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 µA Vin = 2.0 V
R
RST
RST Pulldown Resistor 50 90
(5)
200 kΩ
CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz
T
A
= 25°C
I
PD
Power Down Current 20
(5)
10
(5)
50
30 µAV
CC
= 2.0 V to 5.5 V
(3)
V
CC
= 2.0 V to 3.3 V
(3)
I
CC
under
RESET
Power Supply Current Maximum values, X1
mode:
(7)
1 + 0.2 Freq
(MHz)
@12MHz 3.4
@16MHz 4.2
mA V
CC
= 3.3 V
(1)
I
CC
operating
Power Supply Current Maximum values, X1
mode:
(7)
1 + 0.3 Freq
(MHz)
@12MHz 4.6
@16MHz 5.8 mA V
CC
= 3.3 V
(8)
I
CC
idle
Power Supply Current Maximum values, X1
mode:
(7)
0.15 Freq
(MHz) + 0.2
@12MHz 2
@16MHz 2.6
mA V
CC
= 3.3 V
(2)
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4428E–8051–02/08
AT/TS80C31X2
V
IH
= V
CC
- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V
CC
. I
CC
would be slightly higher if a crystal
oscillator used..
2. Idle I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns,
V
IL
= V
SS
+ 0.5 V, V
IH
= V
CC
- 0.5 V; XTAL2 N.C; Port 0 = V
CC
; EA = RST = V
SS
(see Figure 14-
3.).
3. Power Down I
CC
is measured with all output pins disconnected; EA = V
SS
, PORT 0 = V
CC
;
XTAL2 NC.; RST = V
SS
(see Figure 14-4.).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed
on the V
OL
s of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharg-
ing into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus
operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may
exceed 0.45V with maxi V
OL
peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature and 5V.
6. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin: 10 mA
Maximum I
OL
per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I
OL
for all output pins: 71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guar-
anteed to sink current greater than the listed test conditions.
7. For other values, please contact your sales office.
8. Operating I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
=
5 ns (see Figure 14-5.), V
IL
= V
SS
+ 0.5 V,
V
IH
= V
CC
- 0.5V; XTAL2 N.C.; EA = Port 0 = V
CC
; RST = V
SS
. The internal ROM runs the code
80 FE (label: SJMP label). I
CC
would be slightly higher if a crystal oscillator is used. Measure-
ments are made with OTP products when possible, which is the worst case.
Figure 14-1. I
CC
Test Condition, under reset
mg; L? + 7 E,
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4428E–8051–02/08
AT/TS80C31X2
Figure 14-2. Operating I
CC
Test Condition
Figure 14-3. I
CC
Test Condition, Idle Mode
Figure 14-4. I
CC
Test Condition, Power-Down Mode
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AT/TS80C31X2
Figure 14-5. Clock Signal Waveform for I
CC
Tests in Active and Idle Modes
14.5 AC Parameters
14.5.1 Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The
other characters, depending on their positions, stand for the name of a signal or the logical sta-
tus of that signal. The following is a list of all the characters and what they stand for.
Example:T
AVLL
= Time for Address Valid to ALE Low.
T
LLPL
= Time for ALE Low to PSEN Low.
T
A
= 0 to +70°C (commercial temperature range); V
SS
= 0 V; V
CC
= 5 V ± 10%; -M and -V ranges.
T
A
= -40°C to +85°C (industrial temperature range); V
SS
= 0 V; V
CC
= 5 V ± 10%; -M and -V
ranges.
T
A
= 0 to +70°C (commercial temperature range); V
SS
= 0 V; 2.7 V < V
CC <
5.5 V; -L range.
T
A
= -40°C to +85°C (industrial temperature range); V
SS
= 0 V; 2.7 V < V
CC <
5.5 V; -L range.
Table 14-3. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE
and PSEN signals. Timings will be guaranteed if these capacitances are respected. Higher
capacitance values can be used, but timings will then be degraded.
Table 14-3. Load Capacitance versus speed range, in pF
Table 8-5., Table 8-8. and Table 8-11. give the description of each AC symbols.
Table 14-6., Table 14-9. and Table 14-12. give for each range the AC parameter.
-M -V -L
Port 0 100 50 100
Port 1, 2, 3 80 50 80
ALE / PSEN 100 30 100
41m
31
4428E–8051–02/08
AT/TS80C31X2
Table 14-7., Table 14-10. and Table 14-13. give the frequency derating formula of the AC
parameter. To calculate each AC symbols, take the x value corresponding to the speed grade
you need (-M, -V or -L) and replace this value in the formula. Values of the frequency must be
limited to the corresponding speed grade:
Table 14-4. Max frequency for derating formula regarding the speed grade
Example:
T
LLIV
in X2 mode for a -V part at 20 MHz (T = 1/20
E6
= 50 ns):
x= 25 (Table 14-7.)
T= 50ns
T
LLIV
= 2T - x = 2 x 50 - 25 = 75ns
Table 14-5. External Program Memory Characteristics
-M X1 mode -M X2 mode -V X1 mode -V X2 mode -L X1 mode -L X2 mode
Freq (MHz) 40 20 40 30 30 20
T (ns) 25 50 25 33.3 33.3 50
Symbol Parameter
T Oscillator clock period
T
LHLL
ALE pulse width
T
AVLL
Address Valid to ALE
T
LLAX
Address Hold After ALE
T
LLIV
ALE to Valid Instruction In
T
LLPL
ALE to PSEN
T
PLPH
PSEN Pulse Width
T
PLIV
PSEN to Valid Instruction In
T
PXIX
Input Instruction Hold After PSEN
T
PXIZ
Input Instruction FloatAfter PSEN
T
PXAV
PSEN to Address Valid
T
AVIV
Address to Valid Instruction In
T
PLAZ
PSEN Low to Address Float
41m
32
4428E–8051–02/08
AT/TS80C31X2
Table 14-6. AC Parameters for Fix Clock
Table 14-7. AC Parameters for a Variable Clock: derating formula
Speed
-M
40 MHz
-V
X2 mode
30 MHz
60 MHz equiv.
-V
standard mode 40
MHz
-L
X2 mode
20 MHz
40 MHz equiv.
-L
standard mode
30 MHz
Units
Symbol Min Max Min Max Min Max Min Max Min Max
T 25 33 25 50 33 ns
T
LHLL
40 25 42 35 52 ns
T
AVLL
10 4 12 5 13 ns
T
LLAX
10 4 12 5 13 ns
T
LLIV
70 45 78 65 98 ns
T
LLPL
15 9 17 10 18 ns
T
PLPH
55 35 60 50 75 ns
T
PLIV
35 25 50 30 55 ns
T
PXIX
0 0 0 0 0 ns
T
PXIZ
18 12 20 10 18 ns
T
AVIV
85 53 95 80 122 ns
T
PLAZ
10 10 10 10 10 ns
Symbol Type
Standard
Clock X2 Clock -M -V -L Units
T
LHLL
Min 2 T - x T - x 10 8 15 ns
T
AVLL
Min T - x 0.5 T - x 15 13 20 ns
T
LLAX
Min T - x 0.5 T - x 15 13 20 ns
T
LLIV
Max 4 T - x 2 T - x 30 22 35 ns
T
LLPL
Min T - x 0.5 T - x 10 8 15 ns
T
PLPH
Min 3 T - x 1.5 T - x 20 15 25 ns
T
PLIV
Max 3 T - x 1.5 T - x 40 25 45 ns
T
PXIX
Min x x 0 0 0 ns
T
PXIZ
Max T - x 0.5 T - x 7 5 15 ns
T
AVIV
Max 5 T - x 2.5 T - x 40 30 45 ns
T
PLAZ
Max x x 10 10 10 ns
41m
33
4428E–8051–02/08
AT/TS80C31X2
14.5.2 External Program Memory Read Cycle
Figure 14-6. External Program Memory Read Cycle
Table 14-8. External Data Memory Characteristics
Symbol Parameter
T
RLRH
RD Pulse Width
T
WLWH
WR Pulse Width
T
RLDV
RD to Valid Data In
T
RHDX
Data Hold After RD
T
RHDZ
Data Float After RD
T
LLDV
ALE to Valid Data In
T
AVDV
Address to Valid Data In
T
LLWL
ALE to WR or RD
T
AVWL
Address to WR or RD
T
QVWX
Data Valid to WR Transition
T
QVWH
Data set-up to WR High
T
WHQX
Data Hold After WR
T
RLAZ
RD Low to Address Float
T
WHLH
RD or WR High to ALE high
41m
34
4428E–8051–02/08
AT/TS80C31X2
Table 14-9. AC Parameters for a Fix Clock
Speed -M
40 MHz
-V
X2 mode
30 MHz
60 MHz equiv.
-V
standard mode 40
MHz
-L
X2 mode
20 MHz
40 MHz equiv.
-L
standard mode
30 MHz Units
Symbol Min Max Min Max Min Max Min Max Min Max
T
RLRH
130 85 135 125 175 ns
T
WLWH
130 85 135 125 175 ns
T
RLDV
100 60 102 95 137 ns
T
RHDX
0 0 0 0 0 ns
T
RHDZ
30 18 35 25 42 ns
T
LLDV
160 98 165 155 222 ns
T
AVDV
165 100 175 160 235 ns
T
LLWL
50 100 30 70 55 95 45 105 70 130 ns
T
AVWL
75 47 80 70 103 ns
T
QVWX
10 7 15 5 13 ns
T
QVWH
160 107 165 155 213 ns
T
WHQX
15 9 17 10 18 ns
T
RLAZ
0 0 0 0 0 ns
T
WHLH
10 40 7 27 15 35 5 45 13 53 ns
41m
35
4428E–8051–02/08
AT/TS80C31X2
Table 14-10. AC Parameters for a Variable Clock: derating formula
14.5.3 External Data Memory Write Cycle
Figure 14-7. External Data Memory Write Cycle
Symbol Type
Standard
Clock X2 Clock -M -V -L Units
T
RLRH
Min 6 T - x 3 T - x 20 15 25 ns
T
WLWH
Min 6 T - x 3 T - x 20 15 25 ns
T
RLDV
Max 5 T - x 2.5 T - x 25 23 30 ns
T
RHDX
Min x x 0 0 0 ns
T
RHDZ
Max 2 T - x T - x 20 15 25 ns
T
LLDV
Max 8 T - x 4T -x 40 35 45 ns
T
AVDV
Max 9 T - x 4.5 T - x 60 50 65 ns
T
LLWL
Min 3 T - x 1.5 T - x 25 20 30 ns
T
LLWL
Max 3 T + x 1.5 T + x 25 20 30 ns
T
AVWL
Min 4 T - x 2 T - x 25 20 30 ns
T
QVWX
Min T - x 0.5 T - x 15 10 20 ns
T
QVWH
Min 7 T - x 3.5 T - x 15 10 20 ns
T
WHQX
Min T - x 0.5 T - x 10 8 15 ns
T
RLAZ
Max x x 0 0 0 ns
T
WHLH
Min T - x 0.5 T - x 15 10 20 ns
T
WHLH
Max T + x 0.5 T + x 15 10 20 ns
41m
36
4428E–8051–02/08
AT/TS80C31X2
14.5.4 External Data Memory Read Cycle
Figure 14-8. External Data Memory Read Cycle
Table 14-11. Serial Port Timing - Shift Register Mode
Table 14-12. AC Parameters for a Fix Clock
Symbol Parameter
T
XLXL
Serial port clock cycle time
T
QVHX
Output data set-up to clock rising edge
T
XHQX
Output data hold after clock rising edge
T
XHDX
Input data hold after clock rising edge
T
XHDV
Clock rising edge to input data valid
Speed
-M
40 MHz
-V
X2 mode
30 MHz
60 MHz equiv.
-V
standard mode 40
MHz
-L
X2 mode
20 MHz
40 MHz equiv.
-L
standard mode
30 MHz Units
Symbol Min Max Min Max Min Max Min Max Min Max
T
XLXL
300 200 300 300 400 ns
T
QVHX
200 117 200 200 283 ns
T
XHQX
30 13 30 30 47 ns
T
XHDX
0 0 0 0 0 ns
T
XHDV
117 34 117 117 200 ns
+ + % ’4” X a . + QDQDQDQIDDOQDDD ;fi:>ooaoumm
37
4428E–8051–02/08
AT/TS80C31X2
Table 14-13. AC Parameters for a Variable Clock: derating formula
14.5.5 Shift Register Timing Waveforms
Figure 14-9. Shift Register Timing Waveforms
Table 14-14. External Clock Drive Characteristics (XTAL1)
Symbol Type
Standard
Clock X2 Clock -M -V -L Units
T
XLXL
Min 12 T 6 T ns
T
QVHX
Min 10 T - x 5 T - x 50 50 50 ns
T
XHQX
Min 2 T - x T - x 20 20 20 ns
T
XHDX
Min x x 0 0 0 ns
T
XHDV
Max 10 T - x 5 T- x 133 133 133 ns
Symbol Parameter Min Max Units
T
CLCL
Oscillator Period 25 ns
T
CHCX
High Time 5 ns
T
CLCX
Low Time 5 ns
T
CLCH
Rise Time 5 ns
T
CHCL
Fall Time 5 ns
T
CHCX
/T
CLCX
Cyclic ratio in X2 mode 40 60 %
38
4428E–8051–02/08
AT/TS80C31X2
14.5.6 External Clock Drive Waveforms
Figure 14-10. External Clock Drive Waveforms
14.5.7 AC Testing Input/Output Waveforms
Figure 14-11. AC Testing Input/Output Waveforms
AC inputs during testing are driven at V
CC
- 0.5 for a logic “1” and 0.45V for a logic “0”. Timing
measurement are made at V
IH
min for a logic “1” and V
IL
max for a logic “0”.
14.5.8 Float Waveforms
Figure 14-12. Float Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded V
OH
/V
OL
level occurs. I
OL
/I
OH
≥ ± 20mA.
14.5.9 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by
two.
V
CC
-0.5
V
0.45
V
0.7V
CC
0.2V
CC
-0.1
V
T
CHCL
T
CLCX
T
CLCL
T
CLCH
T
CHCX
39
4428E–8051–02/08
AT/TS80C31X2
Figure 14-13. Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to prop-
agate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on
variables such as temperature and pin loading. Propagation also varies from output to output
and component. Typically though (T
A
=25°C fully loaded) RD and WR propagation delays are
approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated
in the AC specifications.
41m
40
4428E–8051–02/08
AT/TS80C31X2
15. Ordering Information
Part Number
(3)
Memory Size Supply Voltage
Temperature
Range Max Frequency Package Packing
TS80C31X2-MCA
OBSOLETE
TS80C31X2-MCB
TS80C31X2-MCC
TS80C31X2-MCE
TS80C31X2-LCA
TS80C31X2-LCB
TS80C31X2-LCC
TS80C31X2-LCE
TS80C31X2-VCA
TS80C31X2-VCB
TS80C31X2-VCC
TS80C31X2-VCE
TS80C31X2-MIA
TS80C31X2-MIB
TS80C31X2-MIC
TS80C31X2-MIE
TS80C31X2-LIA
TS80C31X2-LIB
TS80C31X2-LIC
TS80C31X2-LIE
TS80C31X2-VIA
TS80C31X2-VIB
TS80C31X2-VIC
TS80C31X2-VIE
AT80C31X2-3CSUM ROMLess 5V ±10% Industrial & Green 40 MHz
(1)
PDIL40 Stick
AT80C31X2-SLSUM ROMLess 5V ±10% Industrial & Green 40 MHz
(1)
PLCC44 Stick
AT80C31X2-RLTUM ROMLess 5V ±10% Industrial & Green 40 MHz
(1)
VQFP44 Tray
AT80C31X2-3CSUL ROMLess 2.7 to 5.5V Industrial & Green 30 MHz
(1)
PDIL40 Stick
AT80C31X2-SLSUL ROMLess 2.7 to 5.5V Industrial & Green 30 MHz
(1)
PLCC44 Stick
AT80C31X2-RLTUL ROMLess 2.7 to 5.5V Industrial & Green 30 MHz
(1)
VQFP44 Tray
41m
41
4428E–8051–02/08
AT/TS80C31X2
Notes: 1. 20 MHz in X2 Mode.
2. Tape and Reel available for SL, PQFP and RL packages.
3. 30 MHz in X2 Mode.
AT80C31X2-3CSUV ROMLess 5V ±10% Industrial & Green 60 MHz
(3)
PDIL40 Stick
AT80C31X2-SLSUV ROMLess 5V ±10% Industrial & Green 60 MHz
(3)
PLCC44 Stick
AT80C31X2-RLTUV ROMLess 5V ±10% Industrial & Green 60 MHz
(3)
VQFP44 Tray
Part Number
(3)
Memory Size Supply Voltage
Temperature
Range Max Frequency Package Packing
41m
Printed on recycled paper.
4428E–8051–02/08
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