CDB4365 Datasheet by Cirrus Logic Inc.

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Evaluation Board for CS4365
Features
Demonstrates recommended layout and
grounding arrangements
CS8416 receives S/PDIF, & EIAJ-340
compatible digital audio
Headers for external audio input for either PCM
or DSD®
Requires only a digital signal source and power
supplies for a complete Digital-to-analog
converter system
Description
The CDB4365 evaluation board is an excellent means
for quickly evaluating the CS4365 24-bit, 48-pin, 6-
channel D/A converter. Evaluation requires an analog
signal analyzer, a digital signal source, a PC for control-
ling the CS4365 (only required for control port mode),
and a power supply. Analog line-level outputs are pro-
vided via RCA phono jacks.
The CS8416 digital audio receiver IC provides the sys-
tem timing necessary to operate the digital-to-analog
converter and will accept S/PDIF and EIAJ-340-com-
patible audio data. The evaluation board may also be
configured to accept external timing and data signals for
operation in a user application during system
development.
ORDERING INFORMATION
CDB4365 Evaluation Board
CS4365 Analog Outputs
and Filtering
Inputs for PCM
Clocks and Data
CS8416
Digital Audio
Interface
Hardware or
Software Board
Control
Inputs for DSD
Clocks and Data
MAY '08
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CDB4365
CIRRUS LOGIC” é:
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TABLE OF CONTENTS
1. CS4365 DIGITAL-TO-ANALOG CONVERTER ..................................................................................... 4
2. CS8416 DIGITAL AUDIO RECEIVER .................................................................................................... 4
3. INPUT FOR CLOCKS AND DATA ......................................................................................................... 4
4. INPUT FOR CONTROL DATA ............................................................................................................... 4
5. POWER SUPPLY CIRCUITRY ............................................................................................................... 5
6. GROUNDING AND POWER SUPPLY DECOUPLING .......................................................................... 5
7. ANALOG OUTPUT FILTERING ............................................................................................................. 5
8. PERFORMANCE PLOTS ....................................................................................................................... 7
9. CDB4365 SCHEMATICS ..................................................................................................................... 17
10. REVISION HISTORY ......................................................................................................................... 30
LIST OF FIGURES
Figure 1.FFT (48 kHz, 0 dB) ....................................................................................................................... 7
Figure 2.FFT (48 kHz, -60 dB) .................................................................................................................... 7
Figure 3.FFT (48 kHz, No Input) ................................................................................................................. 7
Figure 4.FFT (48 kHz Out-of-Band, No Input) ............................................................................................. 7
Figure 5.FFT (48 kHz, -60 dB Wideband) ................................................................................................... 8
Figure 6.FFT (IMD 48 kHz) ......................................................................................................................... 8
Figure 7.48 kHz, THD+N vs. Input Freq ...................................................................................................... 8
Figure 8.48 kHz, THD+N vs. Level ............................................................................................................. 8
Figure 9.48 kHz, Fade-to-Noise Linearity ................................................................................................... 8
Figure 10.48 kHz, Frequency Response ..................................................................................................... 8
Figure 11.48 kHz, Crosstalk ........................................................................................................................ 9
Figure 12.48 kHz, Impulse Response ......................................................................................................... 9
Figure 13.48 kHz, Impulse Prefilter ............................................................................................................. 9
Figure 14.48 kHz Dynamic Range ............................................................................................................ 10
Figure 15.FFT (96 kHz, 0 dB) ................................................................................................................... 10
Figure 16.FFT (96 kHz, -60 dB) ................................................................................................................ 10
Figure 17.FFT (96 kHz, No Input) ............................................................................................................. 11
Figure 18.FFT (96 kHz Out-of-Band, No Input) ......................................................................................... 11
Figure 19.FFT (96 kHz, -60 db Wideband) ............................................................................................... 11
Figure 20.FFT (IMD 96 kHz) ..................................................................................................................... 11
Figure 21.96 kHz, THD+N vs. Input Freq .................................................................................................. 11
Figure 22.96 kHz, THD+N vs. Level ......................................................................................................... 11
Figure 23.96 kHz, Fade-to-Noise Linearity ............................................................................................... 12
Figure 24.96 kHz, Frequency Response ................................................................................................... 12
Figure 25.96 kHz, Crosstalk ...................................................................................................................... 12
Figure 26.96 kHz, Impulse Response ....................................................................................................... 12
Figure 27.96 kHz, Impulse Prefilter ........................................................................................................... 12
Figure 28.Dynamic Range 96 kHz ............................................................................................................ 13
Figure 29.FFT (192 kHz, 0 dB) ................................................................................................................. 13
Figure 30.FFT (192 kHz, -60 dB) .............................................................................................................. 13
Figure 31.FFT (192 kHz, No Input) ........................................................................................................... 14
Figure 32.FFT (192 kHz Out-of-Band, No Input) ....................................................................................... 14
Figure 33.FFT (192 kHz, -60 dB Wideband) ............................................................................................. 14
Figure 34.FFT (IMD 192 kHz) ................................................................................................................... 14
Figure 35.192 kHz, THD+N vs. Input Freq ................................................................................................ 14
Figure 36.192 kHz, THD+N vs. Level ....................................................................................................... 14
Figure 37.192 kHz, Fade-to-Noise Linearity ............................................................................................. 15
Figure 38.192 kHz, Frequency Response ................................................................................................. 15
Figure 39.192 kHz, Crosstalk .................................................................................................................... 15
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Figure 40.192 kHz, Impulse Response ..................................................................................................... 15
Figure 41.192 kHz, Impulse Prefilter ......................................................................................................... 15
Figure 42.Dynamic Range 192 kHz .......................................................................................................... 16
Figure 43.System Block Diagram and SIgnal Flow ................................................................................... 17
Figure 44.CS4365 ..................................................................................................................................... 18
Figure 45.Analog Outputs A1 - B1 ............................................................................................................ 19
Figure 46.Analog Outputs A2 - B2 ............................................................................................................ 20
Figure 47.Analog Outputs A3 - B3 ............................................................................................................ 21
Figure 48.CS8416 S/PDIF Input ............................................................................................................... 22
Figure 49.PCM Input Header and Muxing ................................................................................................. 23
Figure 50.DSD Input Header ..................................................................................................................... 24
Figure 51.Control Input ............................................................................................................................. 25
Figure 52.Power Inputs ............................................................................................................................. 26
Figure 53.Silkscreen Top .......................................................................................................................... 27
Figure 54.Top Side .................................................................................................................................... 28
Figure 55.Bottom Side .............................................................................................................................. 29
LIST OF TABLES
Table 1. System Connections .................................................................................................................... 5
Table 2. CDB4365 Jumper Settings ............................................................................................................ 6
CIRRUS LOGIC” é:
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CDB4365 SYSTEM OVERVIEW
The CDB4365 evaluation board is an excellent means of quickly evaluating the CS4365. The CS8416 digital audio
interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test
equipment. The evaluation board also allows the user to supply external PCM or DSD clocks and data through PCB
headers for system development.
The CDB4365 uses the CDB4385 as a base PCB board. For this reason, there may be additional circuitry on board
which is not populated as it has no function for this device.
The CDB4365 schematic has been partitioned into 9 schematics shown in Figure 44 through 52. Each partitioned
schematic is represented in the system diagram shown in Figure Figure 43 on page 17. Notice that the system dia-
gram also includes the interconnections between the partitioned schematics.
1. CS4365 DIGITAL-TO-ANALOG CONVERTER
A description of the CS4365 is included in the CS4365 datasheet.
2. CS8416 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8416 digital audio receiver
(Figure 48). The outputs of the CS8416 include a serial bit clock, serial data, left-right clock, and a 128/256 Fs mas-
ter clock. The CS8416 data format is fixed to I²S. The operation of the CS8416 and a discussion of the digital audio
interface are included in the CS8416 datasheet.
The evaluation board has been designed such that the input can be either optical or coaxial (See Figure 48). How-
ever, both inputs cannot be driven simultaneously.
Switch position 7 of S1 sets the output MCLK-to-LRCK ratio of the CS8416. This switch should be set to 256 (closed)
for inputs Fs≤96 kHz and 128 (open) for Fs≥64 kHz. The 8416 must be manually reset using ‘HW RST’ (S2) or
through the software when this switch is changed.
3. INPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via headers J11 and J7. Header
J11 allows the evaluation board to accept externally generated PCM clocks and data. The schematic for the
clock/data input is shown in Figure 49. Switch position 6 of S1 selects the source as either CS8416 (open) or header
J11 (closed).
Header J7 allows the evaluation board to accept externally generated DSD data and clocks. The schematic for the
clock/data input is shown in Figure 50. A synchronous MCLK must still be provided via Header J11. Switch position
8 of S1 selects either PCM (open) or DSD (closed).
Please see the CS4365 datasheet for more information.
4. INPUT FOR CONTROL DATA
The evaluation board can be run in either a stand-alone mode or with a PC. Stand-alone mode uses the CS4365 in
hardware mode and the mode pins are configured using switch positions 1 through 5 of S1. PC mode uses software
to setup the CS4365 through I²C® using the PC’s serial or USB ports. PC mode is automatically selected when the
serial or USB port is attached and the CDB4365 software is running.
Header J15 offers the option for external input of RST and SPI™/I²C clocks and data. The board is setup from the
factory to use the on-board microcontroller in conjunction with the supplied software. To use an external control
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source, remove the shunts on J15 and place a ribbon cable so the signal lines are on the center row and the grounds
are on the right side. R116 and R119 should be populated with 2-kΩ resistors when using an external I²C source
that does not already provide pull-ups.
5. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by four binding posts: GND, +5V, +12V, and -12V (See Figure 52). The
‘+5V’ terminal supplies VA and the rest of the +5-V circuitry on the board. The +3.3-V circuitry is powered from a
regulator. The +2.5 volts required for VD is also provided from an on-board regulator. The +5-V supply should be
set within the recommended values for VA stated in the CS4365 datasheet.
WARNING: Refer to the CS4365 datasheet for maximum allowable voltage levels. Operation outside this range can
cause permanent damage to the device.
6. GROUNDING AND POWER SUPPLY DECOUPLING
As with any high-performance converter, the CS4365 requires careful attention to power supply and grounding ar-
rangements to optimize performance. Figure 44 details the connections to the CS4365 and Figures 53, 54, and 55
show the component placement and top and bottom layout. The decoupling capacitors are located as close to the
CS4365 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated
noise.
7. ANALOG OUTPUT FILTERING
The analog output on the CDB4365 has been designed according to the CS4365 datasheet. This output circuit in-
cludes an active 2-pole, 50-kHz filter which uses the multiple-feedback topology.
Table 1. System Connections
CONNECTOR INPUT/OUTPUT SIGNAL PRESENT
+5V Input + 5 V power
GND Input Ground connection from power supply
+12V Input +12 V positive supply for the on-board filtering
-12V Input -12 V negative supply for the on-board filtering
S/PDIF IN - J9 Input Digital audio interface input via coax
S/PDIF IN - OPT1 Input Digital audio interface input via optical
PCM INPUT - J11 Input Input for master, serial, left/right clocks and serial data
DSD INPUT - J7 Input Input for DSD serial clock and DSD data
OUTA1-B3 Output RCA line level analog outputs
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Table 2. CDB4365 Jumper Settings
JUMPER /
SWITCH PURPOSE POSITION FUNCTION SELECTED
J15 Selects source of control data *shunts on Left
shunts removed *Control from PC and on-board microcontroller
External control input using center and right columns
J16 JTAG micro programming - Reserved for factory use only
S2 Resets CS8416 and CS4365 The CS8416 must be reset if switch S1 is changed
S1
CS4365 mode settings M0-M4 1-5 Default: M0, M4 open (HI)
M1, M2, M3 closed (LO)
Sets clock source 6 Sets clock source for CS4365
*open = RX(CS8416), closed = EXT(J11)
Sets MCLK ratio of CS8416 7 Selects 128x (open) or 256x (*closed) MCLK/LRCK ratio
output for CS8416
Selects PCM or DSD mode 8 For PCM input set to *Open, for DSD set to Closed
*Default Factory Settings
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8. PERFORMANCE PLOTS
The plots in the following section were acheived using an Audio Precision System 2700 and a randomly chosen pro-
duction CDB4365. In some cases the performance may be limited by the CDB4365. All measurements were taken
at room temp using the standard AP filter options (20 Hz to 22 kHz) with default board settings and nominal
datasheet voltages applied unless otherwise noted.
The impulse response plots were taken both pre-and post filtering as the off-chip filter was degrading the perfor-
mance at higher sample rates. The pre-filter impulse response plots were taken directly at the output pins of the
DAC (with the analog filter still connected) to show the effect of the CDB’s analog filtering on the impulse response
(as the analog filtering adds its own signature to the impulse response of the DAC, and in the case of the higher
sampling rates it was band-limiting it).
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Figure 1. FFT (48 kHz, 0 dB) Figure 2. FFT (48 kHz, -60 dB)
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Figure 3. FFT (48 kHz, No Input) Figure 4. FFT (48 kHz Out-of-Band, No Input)
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Figure 5. FFT (48 kHz, -60 dB Wideband) Figure 6. FFT (IMD 48 kHz)
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Figure 7. 48 kHz, THD+N vs. Input Freq Figure 8. 48 kHz, THD+N vs. Level
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Figure 9. 48 kHz, Fade-to-Noise Linearity Figure 10. 48 kHz, Frequency Response
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Figure 11. 48 kHz, Crosstalk Figure 12. 48 kHz, Impulse Response
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Figure 13. 48 kHz, Impulse Prefilter
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Figure 14. 48 kHz Dynamic Range
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Figure 15. FFT (96 kHz, 0 dB) Figure 16. FFT (96 kHz, -60 dB)
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Figure 17. FFT (96 kHz, No Input) Figure 18. FFT (96 kHz Out-of-Band, No Input)
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Figure 19. FFT (96 kHz, -60 db Wideband) Figure 20. FFT (IMD 96 kHz)
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Figure 21. 96 kHz, THD+N vs. Input Freq Figure 22. 96 kHz, THD+N vs. Level
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Figure 23. 96 kHz, Fade-to-Noise Linearity Figure 24. 96 kHz, Frequency Response
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Figure 25. 96 kHz, Crosstalk Figure 26. 96 kHz, Impulse Response
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Figure 27. 96 kHz, Impulse Prefilter
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Figure 28. Dynamic Range 96 kHz
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Figure 29. FFT (192 kHz, 0 dB) Figure 30. FFT (192 kHz, -60 dB)
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Figure 31. FFT (192 kHz, No Input) Figure 32. FFT (192 kHz Out-of-Band, No Input)
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Figure 33. FFT (192 kHz, -60 dB Wideband) Figure 34. FFT (IMD 192 kHz)
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Figure 35. 192 kHz, THD+N vs. Input Freq Figure 36. 192 kHz, THD+N vs. Level
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Figure 37. 192 kHz, Fade-to-Noise Linearity Figure 38. 192 kHz, Frequency Response
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-500m
0
500m
1
1.5
2
2.5
V
0600u200u 400u
sec
Figure 39. 192 kHz, Crosstalk Figure 40. 192 kHz, Impulse Response
-3
3
-2.5
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
V
0600u200u 400u
sec
Figure 41. 192 kHz, Impulse Prefilter
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16 DS670DB3
CDB4365
Figure 42. Dynamic Range 192 kHz
SEGOLSSG 9. CDB4365 SCHEMATICS POM HEADER pm cwunxsum (388416 SIPDIF Input pm cwunxsum Serial Control Port PCM cm; Dara T I’C/SPl Header /—$fi CS4365 I 01907 SHHMD m»
DS670DB3 17
CDB4365
9. CDB4365 SCHEMATICS
CS4365
CS8416
S/PDIF
Input
Serial Control Port
PCM mux
PCM Clocks/Data
PCM Clocks/Data
I2C/SPI Header
Power
DSD Clocks/
Dat
a
DSD HEADER
2
2
DSD clk_enable
PCM Clocks/Data
DSD input
enable
M0
- M4
switche
s
( for
stand -alone
mode )
PCM source
select
C
S841
6 clock setting
Hardware Control
Switches
PCM HEADER
2
A1, B1
A2, B2
A3, B3
Differential to Single-Ended
Analog Outputs
Figure 52 on page 26
Figure 45 on page 19
Figure 46 on page 20
Figure 47 on page 21
Figure 51 on page 25 Figure 50 on page 24
Figure 49 on
page 23
Figure 48 on
page 22
Figure 49 on
page 23
Figure 51 on page 25
Figure 43. System Block Diagram and SIgnal Flow
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18 DS670DB3
CDB4365
Figure 44. CS4365
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DS670DB3 19
CDB4365
Figure 45. Analog Outputs A1 - B1
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20 DS670DB3
CDB4365
Figure 46. Analog Outputs A2 - B2
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DS670DB3 21
CDB4365
Figure 47. Analog Outputs A3 - B3
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22 DS670DB3
CDB4365
Figure 48. CS8416 S/PDIF Input
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DS670DB3 23
CDB4365
Figure 49. PCM Input Header and Muxing
[u] D5D_SCLK DSDBA DSDAO DSDB} USDA} DSDBZ DSDAZ DSDBV DSDAI GND DSDJN GND v 4 NC7SZVZSM5X Al A2 A} A4 A5 A6 A7 GND +3.3v cm X7R 0va GM) us T/R vg A0 DE END BO DSDB‘ [7] 31 DSDA4 [7] Hz 0503} [7] B} DSDA3 [7] 54 DSDBZ [7] 55 DSDAZ [71 55 B7 050m [7] DSDM [7] 74VHC245MTC DSD_SCLK [7] 0190'! 511212113 11
24 DS670DB3
CDB4365
Figure 50. DSD Input Header
,, m , 9?, MLE’EWJ‘STE‘S' hm
DS670DB3 25
CDB4365
Figure 51. Control Input
M D ; w W i #2:, m ran IESY oxouuns —— ——— —— —— “31907 STIHMD -
26 DS670DB3
CDB4365
Figure 52. Power Inputs
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DS670DB3 27
CDB4365
Figure 53. Silkscreen Top
—— QIDO’I SHERID _—
28 DS670DB3
CDB4365
Figure 54. Top Side
mm»
DS670DB3 29
CDB4365
Figure 55. Bottom Side
__. :CIRRUS LOGIC “
30 DS670DB3
CDB4365
10.REVISION HISTORY
Release Changes
DB1 Initial Release
DB2 Added Performance Plots
DB3 Added USB support to Section 4. Input for Control Data
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
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does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-
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CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO
FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD-
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
DSD is a registered trademark of Sony Kabushiki Kaisha TA Sony Company.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.

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EVALUATION BOARD FOR CS4365