PIC18F6627/6722/8627/8722 Rev.B1 Errata Datasheet by Microchip Technology

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Q ‘MICROCHIP P|C18F6627/6722/8627/8722 Work around Date Codes that pertain to this issue: Work around Date Codes that pertain to this issue: Work around Date Codes that pertain to this issue:
© 2009 Microchip Technology Inc. DS80343B-page 1
PIC18F6627/6722/8627/8722
The PIC18F6627/6722/8627/8722 Rev. B1 parts you
have received conform functionally to the Device Data
Sheet (DS39646C), except for the anomalies
described below. Any Data Sheet Clarification issues
related to the PIC18F6627/6722/8627/8722 will be
reported in a separate Data Sheet errata. Please check
the Microchip web site for any existing issues.
The following silicon errata apply only to
PIC18F6627/6722/8627/8722 devices with these
Device/Revision IDs:
All of the issues listed here will be addressed in future
revisions of the PIC18F6627/6722/8627/8722 silicon.
1. Module: Master Synchronous Serial Port
(MSSP) — Serial Peripheral
Interface (SPI)
In SPI mode, the Buffer Full flag (BF bit in the
SSPxSTAT register), the Write Collision Detect bit
(WCOL in SSPxCON1) and the Receive Overflow
Indicator bit (SSPOV in SSPxCON1) are not reset
upon disabling the SPI module (by clearing the
SSPEN bit in the SSPxCON1 register).
For example, if SSPxBUF is full (BF bit is set), and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPxBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.
Work around
Ensure that if the buffer is full, SSPxBUF is read
(thus clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the module
is configured in SPI Slave mode, ensure that the
SSPOV bit is clear before disabling the module.
Date Codes that pertain to this issue:
All engineering and production devices.
2. Module: Capture/Compare/PWM (CCP)
PWM output of 10-bit resolution is not available for
either CCP4 or CCP5 when Timer4 is being used
as the PWM time base (T3CON<6,3> = 01, 10 or
11) for the PWM mode (CCPxCON<3:2> = 11).
Work around
For 10-bit resolution, use Timer2 as the PWM time
base (T3CON<6,3> = 00).
For 8-bit resolution, use Timer4 or Timer2 as the
PWM time base and set the two LSBs to ‘00
(CCPxCON<5:4> = 00).
Date Codes that pertain to this issue:
All engineering and production devices.
3. Module: MSSP (I2C™ Slave)
In extremely rare cases, when configured for I2C™
slave reception, the MSSP module may not receive
the correct data. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPxBUF) is not
read within a window after the SSPxIF interrupt has
occurred.
For SSP1BUF, the flag bit is SSP1IF (PIR1<3>).
For SSP2BUF, the flag bit is SSP2IF (PIR3<7>).
Work around
The issue can be resolved in either of these ways:
Prior to the I2C slave reception, enable the
clock-stretching feature.
This is done by setting the SEN bit
(SSP1CON2<0>).
Each time the SSPxIF bit is set, read the
SSPxBUF before the first rising clock edge of
the next byte being received.
Date Codes that pertain to this issue:
All engineering and production devices.
Part Number Device ID Revision ID
PIC18F6627 0001 0011 110 0 0010
PIC18F6722 0001 0100 000 0 0010
PIC18F8627 0001 0011 111 0 0010
PIC18F8722 0001 0100 001 0 0010
The Device IDs (DEVID1 and DEVID2) are located at
addresses 3FFFFEh:3FFFFFh in the device’s
configuration space. They are shown in binary in the
format “DEVID2 DEVID1”.
PIC18F6627/6722/8627/8722 Rev. B1 Silicon Errata
Work around Work around Dale Codes that per to ! su Work around Dale Codes that per to ! sue:
PIC18F6627/6722/8627/8722
DS80343B-page 2 © 2009 Microchip Technology Inc.
4. Module: MSSP (I2C™ Master)
If the module is in I2C Master mode and the slave
performs clock stretching, the first clock pulse after
the slave releases the SCL line may be narrower
than the configured clock width. This may result in
the slave missing the first clock in the next
transmission/reception.
Work around
If the module is in I2C Master mode, do not have
the slave perform clock stretching. Alternately, the
master can slow down the SCL clock frequency to
a level where the slave can detect the narrowed
clock pulse.
Date Codes that pertain to this issue:
All engineering and production devices.
5. Module: Enhanced Universal
Synchronous Asynchronous
(EUSART)
In rare situations when interrupts are enabled,
unexpected results may occur if:
The EUSART is disabled (the SPEN
(RCSTAx <7>) bit = 0)
The EUSART is re-enabled (RCSTAx <7> = 1)
A two-cycle instruction is executed
Work around
Add a 2-TCY delay after re-enabling the EUSART.
1. Disable the receive interrupts:
For RCSTA1 – RC1IE bit (PIE1<5>) = 0
For RCSTA2 – RC2IE bit (PIE3<5>) = 0
2. Disable the EUSART:
For RCSTA1 – SPEN bit (RCSTA1<7>) = 0
For RCSTA2 – SPEN bit (RCSTA2<7>) = 0
3. Re-enable the EUSART (RCSTAx <7> = 1).
(See step 1.)
4. Re-enable the receive interrupts:
For RCSTA1 – RC1IE bit (PIE1<5>) = 1
For RCSTA2 – RC2IE bit (PIE3<5>) = 1
(This is the first TCY delay.)
5. Execute a NOP instruction.
(This is the second TCY delay.)
Date Codes that pertain to this issue:
All engineering and production devices.
6. Module: Timer1
When Timer1 is running on the Timer1 oscillator, if
Sleep mode is executed immediately after loading
Timer 1 with 0xFFFF, the Timer1 interrupt will not
get set on the first overflow from 0xFFFF to
0x0000.
All subsequent overflows, from 0xFFFF to 0x0000,
will work correctly.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
Rev A Documenl 8/2007 Rev B Documenl 2/2009
© 2009 Microchip Technology Inc. DS80343B-page 3
PIC18F6627/6722/8627/8722
REVISION HISTORY
Rev A Document (8/2007)
Initial release of this errata. Includes silicon issues
1 (MSSP) and 2 (CCP).
Rev B Document (2/2009)
Added silicon issues 3 (MSSP – I2C Slave), 4 (MSSP –
I2C Master), 5 (Enhanced Universal Synchronous
Asynchronous – EUSART) and 6 (Timer1).
PIC18F6627/6722/8627/8722
DS80343B-page 4 © 2009 Microchip Technology Inc.
NOTES:
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949:2002 =
© 2009 Microchip Technology Inc. DS80343B-page 5
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Q ‘MICROCHIP
DS80343B-page 6 © 2009 Microchip Technology Inc.
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