TC835 Datasheet by Microchip Technology

Q ‘MICROCHIP TC835

TC835

Features

• Upgrade of Pin-Compatible TC7135, ICL7135

• 200 kHz Operation

• Single 5V Operation With TC7660

• Multiplexed BCD Data Output

• UART and Microprocessor Interface

• Control Outputs for Auto-Ranging

• Input Sensitivity: 100 µV

• No Sample and Hold Required

Applications

• Personal Computer Data Acquisition

• Scales, Panel Meters, Process Controls

• HP-IL Bus Instrumentation

General Description

The TC835 is a low power, 4-1/2 digit (0.005%

resolution), BCD analog-to-digital converter (ADC) that

has been characterized for 200 kHz clock rate

operation. The five conversions per second rate is

nearly twice as fast as the ICL7135 or TC7135. The

TC835, like the TC7135, does not use the external

diode resistor rollover error compensation circuits

required by the ICL7135.

The multiplexed BCD data output is perfect for interfac-

ing to personal computers. The low cost, greater than

14-bit high-resolution and 100 µV sensitivity makes the

TC835 exceptionally cost-effective.

Microprocessor-based data acquisition systems are

supported by the BUSY and STROBE outputs, along

with the RUN/HOLD input of the TC835. The

OVERRANGE, UNDERRANGE, BUSY and RUN/

HOLD control functions, plus multiplexed BCD data

outputs, make the TC835 the ideal converter for micro-

processor-based scales, measurement systems and

intelligent panel meters.

The TC835 interfaces with full function LCD and LED

display decoder/drivers. The UNDERRANGE and

OVERRANGE outputs may be used to implement an

auto-ranging scheme or special display functions.

Typical Application

Channel 1

Channel 2

Channel 3

Channel 4

Data Bus

Control

Address Bus

R 6522 P

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

CA1

CA2

PB0 PB3PB2PB1

Channel Selection

HCTS157 POL

STB

R/H

V+ REF CAP

BUF

INT

INPUT+

Input

Analog

Common

DGND

-5V

REF Voltage

+15V -15V

Differential

Multiplexer

DG529

A1A0EN

FIN

TC835

FIN

Personal Computer Data Acquisition A/D Converter

K c 5 3 a c T jEjjjjjjjjjjjj EEECCCCECECCCC ﬂmﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂﬂ Ejjjjjijjjjijj UUUUUUUUUUUUUUUU IDDDDDDDDEDDDDEE

TC835

Package Type

64-Pin MQFP

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

61 60 59 58 57 56 55 54 53 52 51 50 4964

TC835CBU

INT OUT

AZ IN

V+

+INPUT

BUFF OUT

BUF CAP–

SUB

BUF CAP+

–INPUT

DGND

POL

SUB

CLK IN

BUSY

OVERRANGE

UNDERRANGE

SUB

V–

REF IN

ANALOG COM

SUB

NC NC

STROBE

RUN/HOLD

TC835CPI

28-Pin PDIP

4RUN/HOLD

STROBE

OVERRANGE

D1 (LSD)

BUSY

CLOCK IN

POLARITY

DIGTAL GND

UNDERRANGE

(LSB) B1

(MSD) D5

V+

+INPUT

–INPUT

CREF+

CREF-

BUFF OUT

AZ IN

INT OUT

ANALOG

COM

REF IN

V-

B8 (MSD)

TC835CKW

12 13 14 15 17 18

44 43 42 41 39 3840

37 36 35 34

19 20 21 22

ANALOG

REF IN

V–

DGND

POLARITY

CLK IN

INT OUT

AZ IN

BUFF OUT

REF CAP–

–INPUT

+INPUT

V+

REF CAP+

(MSD) D5

(LSB) B1

(MSB) B8

D1 (LSD)

BUSY

RUN/HOLD

STROBE

44-Pin MQFP

COMMON

Note 1: NC = No internal connection.

2: Pins 9, 25, 40, and 56 are connected to the die substrate. The poteltial at these pins is approximately

V+. No external connections should be made.

TC835

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings†

Positive Supply Voltage.....................................................+6V

Negative Supply Voltage....................................................-9V

Analog Input Voltage (Pin 9 or 10) ..............V+ to V– (Note 2)

Reference Input Voltage (Pin 2)................................ V+ to V–

Clock Input Voltage....................................................0V to V+

Operating Temperature Range ..........................0°C to +70°C

Storage Temperature Range.........................-65°C to +150°C

Package Power Dissipation (TA ≤ 70°C)

28-Pin Plastic DIP ..................................................... 1.14Ω

44-Pin MQFP............................................................. 1.00Ω

64-Pin MQFP............................................................. 1.14Ω

† Stresses above those listed under "Absolute Maximum Rat-

ings" may cause permanent damage to the device. These are

stress ratings only and functional operation of the device at

these or any other conditions above those indicated in the

operation sections of the specifications is not implied. Expo-

sure to Absolute Maximum Rating conditions for extended

periods may affect device reliability.

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise specified, TA = +25°C, FCLOCK = 200 kHz, V+ = +5V, V- = -5V.

Parameter Sym Min Typ Max Unit Conditions

Analog

Display Reading with Zero Volt Input -0.0000 ±0.0000 +0.0000 Display

Reading Note 3, Note 4

Zero Reading Temperature Coefficient TCZ— 0.5 2 µV/°C VIN = 0V, (Note 5)

Full-Scale Temperature Coefficient TCFS — — 5 ppm/°C VIN = 2V;

(Note 5, Note 6

Nonlinearity Error NL — 0.5 1 Count Note 7

Differential Linearity Error DNL — 0.01 — LSB Note 7

Display Reading in Ratiometric Operation +0.9995 +0.9998 +1.0000 Display

Reading VIN = VREF, (Note 3)

± Full Scale Symmetry Error (Rollover Error) ±FSE — 0.5 1 Count –VIN = +VIN, (Note 8)

Input Leakage Current IIN — 1 10 pA Note 4

Noise eN—15 —μVP-P Peak-to-Peak Value not

Exceeded 95% of Time

Digital

Input Low Current IIL — 10 100 μAV

IN = 0V

Input High Current IIH —0.08 10 μAV

IN = +5V

Output Low Voltage VOL — 0.2 0.4 V IOL = 1.6 mA

Output High Voltage;

B1, B2, B4, B8, D1 –D5

Busy, Polarity, Overrange,

Underrange, Strobe

VOH 2.4 4.4 5 V IOH = 1 mA

4.9 4.99 5 V IOH = 10 µA

Clock Frequency fCLK 0 200 1200 kHz Note 10

Note 1: Functional operation is not implied.

2: Limit input current to under 100 µA if input voltages exceed supply voltage.

3: Full scale voltage = 2V.

4: VIN = 0V.

5: 0°C ≤ TA ≤ +70°C.

6: External reference temperature coefficient less than 0.01ppm/°C.

7: -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line.

8: |VIN| = 1.9959.

9: Test circuit shown in Figure 6-7.

10: Specification related to clock frequency range over which the TC835 correctly performs its various functions. Increased

errors result at higher operating frequencies.

TC835

Power Supply

Positive Supply Voltage V+ 4 5 6 V

Negative Supply Voltage V– -3 -5 -8 V

Positive Supply Current I+ — 1 3 mA fCLK = 0Hz

Negative Supply Current I– — 0.7 3 mA fCLK = 0Hz

Power Dissipation PD — 8.5 30 mΩfCLK = 0Hz

DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, TA = +25°C, FCLOCK = 200 kHz, V+ = +5V, V- = -5V.

Parameter Sym Min Typ Max Unit Conditions

Note 1: Functional operation is not implied.

2: Limit input current to under 100 µA if input voltages exceed supply voltage.

3: Full scale voltage = 2V.

4: VIN = 0V.

5: 0°C ≤ TA ≤ +70°C.

6: External reference temperature coefficient less than 0.01ppm/°C.

7: -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line.

8: |VIN| = 1.9959.

9: Test circuit shown in Figure 6-7.

10: Specification related to clock frequency range over which the TC835 correctly performs its various functions. Increased

errors result at higher operating frequencies.

TC835

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Pin Number

28-Pin PDIP Symbol Description

1 V- Negative power supply input.

2 REF IN External reference input.

3 ANALOG COMMON Reference point for REF IN.

4 INT OUT Integrator output. Integrator capacitor connection.

5 AZ IN Auto zero input. Auto zero capacitor connection.

6 BUFF OUT Analog input buffer output. Integrator resistor connection.

REF- Reference capacitor input. Reference capacitor negative connection.

REF+ Reference capacitor input. Reference capacitor positive connection.

9 -INPUT Analog input. Analog input negative connection.

10 +INPUT Analog input. Analog input positive connection.

11 V+ Positive power supply input.

12 D5 Digit drive output. Most Significant Digit (MSD)

13 B1 Binary Coded Decimal (BCD) output. Least Significant Bit (LSB)

14 B2 BCD output.

15 B4 BCD output.

16 B8 BCD output. Most Significant Bit (MSB)

17 D4 Digit drive output.

18 D3 Digit drive output.

19 D2 Digit drive output.

20 D1 Digit drive output. Least Significant Digit (LSD)

21 BUSY Busy output. At the beginning of the signal-integration phase, BUSY goes High and

remains High until the first clock pulse after the integrator zero crossing.

22 CLOCK IN Clock input. Conversion clock connection.

23 POLARITY Polarity output. A positive input is indicated by a logic High output. The polarity output is

valid at the beginning of the reference integrate phase and remains valid until determined

during the next conversion.

24 DGND Digital logic reference input.

25 RUN/HOLD Run / Hold input. When at a logic High, conversions are performed continuously. A logic

Low holds the current data as long as the Low condition exists.

26 STROBE Strobe output. The STROBE output pulses low in the center of the digit drive outputs.

27 OVERRANGE Over range output. A logic High indicates that the analog input exceeds the full scale input

range.

28 UNDERRANGE Under range output. A logic High indicates that the analog input is less than 9% of the full

scale input range.

TC835

3.0 DETAILED DESCRIPTION

(All Pin Designations Refer to 28-Pin DIP)

3.1 Dual Slope Conversion Principles

The TC835 is a dual slope, integrating analog-to-digital

converter. An understanding of the dual slope

conversion technique will aid in following the detailed

TC835 operational theory.

The conventional dual slope converter measurement

cycle has two distinct phases:

1. Input signal integration.

2. Reference voltage integration (de-integration).

The input signal being converted is integrated for a

fixed time period, with time being measured by

counting clock pulses. An opposite polarity constant

reference voltage is then integrated until the integrator

output voltage returns to zero. The reference

integration time is directly proportional to the input

signal.

In a simple dual slope converter, a complete

conversion requires the integrator output to "ramp-up"

and "ramp-down."

A simple mathematical equation relates the input sig-

nal, reference voltage and integration time:

EQUATION 3-1:

For a constant VIN:

EQUATION 3-1:

The dual slope converter accuracy is unrelated to the

integrating resistor and capacitor values, as long as

they are stable during a measurement cycle. An

inherent benefit is noise immunity. Noise spikes are

integrated, or averaged, to zero during the integration

periods. Integrating ADCs are immune to the large

conversion errors that plague successive approxima-

tion converters in high noise environments (see

Figure 3-1).

FIGURE 3-1: Basic Dual Slope Converter.

3.2 Operational Theory

The TC835 incorporates a system zero phase and

integrator output voltage zero phase to the normal two

phase dual slope measurement cycle. Reduced

system errors, fewer calibration steps and a shorter

overrange recovery time result.

The TC835 measurement cycle contains four phases:

1. System zero.

2. Analog input signal integration.

3. Reference voltage integration.

4. Integrator output zero.

Internal analog gate status for each phase is shown in

Table 3-6.

3.2.1 SYSTEM ZERO

During this phase, errors due to buffer, integrator and

comparator offset voltages are compensated for by

charging CAZ (auto zero capacitor) with a compensat-

ing error voltage. With a zero input voltage the

integrator output will remain at zero.

The external input signal is disconnected from the

internal circuitry by opening the two SWI switches. The

internal input points connect to ANALOG COMMON.

The reference capacitor charges to the reference

voltage potential through SWR. A feedback loop,

closed around the integrator and comparator, charges

the CAZ capacitor with a voltage to compensate for

buffer amplifier, integrator and comparator offset

voltages (see Figure 3-2).

Where:

VREF = Reference voltage

TINT = Signal integration time (fixed)

TDEINT = Reference voltage integration

time (variable)

RINTCINT

------------------------VIN T()DT

TINT

∫VREFTDEINT

RINTCINT

--------------------------------=

VIN

VREFTDEINT

tINT

--------------------------------=

REF

Voltage

Analog Input

Signal

Display

Switch

Drive

Control

Logic

Integrator

Output

Clock

Counter

Polarity Control

Phase

Control

VIN ≈ VREF

Variable

Reference

Integrate

Time

Fixed

Signal

Integrate

Time

Integrator Comparator

VIN ≈ 1/2 VREF

Egg g? W5 }§:§f W

TC835

FIGURE 3-2: System Zero Phase.

3.2.2 ANALOG INPUT SIGNAL

INTEGRATION

The TC835 integrates the differential voltage between

the +INPUT and -INPUT pins. The differential voltage

must be within the device Common mode range (-1V

from either supply rail, typically). The input signal polar-

ity is determined at the end of this phase (see

Figure 3-3).

FIGURE 3-3: Input Signal Integration

Phase.

3.2.3 REFERENCE VOLTAGE

INTEGRATION

The previously charged reference capacitor is con-

nected with the proper polarity to ramp the integrator

output back to zero (see Figure 3-4). The digital read-

ing displayed is:

FIGURE 3-4: Reference Voltage

Integration Cycle.

3.2.4 INTEGRATOR OUTPUT ZERO

This phase guarantees the integrator output is at 0V

when the system zero phase is entered and that the

true system offset voltages are compensated for. This

phase normally lasts 100 to 200 clock cycles. If an

overrange condition exists, the phase is extended to

6200 clock cycles (see Figure 3-5).

FIGURE 3-5: Integrator Output Zero

Phase.

TABLE 3-6: INTERNAL ANALOG GATE STATUS

+IN

REF

Analog

Common

SWRSWIZ SWZ

SWZIntegrator

Switch Closed

Switch Open

SWRI+

Comparator

Section

Analog

Input Buffer

RINT CINT

CREF

CSZ

SWRI-

SWI

SWZ

SWRI+

SWRI-

SWISW1

Digital

–

+IN

REF

Analog

Common

SWR

SWIZ SWZ

SWZIntegrator

Switch Closed

Switch Open

SWRI+

Comparator

Section

Analog

Input Buffer RINT CINT

CREF

CSZ

SWRI-

SWI

SWZ

SWRI+

SWRI-

SWISW1

–Digital

Reading = 10,000

[Differential Input]

VREF

–

+IN

REF

Analog

Common

SWR

SWIZ SWZ

SWZIntegrator

Switch Closed

Switch Open

SWRI+

Comparator

Section

Analog

Input Buffer

RINT CINT

CREF

CSZ

SWRI-

SWI

SWZ

SWRI+

SWRI-

SWISW1

–Digital

–

+IN

REF

Analog

Common

SWR

SWIZ SWZ

SWZIntegrator

Switch Closed

Switch Open

SWRI+

Comparator

Section

Analog

Input BufferRINT CINT

CREF

CSZ

SWRI-

SWI

SWZ

SWRI+

SWRI-

SWISW1

–Digital

Conversion Cycle Phase SWISWRI+SW

RI-SW

ZSWRSW1 SWIZ Reference Figures

System Zero — — — Closed Closed Closed — Figure 3-2

Input Signal Integration Closed — — — — — — Figure 3-3

Reference Voltage Integration — Closed* — — — Closed — Figure 3-4

Integrator Output Zero — — — — — Closed Closed Figure 3-5

*Note: Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.

i K?

TC835

4.0 ANALOG SECTION

FUNCTIONAL DESCRIPTION

4.1 Differential Inputs

The TC835 operates with differential voltages within

the input amplifier Common mode range. The input

amplifier Common mode range extends from 0.5V

below the positive supply to 1V above the negative

supply. Within this Common mode voltage range, an

86dB Common mode rejection ratio is typical.

The integrator output also follows the Common mode

voltage. The integrator output must not be allowed to

saturate. An example of a worst case condition would

be when a large positive Common mode voltage with a

near full scale negative differential input voltage is

applied. The negative input signal drives the integrator

positive when most of its swing has been used up by

the positive Common mode voltage. For these critical

applications, the integrator swing can be reduced to

less than the recommended 4V full scale swing, with

the effect of reduced accuracy. The integrator output

can swing within 0.3V of either supply without loss of

linearity.

4.2 Analog Common Input

ANALOG COMMON is used as the -INPUT return dur-

ing auto zero and de-integrate. If -INPUT is different

from ANALOG COMMON, a Common mode voltage

exists in the system. This signal is rejected by the

excellent CMRR of the converter. In most applications,

-INPUT will be set at a fixed, known voltage (power

supply common, for instance). In this application,

ANALOG COMMON should be tied to the same point,

thus removing the common-mode voltage from the

converter. The reference voltage is referenced to

ANALOG COMMON.

4.3 Reference Voltage Input

The REF IN input must be a positive voltage with

respect to ANALOG COMMON. A reference voltage

circuit is shown in Figure 4-1.

FIGURE 4-1: Using An External

Reference.

MCP1525

2.5 VREF

V+ 10 kΩ

10 kΩ

V+

REF

ANALOG

COMMON

Analog Ground

TC835

1µF

RUN/

TC835

5.0 DIGITAL SECTION

FUNCTIONAL DESCRIPTION

The major digital subsystems within the TC835 are

illustrated in Figure 5-1, with timing relationships

shown in Figure 5-2. The multiplexed BCD output data

can be displayed on LCD or LED. The digital section is

best described through a discussion of the control sig-

nals and data outputs.

FIGURE 5-1: Digital Section Functional Diagram.

Latch Latch Latch Latch Latch

Counters

Control Logic

Multiplexer

Polarity D5 D4 D3 D2 D1

13 B1

14 B2

15 B4

16 B8

Polarity

MSB Digit Drive Signal LSB

Data

Output

24 22 25 27 28 26 21

DGND Clock

In RUN/

HOLD Overrange STROBE BusyUnderrange

Zero

Cross

Detect

From

Analog

Section

TC835

FIGURE 5-2: Timing Diagrams for

Outputs.

5.1 RUN/HOLD Input

When left open, this pin assumes a logic "1" level. With

a RUN/HOLD = 1, the TC835 performs conversions

continuously, with a new measurement cycle beginning

every 40,002 clock pulses.

When RUN/HOLD changes to a logic "0," the measure-

ment cycle in progress will be completed, and data held

and displayed as long as the logic "0" condition exists.

A positive pulse (> 300 ns) at RUN/HOLD initiates a

new measurement cycle. The measurement cycle in

progress when RUN/HOLD initially assumed the logic

"0" state must be completed before the positive pulse

can be recognized as a single conversion run

command.

The new measurement cycle begins with a

10,001-count auto zero phase. At the end of this phase,

the busy signal goes high.

5.2 STROBE Output

During the measurement cycle, the STROBE control

line is pulsed low five times. The five low pulses occur

in the center of the digit drive signals (D1, D2, D3, D5)

(see Figure 5-3).

D5 (MSD) goes high for 201 counts when the measure-

ment cycles end. In the center of the D5 pulse, 101

clock pulses after the end of the measurement cycle,

the first STROBE occurs for one-half clock pulse. After

the D5 digit strobe, D4 goes high for 200 clock pulses.

The STROBE goes low 100 clock pulses after D4 goes

high. This continues through the D1 digit drive pulse.

The digit drive signals will continue to permit display

scanning. STROBE pulses are not repeated until a new

measurement is completed. The digit drive signals will

not continue if the previous signal resulted in an

overrange condition.

The active low STROBE pulses aid BCD data transfer

to UARTs, processors and external latches.

FIGURE 5-3: Strobe Signal Low Five

Times Per Conversion.

5.3 BUSY Output

At the beginning of the signal integration phase, BUSY

goes high and remains high until the first clock pulse

after the integrator zero crossing. BUSY returns to the

logic "0" state after the measurement cycle ends in an

overrange condition. The internal display latches are

loaded during the first clock pulse after BUSY and are

latched at the clock pulse end. The BUSY signal does

not go high at the beginning of the measurement cycle,

which starts with the auto zero cycle.

Integrator

Output

Overrange when

Applicable

Underrange when

Applicable

System

Zero

10,001

Counts

Signal

Integrate

10,000

Counts

(Fixed)

Reference

Integrate

20,001

Counts (Max)

Full Measurement Cycle

40,002 Counts

Busy

Expanded Scale Below

100

Counts

Digit Scan

STROBE

Auto-Zero Signal

Integrate Reference

Integrate

Digit Scan

for Overrange

* First D5 of System Zero and

Reference Integrate One Count

Longer

End of Conversion

(MSD)

Data

Busy

B1 B8

STROBE

Data D3

Data D2

Data (LSD)

Data D5

Data

Note Absence

of STROBE

201

Counts

200

Counts

200

Counts

200

Counts

200

Counts

200

Counts

200

Counts

*Delay between Busy going Low and First STROBE pulse is

dependent on Analog Input.

TC835

Outputs

D5 D1

TC835

5.4 OVERRANGE Output

If the input signal causes the reference voltage integra-

tion time to exceed 20,000 clock pulses, the

OVERRANGE output is set to a logic "1." The

overrange output register is set when BUSY goes low,

and is reset at the beginning of the next reference

integration phase.

5.5 UNDERRANGE Output

If the output count is 9% of full scale or less (-1800

counts), the underrange register bit is set at the end of

BUSY. The bit is set low at the next signal integration

phase.

5.6 POLARITY Output

A positive input is registered by a logic "1" polarity

signal. The POLARITY bit is valid at the beginning of

Reference Integrate and remains valid until determined

during the next conversion.

The POLARITY bit is valid even for a zero reading.

Signals less than the converter's LSB will have the

signal polarity determined correctly. This is useful in

null applications.

5.7 Digit Drive Outputs

Digit drive signals are positive going signals. The scan

sequence is D5 to D1. All positive pulses are 200 clock

pulses wide, except D5, which is 201 clock pulses wide.

All five digits are scanned continuously, unless an over-

range condition occurs. In an overrange condition, all

digit drives are held low from the final STROBE pulse

until the beginning of the next reference integrate

phase. The scanning sequence is then repeated. This

provides a blinking visual display indication.

5.8 BCD Data Outputs

The binary coded decimal (BCD) bits B8, B4, B2, B1 are

positive-true logic signals. The data bits become active

simultaneously with the digit drive signals. In an

overrange condition, all data bits are at a logic "0" state.

TC835

6.0 TYPICAL APPLICATIONS

6.1 Component Value Selection

The integrating resistor is determined by the full-scale

input voltage and the output current of the buffer used

to charge the integrator capacitor. Both the buffer

amplifier and the integrator have a class A output

stage, with 100 µA of quiescent current. A 20 µA drive

current gives negligible linearity errors. Values of 5 µA

to 40 µA give good results. The exact value of an

integrating resistor for a 20 µA current is easily

calculated.

EQUATION 6-1:

6.1.1 INTEGRATING CAPACITOR

The product of integrating resistor and capacitor should

be selected to give the maximum voltage swing that

ensures the tolerance buildup will not saturate the

integrator swing (approximately 0.3V from either

supply). For ±5V supplies and ANALOG COMMON tied

to supply ground, a ±3.5V to ±4V full-scale integrator

swing is adequate. A 0.10 µF to 0.47 µF is

recommended. In general, the value of CINT is given

by:

EQUATION 6-2:

A very important characteristic of the integrating

capacitor is that it has low dielectric absorption to

prevent rollover or ratiometric errors. A good test for

dielectric absorption would be to use the capacitor with

the input tied to the reference. This ratiometric

condition should read half scale 0.9999, with any

deviation probably due to dielectric absorption.

Polypropylene capacitors give undetectable errors at

reasonable cost. Polystyrene and polycarbonate

capacitors may also be used in less critical

applications.

6.1.2 AUTO ZERO AND REFERENCE

CAPACITORS

The size of the auto zero capacitor has some influence

on the noise of the system. A large capacitor reduces

the noise. The reference capacitor should be large

enough such that stray capacitance to ground from its

nodes is negligible.

The dielectric absorption of the reference capacitor and

auto zero capacitor are only important at power-on or

when the circuit is recovering from an overload.

Smaller or cheaper capacitors can be used if accurate

readings are not required for the first few seconds of

recovery.

6.1.3 REFERENCE VOLTAGE

The analog input required to generate a full scale

output is VIN = 2VREF.

The stability of the reference voltage is a major factor in

the overall absolute accuracy of the converter. For this

reason, it is recommended that a high-quality reference

be used where high-accuracy absolute measurements

are being made.

6.2 Conversion Timing

6.2.1 LINE FREQUENCY REJECTION

A signal integration period at a multiple of the 60Hz line

frequency will maximize 60Hz "line noise" rejection. A

200 kHz clock frequency will reject 60Hz and 400Hz

noise. This corresponds to five readings per second

(see Table 6-1 and Table 6-2).

TABLE 6-1: CONVERSION RATE VS.

CLOCK FREQUENCY

RINT = Full scale voltage

20µA

CINT = [10,000 x clock period] x IINT

Integrator output voltage swing

= (10,000) (clock period) (20

Integrator output voltage swing

Oscillator Frequency

(kHz) Conversion Rate

(Conv./Sec.)

100 2.5

120 3

200 5

300 7.5

400 10

800 20

1200 30

TC835

TABLE 6-2: LINE FREQUENCY VS.

CLOCK FREQUENCY

The conversion rate is easily calculated:

EQUATION 6-3:

6.3 Power Supplies and Grounds

6.3.1 POWER SUPPLIES

The TC835 is designed to work from ±5V supplies. For

single +5V operation, a ICL7135 can provide a –5V

supply.

6.3.2 GROUNDING

Systems should use separate digital and analog

ground systems to avoid loss of accuracy.

6.4 High-Speed Operation

The maximum conversion rate of most dual-slope A/D

converters is limited by the frequency response of the

comparator. The comparator in this circuit follows the

integrator ramp with a 3 µs delay, and at a clock

frequency of 200 kHz (5 µs period), half of the first

reference integrate clock period is lost in delay. This

means that the meter reading will change from 0 to 1

with a 50 µV input, 1 to 2 with 150 µV, 2 to 3 at 250 µV,

etc. This transition at midpoint is considered desirable

by most users, however, if the clock frequency is

increased appreciably above 200 kHz, the instrument

will flash "1" on noise peaks even when the input is

shorted.

For many dedicated applications where the input signal

is always of one polarity, the delay of the comparator

need not be a limitation. Since the nonlinearity and

noise do not increase substantially with frequency,

clock rates of up to ~1 MHz may be used. For a fixed

clock frequency, the extra count or counts caused by

comparator delay will be a constant and can be

subtracted out digitally.

The clock frequency may be extended above 200 kHz

without this error, however, by using a low-value

resistor in series with the integrating capacitor. The

effect of the resistor is to introduce a small pedestal

voltage onto the integrator output at the beginning of

the reference integrate phase. By careful selection of

the ratio between this resistor and the integrating

resistor (a few tens of ohms in the recommended

circuit), the comparator delay can be compensated and

the maximum clock frequency extended by approxi-

mately a factor of 3. At higher frequencies, ringing and

second-order breaks will cause significant nonlineari-

ties in the first few counts of the instrument.

The minimum clock frequency is established by leak-

age on the auto zero and reference capacitors. With

most devices, measurement cycles as long as 10 sec-

onds give no measurable leakage error.

The clock used should be free from significant phase or

frequency jitter. Several suitable low-cost oscillators

are shown in Section 6.0 “Typical Applications”,

Typical Applications. The multiplexed output means

that if the display takes significant current from the logic

supply, the clock should have good PSRR.

6.5 Zero Crossing Flip-Flop

The flip flop interrogates the data once every clock

pulse after the transients of the previous clock pulse

and half-clock pulse have died down. False zero cross-

ings caused by clock pulses are not recognized. Of

course, the flip flop delays the true zero crossing by up

to one count in every instance. If a correction were not

made, the display would always be one count too high.

Therefore, the counter is disabled for one clock pulse

at the beginning of the reference integrate (de-inte-

grate) phase. This one-count delay compensates for

the delay of the zero crossing flip flop and allows the

correct number to be latched into the display. Similarly,

a one-count delay at the beginning of auto zero gives

an overload display of 0000 instead of 0001. No delay

occurs during signal integrate, so that true ratiometric

readings result.

Oscillator Frequency

(kHz)

Line Frequency Rejection

60Hz 50Hz 400Hz

50.000 • • •

53.333 — — •

66.667 • — •

80.000 — — •

83.333 — • •

100.000 • • •

125.000 — • •

133.333 — — •

166.667 — — •

200.000 • — •

250.000

Reading 1/sec = Clock Frequency (Hz)

4000

TC835

FIGURE 6-3: 4-1/2 Digit ADC Multiplexed Common Anode LED Display.

FIGURE 6-4: RC Oscillator Circuit.

FIGURE 6-5: Comparator Clock Circuits.

20 19 18 17 12

59 15

bc 7777

DM7447A

Blank MSD On Zero

D1 D2 D3 D4 D5

INT OUT

AZ IN

BUFF

OUT

FIN

+INPUT

–INPUT

ANALOG

COMMON

V– REF

POL

CREF –

+5V

0.33 µF

200 kHz

–

Analog

Input 1µF

100 kΩ

1µF

4.7 kΩ

1µF

100 kΩ

RBI

V+

CREF+

TC835

MCP1525

a. If R1 = R2 = R1, F≅ 0.55/RC

a. F = 120 kHz, C = 420 pF

R1 = 8.93 kΩ

R1 = 27.3 kΩ

R2R1

Gates are 74C04

FO1

2C0.41RP0.7R1

+()

--------------------------------------------------=,RP

R1R2

------------------=

b. If R2 >> R1, F ≅ 0.45/R1C

c. If R2 << R1, F ≅ 0.72/R1C

2. Examples:

R1 = R2 ≈ 10.9 kΩ

b. F = 120 kHz, C = 420pF, R2 = 50 kΩ

c. F = 120 kHz, C = 220 pF, R2 = 5 kΩ

+5V

VOUT

390 pF

30 kΩ

16 kΩ

0.22 µF

16 kΩ

1kΩ

+5V

VOUT

100 kΩ

100 kΩR3

50 kΩ

10 pF

2kΩ

0.1 µF

–

LM311

–

LM311

56 kΩ

UR REF \N OR ANALOGi GND STHDEE \NT ‘7 OUT RUN HOLD AZ w DGND EUFF OUT POLAR‘TV CREF+ CLK IN BUSY Maw

TC835

FIGURE 6-6: 4-1/2 Digit ADC with Multiplexed Common Cathode LED Display.

FIGURE 6-7: Test Circuit.

REF IN

ANALOG

GND

INT

OUT

AZ IN

BUFF

OUT

CREF+

+5V

DGND

POLARITY

STROBE

RUN/HOLD

CLK IN

BUSY

SET VREF = 1V

100

kΩ

Analog

GND

0.33 µF

100 kΩ

1µF

kΩ

150Ω

+5V

150Ω

+5V

MC14513

1µF

–INPUT

+INPUT

V+

D5 (MSD)

B1 (LSB)

(LSD) D1

(MSB) B8

100

kΩ

SIG

0.1

µF

+5V

FOSC = 200 kHz

CREF –

V– TC835

MCP1525

TC835

100 kΩ

Analog GND

100 kΩ

Signal

Input

0.1 µF

SET VREF = 1V

V-

REF IN

ANALOG

COMMON

INT OUT

AZ IN

BUFF OUT

CREF-

CREF+

-INPUT

+INPUT

D5 (MSD)

B1 (LSB)

V+

UNDERRANGE

OVERRANGE

STROBE

RUN/HOLD

DIGTAL GND

POLARITY

CLOCK IN

BUSY

(LSD) D1

(MSB) B8

+5V

1µF

100 kΩ

1µF

0.47 µF

VREF IN

Clock Input

120 kHz

H‘Vf‘vf‘vf‘lf‘lﬂ‘wf‘wf‘lf‘lf‘lf‘lf‘vf‘lf‘l H‘WH‘WH‘NH‘IH‘IH‘NH‘NH‘IH‘IH‘WH‘WH‘VH‘IH‘N CPI O O U U U U U U U U U U U U U U HJHJU U U U U U U U U U U U HHHHHHHHHHH HHHHHHHHHHH HHHHHHHHHHH UHUHUUUHUHU HHHHHHHHHHH UUHUUUUUUUU O UUUUUUUUHUU m HHHHHHHHHHHHHH Mucaump XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWXXX Mlcﬁncmv TCBBSCBU HHHHHHHHHHHHHH NMN alor ( ,)

TC835

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

28-Pin PDIP (Wide)

XXXXXXXXXXXXXXX

YYWWNNN

Example:

TC835CPI^^

0741256

44-Pin MQFP

Example:

64-Pin MQFP Example:

XXXXXXXXXX

YYWWNNN

XXXXXXXXXX

TC835CKW

^^0741256

XXXXXXXXXX

YYWWNNN

XXXXXXXXXX

TC835CBU

0741256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

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TC835

APPENDIX A: REVISION HISTORY

Revision C (November 2007)

The following is the list of modifications:

1. DC Characteristics: Changed “Display Reading in

Ratiometric Operation” from +0.9996 to +0.9995.

2. Updates package marking information for pb-

free markings.

3. Updated package outline drawings and added

landing pattern to applicable package outline

drawing.

Revision B (May 2002)

The following is the list of modifications:

1. Undocumented changes

Revision A (April 2002)

• Original Release of this Document.

TC835

NOTES:

PART NO. IXX

TC835

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device TC835: 4-1/2 Digit BCD A/D for PC Data Acq.

Temperature Range C = 0°C to +70°C

Package PI = Plastic DIP, (600 mil Body), 28-lead

KW = Plastic Metric Quad Flatpack, (MQFP), 44-lead

BU = Plastic Metric Quad Flatpack, (MQFP), 64-lead

PART NO. X/XX

PackageTemperature

Range

Device

Examples:

a) TC835CBU: 4-1/2 Digit BCD A/D,

64LD MQFP package.

b) TC835CKW: 4-1/2 Digit BCD A/D,

44LD MQFP package.

c) TC835CPI: 4-1/2 Digit BCD A/D,

28LD PDIP package.

TC835

NOTES:

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 1694922002 =

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The

Embedded Control Solutions Company are registered

trademarks of Microchip Technology Incorporated in the

U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

Q ‘MICROCHIP

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

10/05/07

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