PSoC® 4: PSoC 4000 Family Datasheet by Cypress Semiconductor Corp

PSoC® 4: PSoC 4000 Family

Datasheet

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-89638 Rev. *B Revised April 16, 2014

General Description

PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an

ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The

PSoC 4000 product family is the smallest member of the PSoC 4 platform architecture. It is a combination of a microcontroller with

standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, and

general-purpose analog. PSoC 4000 products will be fully upward compatible with members of the PSoC 4 platform for new applica-

tions and design needs.

Features

32-bit MCU Subsystem

■16-MHz ARM Cortex-M0 CPU

■Up to 16 KB of flash with Read Accelerator

■Up to 2 KB of SRAM

Programmable Analog

■Two current DACs (IDACs) for general-purpose or capacitive

sensing applications

■One low-power comparator with internal reference

Low Power 1.71-V to 5.5-V operation

■Deep Sleep mode with wake-up on interrupt and I2C address

detect

Capacitive Sensing

■Cypress Capacitive Sigma-Delta (CSD) provides best-in-class

signal-to-noise ratio (SNR) and water tolerance

■Cypress-supplied software component makes capacitive

sensing design easy

■Automatic hardware tuning (SmartSense™)

Serial Communication

■Multi-master I2C block with the ability to do address matching

during Deep Sleep and generate a wake-up on match

Timing and Pulse-Width Modulation

■One 16-bit Timer/Counter/Pulse-Width Modulator (TCPWM)

block

■Center-aligned, Edge, and Pseudo-Random modes

■Comparator-based triggering of Kill signals for motor drive and

other high-reliability digital logic applications

Up to 20 Programmable GPIO Pins

■24-pin QFN, 16-pin SOIC, 16-pin QFN, and 8-pin SOIC

packages

■GPIO pins on Ports 0, 1, and 2 can be CapSense or have other

functions

■Drive modes, strengths, and slew rates are programmable

PSoC Creator Design Environment

■Integrated Development Environment (IDE) provides

schematic design entry and build (with analog and digital

automatic routing)

■Applications Programming Interface (API) component for all

fixed-function and programmable peripherals

Industry-Standard Tool Compatibility

■After schematic entry, development can be done with

ARM-based industry-standard development tools

Ti: CYPRESS VERFORM

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 2 of 30

Contents

Functional Definition........................................................ 4

CPU and Memory Subsystem ..................................... 4

System Resources ...................................................... 4

Analog Blocks.............................................................. 5

Fixed Function Digital.................................................. 5

GPIO ........................................................................... 5

Special Function Peripherals....................................... 5

Pinouts .............................................................................. 6

Power................................................................................. 9

Unregulated External Supply....................................... 9

Regulated External Supply.......................................... 9

Development Support .................................................... 10

Documentation .......................................................... 10

Online ........................................................................ 10

Tools.......................................................................... 10

Electrical Specifications ................................................ 11

Absolute Maximum Ratings....................................... 11

Device Level Specifications....................................... 11

Analog Peripherals .................................................... 14

Digital Peripherals ..................................................... 16

Memory ..................................................................... 17

System Resources .................................................... 17

Ordering Information...................................................... 20

Part Numbering Conventions .................................... 20

Packaging........................................................................ 22

Package Outline Drawings........................................ 23

Acronyms........................................................................ 26

Document Conventions................................................. 28

Units of Measure ....................................................... 28

Revision History............................................................. 29

Sales, Solutions, and Legal Information...................... 30

Worldwide Sales and Design Support ....................... 30

Products .................................................................... 30

PSoC® Solutions ...................................................... 30

Cypress Developer Community................................. 30

Technical Support ..................................................... 30

WDT — Deep S‘eep

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 3 of 30

Figure 1. Block Diagram

PSoC 4000 devices include extensive support for programming,

testing, debugging, and tracing both hardware and firmware.

The ARM Serial-Wire Debug (SWD) interface supports all

programming and debug features of the device.

Complete debug-on-chip functionality enables full-device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator IDE provides fully integrated programming

and debug support for the PSoC 4000 devices. The SWD

interface is fully compatible with industry-standard third-party

tools. The PSoC 4000 family provides a level of security not

possible with multi-chip application solutions or with microcon-

trollers. It has the following advantages:

■Allows disabling of debug features

■Robust flash protection

■Allows customer-proprietary functionality to be implemented in

on-chip programmable blocks

The debug circuits are enabled by default and can only be

disabled in firmware. If they are not enabled, the only way to

re-enable them is to erase the entire device, clear flash

protection, and reprogram the device with new firmware that

enables debugging.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing

attacks due to a maliciously reprogrammed device or attempts to

defeat security by starting and interrupting flash programming

sequences. All programming, debug, and test interfaces are

disabled when maximum device security is enabled. Therefore,

PSoC 4000, with device security enabled, may not be returned

for failure analysis. This is a trade-off the PSoC 4000 allows the

customer to make.

Deep Sleep

Active/ Sleep

CPU Subsystem

SRAM

2 KB

SRAM Controller

ROM

4 KB

ROM Controller

Flash

16 KB

Read Accelerator

SPCIFSWD/TC

NVIC, IRQMX

Cortex

16 MHz

MUL

System Interconnect (Single/Multi Layer AHB)

I/O Subsystem

20 x GPIOs

IOSS GPIO (4x ports)

Peripherals

Peripheral Interconnect (MMIO)

PCLK

PSoC 4000

32-bit

AHB- Lite

DFT Logic

Test

DFT Analog

System Resources

Lite

Power

Clock

WDT

ILO

Reset

Clock Control

IMO

Sleep Control

PWRSYS

REFPOR

WIC

Reset Control

XRES

1x SCB-I2C

CapSense

High Speed I/O Matrix

Power Modes

1x TCPWM

CYPRESS rsnroiM

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 4 of 30

Functional Definition

CPU and Memory Subsystem

CPU

The Cortex-M0 CPU in the PSoC 4000 is part of the 32-bit MCU

subsystem, which is optimized for low-power operation with

extensive clock gating. Most instructions are 16 bits in length and

the CPU executes a subset of the Thumb-2 instruction set. This

enables fully compatible, binary, upward migration of the code to

higher performance processors, such as the Cortex-M3 and M4.

It includes a nested vectored interrupt controller (NVIC) block

with eight interrupt inputs and also includes a Wakeup Interrupt

Controller (WIC). The WIC can wake the processor from the

Deep Sleep mode, allowing power to be switched off to the main

processor when the chip is in the Deep Sleep mode.

The CPU also includes a debug interface, the serial wire debug

(SWD) interface, which is a 2-wire form of JTAG. The debug

configuration used for PSoC 4000 has four breakpoint (address)

comparators and two watchpoint (data) comparators.

Flash

The PSoC 4000 device has a flash module with a flash accel-

erator, tightly coupled to the CPU to improve average access

times from the flash block. The low-power flash block is designed

to deliver zero wait-state (WS) access time at 16 MHz.

SRAM

Two KB of SRAM are provided with zero wait-state access at

16 MHz.

SROM

A supervisory ROM that contains boot and configuration routines

is provided.

System Resources

Power System

The power system is described in detail in the section on Power

on page 9. It provides an assurance that voltage levels are as

required for each respective mode and either delays mode entry

(for example, on power-on reset (POR)) until voltage levels are

as required for proper functionality, or generates resets (for

example, on brown-out detection). The PSoC 4000 operates

with a single external supply over the range of either 1.8 V ±5%

(externally regulated) or 1.8 to 5.5 V (internally regulated) and

has three different power modes, transitions between which are

managed by the power system. The PSoC 4000 provides Active,

Sleep, and Deep Sleep low-power modes.

All subsystems are operational in Active mode. The CPU

subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep

mode, while all peripherals and interrupts are active with instan-

taneous wake-up on a wake-up event. In Deep Sleep mode, the

high-speed clock and associated circuitry is switched off;

wake-up from this mode takes 35 µS.

Clock System

The PSoC 4000 clock system is responsible for providing clocks

to all subsystems that require clocks and for switching between

different clock sources without glitching. In addition, the clock

system ensures that there are no metastable conditions.

The clock system for the PSoC 4000 consists of the internal main

oscillator (IMO) and the internal low-frequency oscillator (ILO)

and provision for an external clock.

Figure 2. PSoC 4000 MCU Clocking Architecture

The FCPU signal can be divided down to generate synchronous

clocks for the analog and digital peripherals. There are four clock

dividers for the PSoC 4000, each with 16-bit divide capability The

16-bit capability allows flexible generation of fine-grained

frequency values and is fully supported in PSoC Creator.

IMO Clock Source

The IMO is the primary source of internal clocking in the

PSoC 4000. It is trimmed during testing to achieve the specified

accuracy.The IMO default frequency is 24 MHz and it can be

adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO

tolerance with Cypress-provided calibration settings is ±2% (24

and 32 MHz).

ILO Clock Source

The ILO is a very low power, 40-kHz oscillator, which is primarily

used to generate clocks for the watchdog timer (WDT) and

peripheral operation in Deep Sleep mode. ILO-driven counters

can be calibrated to the IMO to improve accuracy. Cypress

provides a software component, which does the calibration.

Watchdog Timer

A watchdog timer is implemented in the clock block running from

the ILO; this allows watchdog operation during Deep Sleep and

generates a watchdog reset if not serviced before the set timeout

occurs. The watchdog reset is recorded in a Reset Cause

Reset

The PSoC 4000 can be reset from a variety of sources including

a software reset. Reset events are asynchronous and guarantee

reversion to a known state. The reset cause is recorded in a

determine the cause of the reset. An XRES pin is reserved for

external reset on the 24-pin package. An internal POR is

provided on the 16-pin and 8-pin packages. The XRES pin has

an internal pull-up resistor that is always enabled.

Voltage Reference

The PSoC 4000 reference system generates all internally

required references. A 1.2-V voltage reference is provided for the

comparator. The IDACs are based on a ±5% reference.

IMO

External Clock

CPU

(connects to GPIO pin P0.4)

Divide By

2,4,8

Ti: CYPRESS VERFORM

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 5 of 30

Analog Blocks

Low-power Comparators

The PSoC 4000 has a low-power comparator, which uses the

built-in voltage reference. Any one of up to 16 pins can be used

as a comparator input and the output of the comparator can be

brought out to a pin. The selected comparator input is connected

to the minus input of the comparator with the plus input always

connected to the 1.2-V voltage reference. This comparator is

also used for CapSense purposes and is not available during

CapSense operation.

Current DACs

The PSoC 4000 has two IDACs, which can drive any of up to 16

pins on the chip. These IDACs have programmable current

ranges.

Analog Multiplexed Buses

The PSoC 4000 has two concentric independent buses that go

around the periphery of the chip. These buses (called amux

buses) are connected to firmware-programmable analog

switches that allow the chip's internal resources (IDACs,

comparator) to connect to any pin on Ports 0, 1, and 2.

Fixed Function Digital

Timer/Counter/PWM (TCPWM) Block

The TCPWM block consists of a 16-bit counter with

user-programmable period length. There is a capture register to

record the count value at the time of an event (which may be an

I/O event), a period register that is used to either stop or

auto-reload the counter when its count is equal to the period

signals that are used as PWM duty cycle outputs. The block also

provides true and complementary outputs with programmable

offset between them to allow use as dead-band programmable

complementary PWM outputs. It also has a Kill input to force

outputs to a predetermined state; for example, this is used in

motor drive systems when an over-current state is indicated and

the PWM driving the FETs needs to be shut off immediately with

no time for software intervention.

Serial Communication Block (SCB)

The PSoC 4000 has a serial communication block, which imple-

ments a multi-master I2C interface.

I2C Mode: The hardware I2C block implements a full

multi-master and slave interface (it is capable of multi-master

arbitration). This block is capable of operating at speeds of up to

400 kbps (Fast Mode) and has flexible buffering options to

reduce interrupt overhead and latency for the CPU. It also

supports EZI2C that creates a mailbox address range in the

memory of the PSoC 4000 and effectively reduces I2C commu-

nication to reading from and writing to an array in memory. In

addition, the block supports an 8-deep FIFO for receive and

transmit which, by increasing the time given for the CPU to read

data, greatly reduces the need for clock stretching caused by the

CPU not having read data on time.

The I2C peripheral is compatible with the I2C Standard-mode and

Fast-mode devices as defined in the NXP I2C-bus specification

and user manual (UM10204). The I2C bus I/O is implemented

with GPIO in open-drain modes.

The PSoC 4000 is not completely compliant with the I2C spec in

the following respect:

■GPIO cells are not overvoltage tolerant and, therefore, cannot

be hot-swapped or powered up independently of the rest of the

I2C system.

GPIO

The PSoC 4000 has up to 20 GPIOs. The GPIO block imple-

ments the following:

■Eight drive modes:

❐Analog input mode (input and output buffers disabled)

❐Input only

❐Weak pull-up with strong pull-down

❐Strong pull-up with weak pull-down

❐Open drain with strong pull-down

❐Open drain with strong pull-up

❐Strong pull-up with strong pull-down

❐Weak pull-up with weak pull-down

■Input threshold select (CMOS or LVTTL).

■Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

■Selectable slew rates for dV/dt related noise control to improve

EMI

The pins are organized in logical entities called ports, which are

8-bit in width (less for Ports 2 and 3). During power-on and reset,

the blocks are forced to the disable state so as not to crowbar

any inputs and/or cause excess turn-on current. A multiplexing

network known as a high-speed I/O matrix is used to multiplex

between various signals that may connect to an I/O pin.

Data output and pin state registers store, respectively, the values

to be driven on the pins and the states of the pins themselves.

Every I/O pin can generate an interrupt if so enabled and each

I/O port has an interrupt request (IRQ) and interrupt service

routine (ISR) vector associated with it (4 for PSoC 4000).

Special Function Peripherals

CapSense

CapSense is supported in the PSoC 4000 through a CSD block

that can be connected to up to 16 pins through an analog mux

bus via an analog switch (pins on Port 3 are not available for

CapSense purposes). CapSense function can thus be provided

on any available pin or group of pins in a system under software

control. A PSoC Creator component is provided for the

CapSense block to make it easy for the user.

Shield voltage can be driven on another mux bus to provide

water-tolerance capability. Water tolerance is provided by driving

the shield electrode in phase with the sense electrode to keep

the shield capacitance from attenuating the sensed input.

Proximity sensing can also be implemented.

The CapSense block has two IDACs, which can be used for

general purposes if CapSense is not being used (both IDACs are

available in that case) or if CapSense is used without water

tolerance (one IDAC is available).

PERFORM

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 6 of 30

Pinouts

The following is the pin list for PSoC 4000. All Port pins support GPIO. Ports 0, 1, and 2 support CSD CapSense and analog mux bus

connections.

Table 1. PSoC 4000 Pin Descriptions

24-QFN 16-QFN 16-SOIC 8-SOIC

Pin Name Pin Name Pin Name Pin Name TCPWM Signals Alternate Functions

1 P0.0/TRIN0 TRIN0: Trigger

Input 0

2 P0.1/TRIN1/

CMPO_0

1 P0.1/TRIN1/C

MPO_0

3 P0.1/TRIN1/C

MPO_0

TRIN1: Trigger

Input 1

CMPO_0: Sense Comp

Out

3 P0.2/TRIN2 2 P0.2/TRIN2 4 P0.2/TRIN2 TRIN2: Trigger

Input 2

4 P0.3/TRIN3 TRIN3: Trigger

Input 3

5 P0.4/TRIN4/

CMPO_0/EX

T_CLK

3 P0.4/TRIN4/

CMPO_0/EXT

_CLK

5 P0.4/TRIN4/C

MPO_0/EXT_

CLK

2 P0.4/TRIN4/

CMPO_0/E

XT_CLK

TRIN4: Trigger

Input 4

CMPO_0: Sense Comp

Out, External Clock,

CMOD Cap

6 VCCD 4 VCCD 6 VCCD 3 VCCD

7 VDD 5 VDDIO 7 VDD 4 VDD

8 VSS 6 VDD 8 VSS 5 VSS

9 P0.5 7 VSS 9 P0.5

10 P0.6 8 P0.610P0.6

11 P0.7

12 P1.0

13 P1.1/OUT0 9 P1.1/OUT0 11 P1.1/OUT0 6 P1.1/OUT0 OUT0: PWM OUT

14 P1.2/SCL 10 P1.2/SCL 12 P1.2/SCL I2C SCL

15 P1.3/SDA 11 P1.3/SDA 13 P1.3/SDA I2C Data

16 P1.4/UND0 UND0: Underflow

Out

17 P1.5/OVF0 OVF0: Overflow

Out

18 P1.6/OVF0/U

ND0

/nOUT0/CMP

O_0

12 P1.6/OVF0/

UND0/nOUT0

/CMPO_0

14 P1.6/OVF0/U

ND0

/nOUT0/CMP

O_0

7 P1.6/OVF0/

UND0

/nOUT0/CM

PO_0

nOUT0:

Complement of

OUT0 (not OUT)

CMPO_0: Sense Comp

Out, Internal Reset

function during POR (must

not have load to ground

during POR).

19 P1.7/MATCH/

EXT_CLK

13 P1.7/MATCH/

EXT_CLK

15 P1.7/MATCH/

EXT_CLK

MATCH: Match

Out

External Clock

20 P2.0 16 P2.0

21 P3.0/SDA/

SWD_IO

14 P3.0/SDA/

SWD_IO

1 P3.0/SDA/

SWD_IO

8 P3.0/SDA/

SWD_IO

I2C Data, SWD IO

22 P3.1/SCL/

SWD_CLK

15 P3.1/SCL/

SWD_CLK

2 P3.1/SCL/

SWD_CLK

1 P3.1/SCL/

SWD_CLK

I2C Clock, SWD Clock

23 P3.2 16 P3.2 OUT0:PWM OUT

24 XRES XRES: External Reset

5’ CYPRESS PERFORM

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 7 of 30

Descriptions of the Pin functions are as follows:

VDD: Power supply for both analog and digital sections.

VDDIO: Where available, this pin provides a separate voltage domain (see the Power section for details).

VSS: Ground pin.

VCCD: Regulated digital supply (1.8 V ±5%).

Pins belonging to Ports 0, 1, and 2 can all be used as CSD sense and shield pins can be connected to AMUXBUS A or B or can all

be used as GPIO pins that can be driven by the firmware.

Pins on Port 3 can be used as GPIO, in addition to their alternate functions listed above.

The following packages are provided: 24-pin QFN, 16-pin QFN, 16-pin SOIC, and 8-pin SOIC.

Figure 3. 24-pin QFN Pinout

Figure 4. 16-Pin QFN Pinout

QFN

24Top

View

P0.5

XRES

24 23 22 21 20 19

78910

VDD

VSS

P0.6

P0.7

P1.0

P3.2

P3.1

P3.0

P2.0

P1.7

VCCD

P0.0

P0.1

P1.4

P1.3

P1.2

P1.1

P1.6

P1.5

11 12

P0.2

P0.3

P0.4

QFN

Top

View

P3.2

16 15 14 13

P3.1

P3.0

P1.7

P0.1

P0.2

P0.4

VCCD

P1.2

P1.1

P1.6

P1.3

VSS

567 8

VDDIO

VDD

P0.6

fYPREss PERIORM I'll—II'II'WI'IFII'IFI LILILILILILILILI

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 8 of 30

Figure 5. 16-Pin SOIC Pinout

Figure 6. 8-Pin SOIC Pinout

P3.0

16-SOIC

Top View

P3.1

P0.1

P0.2

P0.4

VCCD

VDD

VSS P0.5

P0.6

P1.1

P1.2

P1.3

P1.6

P1.7

P2.0

P3.1

P0.4

VCCD

VDD VSS

P1.1

P1.6

P3.0

8-SOIC

Top View

C5: .5 (NPRESS ”WORM ulﬂlll‘”

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 9 of 30

Power

The following power system diagrams (Figure 7 and Figure 8)

show the set of power supply pins as implemented for the

PSoC 4000. The system has one regulator in Active mode for the

digital circuitry. There is no analog regulator; the analog circuits

run directly from the VDD input. There is a separate regulator for

the Deep Sleep mode. The supply voltage range is either 1.8 V

±5% (externally regulated) or 1.8 V to 5.5 V (unregulated exter-

nally; regulated internally) with all functions and circuits

operating over that range.

The VDDIO pin, available in the 16-pin QFN package, provides a

separate voltage domain for the following pins: P3.0, P3.1, and

P3.2. P3.0 and P3.1 can be I2C pins and the chip can thus

communicate with an I2C system, running at a different voltage

(where VDDIO ≤ VDD). For example, VDD can be 3.3 V and VDDIO

can be 1.8 V.

The PSoC 4000 family allows two distinct modes of power supply

operation: Unregulated External Supply and Regulated External

Supply.

Unregulated External Supply

In this mode, the PSoC 4000 is powered by an external power

supply that can be anywhere in the range of 1.8 to 5.5 V. This

range is also designed for battery-powered operation. For

example, the chip can be powered from a battery system that

starts at 3.5 V and works down to 1.8 V. In this mode, the internal

regulator of the PSoC 4000 supplies the internal logic and the

VCCD output of the PSoC 4000 must be bypassed to ground via

an external capacitor (0.1 µF; X5R ceramic or better).

Bypass capacitors must be used from VDDD to ground. The

typical practice for systems in this frequency range is to use a

capacitor in the 1-µF range, in parallel with a smaller capacitor

(0.1 µF, for example). Note that these are simply rules of thumb

and that, for critical applications, the PCB layout, lead induc-

tance, and the bypass capacitor parasitic should be simulated to

design and obtain optimal bypassing.

An example of a bypass scheme follows (VDDIO is available on

the 16-QFN package).

Figure 7. 16-pin QFN Bypass Scheme Example - Unregulated

External Supply

Regulated External Supply

In this mode, the PSoC 4000 is powered by an external power

supply that must be within the range of 1.71 to 1.89 V; note that

this range needs to include the power supply ripple too. In this

mode, the VDD and VCCD pins are shorted together and

bypassed. The internal regulator is disabled in the firmware.

An example of a bypass scheme follows (VDDIO is available on

the 16-QFN package).

Figure 8. 16-pin QFN Bypass Scheme Example - Regulated

External Supply

PSoC 4000

VDD

VDDIO

VSS

1.71 V < VDDIO V

1.8 V to 5.5 V

0. 1 F

0.1

μF

VCCD

0. 1 F

Power supply connections when 1.8 VDD 5. 5 V

1 F

≤≤

≤

μμ

PSoC 4000

VDD

VDDIO

VSS

0.1 μF

VCCD

0.1 μF

Power supply connections when 1.71 ≤ VDD ≤ 1.89 V

1 μF

1.71 V to 1.89 V

1.71 V < VDDIO < VDD

Ti: CYPRESS VERFORM

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 10 of 30

Development Support

The PSoC 4000 family has a rich set of documentation, devel-

opment tools, and online resources to assist you during your

development process. Visit www.cypress.com/go/psoc4 to find

out more.

Documentation

A suite of documentation supports the PSoC 4000 family to

ensure that you can find answers to your questions quickly. This

section contains a list of some of the key documents.

Software User Guide: A step-by-step guide for using PSoC

Creator. The software user guide shows you how the PSoC

Creator build process works in detail, how to use source control

with PSoC Creator, and much more.

Component Datasheets: The flexibility of PSoC allows the

creation of new peripherals (components) long after the device

has gone into production. Component data sheets provide all of

the information needed to select and use a particular component,

including a functional description, API documentation, example

code, and AC/DC specifications.

Application Notes: PSoC application notes discuss a particular

application of PSoC in depth; examples include brushless DC

motor control and on-chip filtering. Application notes often

include example projects in addition to the application note

document.

Technical Reference Manual: The Technical Reference Manual

(TRM) contains all the technical detail you need to use a PSoC

device, including a complete description of all PSoC registers.

The TRM is available in the Documentation section at

www.cypress.com/psoc4.

Online

In addition to print documentation, the Cypress PSoC forums

connect you with fellow PSoC users and experts in PSoC from

around the world, 24 hours a day, 7 days a week.

Tools

With industry standard cores, programming, and debugging

interfaces, the PSoC 4000 family is part of a development tool

ecosystem. Visit us at www.cypress.com/go/psoccreator for the

latest information on the revolutionary, easy to use PSoC Creator

IDE, supported third party compilers, programmers, debuggers,

and development kits.

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 11 of 30

Electrical Specifications

Absolute Maximum Ratings

Device Level Specifications

All specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

Note

1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended

periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.

Table 2. Absolute Maximum Ratings[1]

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID1 VDDD_ABS Digital supply relative to VSS –0.5 – 6 V

SID2 VCCD_ABS Direct digital core voltage input relative

to VSS

–0.5 – 1.95 V

SID3 VGPIO_ABS GPIO voltage –0.5 – VDD+0.5 V

SID4 IGPIO_ABS Maximum current per GPIO –25 – 25 mA

SID5 IGPIO_injection GPIO injection current, Max for VIH >

VDDD, and Min for VIL < VSS

–0.5 – 0.5 mA Current injected

per pin

BID44 ESD_HBM Electrostatic discharge human body

model

2200 – – V

BID45 ESD_CDM Electrostatic discharge charged device

model

500 – – V

BID46 LU Pin current for latch-up –140 – 140 mA

Table 3. DC Specifications

Typical values measured at VDD = 3.3 V and 25 °C.

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID53 VDD Power supply input voltage 1.8 – 5.5 V With regulator

enabled

SID255 VDD Power supply input voltage (VCCD =

VDD)

1.71 – 1.89 V Internally unreg-

ulated supply

SID54 VDDIO VDDIO domain supply 1.71 – VDD V

SID55 CEFC External regulator voltage bypass – 0.1 – µF X5R ceramic or

better

SID56 CEXC Power supply bypass capacitor – 1 – µF X5R ceramic or

better

Active Mode, VDD = 1.8 to 5.5 V

SID9 IDD5 Execute from flash; CPU at 6 MHz – 2.0 2.85 mA

SID12 IDD8 Execute from flash; CPU at 12 MHz – 3.2 3.75 mA

SID16 IDD11 Execute from flash; CPU at 16 MHz – 4.0 4.5 mA

Sleep Mode, VDDD = 1.71 to 5.5 V

SID25 IDD20 I2C wakeup, WDT on. 6 MHz – 1.1 – mA

SID25A IDD20A I2C wakeup, WDT on. 12 MHz – 1.4 – mA

Deep Sleep Mode, VDD = 1.8 to 3.6 V (Regulator on)

SID31 IDD26 I2C wakeup and WDT on – 2.5 8.2 µA

[ 1 [ 1 [ 1 w w

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 12 of 30

GPIO

Deep Sleep Mode, VDD = 3.6 to 5.5 V (Regulator on)

SID34 IDD29 I2C wakeup and WDT on – 2.5 12 µA

Deep Sleep Mode, VDD = VCCD = 1.71 to 1.89 V (Regulator bypassed)

SID37 IDD32 I2C wakeup and WDT on – 2.5 9.2 µA

XRES Current

SID307 IDD_XR Supply current while XRES asserted – 2 5 mA

Table 3. DC Specifications (continued)

Typical values measured at VDD = 3.3 V and 25 °C.

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

Table 4. AC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID48 FCPU CPU frequency DC – 16 MHz 1.71 ≤ VDD ≤ 5.5

SID49[2] TSLEEP Wakeup from Sleep mode – 0 – µs

SID50[2] TDEEPSLEEP Wakeup from Deep Sleep mode – 35 – µs

Notes

2. Guaranteed by characterization.

3. VIH must not exceed VDDD + 0.2 V.

Table 5. GPIO DC Specifications (referenced to VDDIO for 16-Pin QFN VDDIO pins)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID57 VIH[3] Input voltage high threshold 0.7 ×

VDDD

– – V CMOS Input

SID58 VIL Input voltage low threshold – – 0.3 ×

VDDD

V CMOS Input

SID241 VIH[3] LVTTL input, VDDD < 2.7 V 0.7×

VDDD

–– V

SID242 VIL LVTTL input, VDDD < 2.7 V – – 0.3 ×

VDDD

SID243 VIH[3] LVTTL input, VDDD ≥ 2.7 V 2.0 – – V

SID244 VIL LVTTL input, VDDD ≥ 2.7 V – – 0.8 V

SID59 VOH Output voltage high level VDDD

–0.6

–– VI

OH = 4 mA at

3V V

DDD

SID60 VOH Output voltage high level VDDD

–0.5

–– VI

OH = 1 mA at

1.8 V VDDD

SID61 VOL Output voltage low level – – 0.6 V IOL = 4 mA at

1.8 V VDDD

SID62 VOL Output voltage low level – – 0.6 V IOL = 10 mA at

3V V

DDD

SID62A VOL Output voltage low level – – 0.4 V IOL = 3mA at 3V

VDDD

SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ

SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ

m PERFORM [4] w [4] AM [4] AM m m m m m m m

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 13 of 30

SID65 IIL Input leakage current (absolute value) – – 2 nA 25 °C, VDDD =

3.0 V

SID66 CIN Input capacitance – 3 7 pF

SID67[4] VHYSTTL Input hysteresis LVTTL 15 40 – mV VDDD ≥ 2.7 V

SID68[4] VHYSCMOS Input hysteresis CMOS 0.05 ×

VDDD

––mVV

DD < 4.5 V

SID68A[4] VHYSCMOS5V5 Input hysteresis CMOS 200 – – mV VDD > 4.5 V

SID69[4] IDIODE Current through protection diode to

VDD/VSS

––100µA

SID69A[4] ITOT_GPIO Maximum total source or sink chip

current

––85mA

Table 5. GPIO DC Specifications (referenced to VDDIO for 16-Pin QFN VDDIO pins) (continued)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

Note

4. Guaranteed by characterization.

Table 6. GPIO AC Specifications

(Guaranteed by Characterization)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID70 TRISEF Rise time in fast strong mode 2 – 12 ns 3.3 V VDDD,

Cload = 25 pF

SID71 TFALLF Fall time in fast strong mode 2 – 12 ns 3.3 V VDDD,

Cload = 25 pF

SID72 TRISES Rise time in slow strong mode 10 – 60 – 3.3 V VDDD,

Cload = 25 pF

SID73 TFALLS Fall time in slow strong mode 10 – 60 – 3.3 V VDDD,

Cload = 25 pF

SID74 FGPIOUT1 GPIO FOUT

; 3.3 V ≤ VDDD ≤ 5.5 V.

Fast strong mode.

– – 16 MHz 90/10%, 25 pF

load, 60/40 duty

cycle

SID75 FGPIOUT2 GPIO FOUT

; 1.71 V≤ VDDD≤ 3.3 V.

Fast strong mode.

– – 16 MHz 90/10%, 25 pF

load, 60/40 duty

cycle

SID76 FGPIOUT3 GPIO FOUT

; 3.3 V ≤ VDDD ≤ 5.5 V.

Slow strong mode.

– – 7 MHz 90/10%, 25 pF

load, 60/40 duty

cycle

SID245 FGPIOUT4 GPIO FOUT

; 1.71 V ≤ VDDD ≤ 3.3 V.

Slow strong mode.

– – 3.5 MHz 90/10%, 25 pF

load, 60/40 duty

cycle

SID246 FGPIOIN GPIO input operating frequency;

1.71 V ≤ VDDD ≤ 5.5 V

– – 16 MHz 90/10% VIO

EYPRESS vswop'M [ 1 [ 1 B|D#194[ 1

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 14 of 30

XRES

Analog Peripherals

Comparator

Note

5. Guaranteed by characterization.

Table 7. XRES DC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID77 VIH Input voltage high threshold 0.7 ×

VDDD

– – V CMOS Input

SID78 VIL Input voltage low threshold – – 0.3 ×

VDDD

V CMOS Input

SID79 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ

SID80 CIN Input capacitance – 3 7 pF

SID81[5] VHYSXRES Input voltage hysteresis – 05*VDD – mV Typical hysteresis

is 200 mV for VDD

> 4.5V

Table 8. XRES AC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID83[5] TRESETWIDTH Reset pulse width 5 – – µs

BID#194[5] TRESETWAKE Wake-up time from reset release – – 3 ms

Table 9. Comparator DC Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID330[5] ICMP1 Block current, High Bandwidth mode – – 110 µA

SID331[5] ICMP2 Block current, Low Power mode – – 85 µA

SID332[5] VOFFSET1 Offset voltage, High Bandwidth mode – 10 30 mV

SID333[5] VOFFSET2 Offset voltage, Low Power mode – 10 30 V

SID334[5] ZCMP DC input impedance of comparator 35 – – MΩ

SID338[5] VINP_COMP Comparator input range 0 – 3.6 V Max input voltage

is lower of 3.6 V or

VDD

Table 10. Comparator AC Specifications (Guaranteed by Characterization)

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

SID336[5] TCOMP1 Response Time High Bandwidth mode,

50-mV overdrive

– – 90 ns

SID337[5] TCOMP2 Response Time Low Power mode,

50-mV overdrive

– – 110 ns

SS ”mop

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 15 of 30

CSD

Table 11. CSD and IDAC Block Specifications

Spec ID# Parameter Description Min Typ Max Units Details/

Conditions

CSD and IDAC Specifications

SYS.PER#3 VDD_RIPPLE Max allowed ripple on power supply,

DC to 10 MHz

– – ±50 mV VDD > 2V (with ripple),

25 °C TA,

Sensitivity = 0.1 pF

SYS.PER#16 VDD_RIPPLE_1.8 Max allowed ripple on power supply,

DC to 10 MHz

– – ±25 mV VDD > 1.75V (with

ripple), 25 C TA, Parasitic

Capacitance (CP) <

20 pF, Sensitivity ≥ 0.4 pF

SID.CSD#15 VREF Voltage reference for CSD and

Comparator

1.1 1.2 1.3 V

SID.CSD#16 IDAC1IDD IDAC1 (8-bits) block current – – 1125 µA

SID.CSD#17 IDAC2IDD IDAC2 (7-bits) block current – – 1125 µA

SID308 VCSD Voltage range of operation 1.71 – 5.5 V 1.8 V ±5% or 1.8 V to

5.5 V

SID308A VCOMPIDAC Voltage compliance range of IDAC 0.8 – VDD –0.8 V

SID309 IDAC1DNL DNL for 8-bit resolution –1 – 1 LSB

SID310 IDAC1INL INL for 8-bit resolution –3 – 3 LSB

SID311 IDAC2DNL DNL for 7-bit resolution –1 – 1 LSB

SID312 IDAC2INL INL for 7-bit resolution –3 – 3 LSB

SID313 SNR Ratio of counts of finger to noise.

Guaranteed by characterization

5 – – Ratio Capacitance range of 9 to

35 pF, 0.1 pF sensitivity

SID314 IDAC1CRT1 Output current of IDAC1 (8 bits) in

high range

– 612 – µA

SID314A IDAC1CRT2 Output current of IDAC1(8 bits) in

low range

– 306 – µA

SID315 IDAC2CRT1 Output current of IDAC2 (7 bits) in

high range

– 304.8 – µA

SID315A IDAC2CRT2 Output current of IDAC2 (7 bits) in

low range

– 152.4 – µA

SID320 IDACOFFSET All zeroes input – – ±1 LSB

SID321 IDACGAIN Full-scale error less offset – – ±10 %

SID322 IDACMISMATCH Mismatch between IDACs – – 7 LSB

SID323 IDACSET8 Settling time to 0.5 LSB for 8-bit

IDAC

– – 10 µs Full-scale transition. No

external load.

SID324 IDACSET7 Settling time to 0.5 LSB for 7-bit

IDAC

– – 10 µs Full-scale transition. No

external load.

SID325 CMOD External modulator capacitor. – 2.2 – nF 5-V rating, X7R or NP0

cap.

‘5» ELYPRESS PERIOPM Fc max : CLK_SYS. Minimum possible Minimum lime Minimum pulse width Minimum pulse width

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 16 of 30

Digital Peripherals

Timer Counter Pulse-Width Modulator (TCPWM)

I2C

Note

6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.

7. Guaranteed by characterization.

Table 12. TCPWM Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID.TCPWM.1 ITCPWM1 Block current consumption at 3 MHz – – 45 μAAll modes (TCPWM)

SID.TCPWM.2 ITCPWM2 Block current consumption at 8 MHz – – 145 μAAll modes (TCPWM)

SID.TCPWM.2A ITCPWM3 Block current consumption at 16 MHz – – 160 μAAll modes (TCPWM)

SID.TCPWM.3 TCPWMFREQ Operating frequency – – Fc MHz Fc max = CLK_SYS.

Maximum = 16 MHz

SID.TCPWM.4 TPWMENEXT Input trigger pulse width 2/Fc – – ns For all trigger events[6]

SID.TCPWM.5 TPWMEXT Output trigger pulse widths 2/Fc – – ns

Minimum possible

width of Overflow,

Underflow, and CC

(Counter equals

Compare value)

outputs

SID.TCPWM.5A TCRES Resolution of counter 1/Fc – – ns

Minimum time

between successive

counts

SID.TCPWM.5B PWMRES PWM resolution 1/Fc – – ns Minimum pulse width

of PWM Output

SID.TCPWM.5C QRES Quadrature inputs resolution 1/Fc – – ns

Minimum pulse width

between Quadrature

phase inputs.

Table 13. Fixed I2C DC Specifications[7]

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID149 II2C1 Block current consumption at 100 kHz – – 25 µA

SID150 II2C2 Block current consumption at 400 kHz – – 135 µA

SID.PWR#5 ISBI2C I2C enabled in Deep Sleep mode – – 2.5 µA

Table 14. Fixed I2C AC Specifications[7]

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID153 FI2C1 Bit rate – – 400 Kbps

EYPRESS PERFORM TROWWR‘TE S|D18 S|D186 SID190l9l SID192I9I

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 17 of 30

Memory

System Resources

Power-on Reset (POR)

Table 15. Flash DC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID173 VPE Erase and program voltage 1.71 – 5.5 V

Notes

8. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied

on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.

Make certain that these are not inadvertently activated.

9. Guaranteed by characterization.

Table 16. Flash AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID174 TROWWRITE[8] Row (block) write time (erase and

program)

– – 20 ms Row (block) = 128 bytes

SID175 TROWERASE[8] Row erase time – – 13 ms

SID176 TROWPROGRAM[8] Row program time after erase – – 7 ms

SID178 TBULKERASE[8] Bulk erase time (16 KB) – – 15 ms

SID180[9] TDEVPROG[8] Total device program time – – 7.5 seconds

SID181[9] FEND Flash endurance 100 K – – cycles

SID182[9] FRET Flash retention. TA ≤ 55 °C, 100 K

P/E cycles

20 – – years

SID182A[9] Flash retention. TA ≤ 85 °C, 10 K

P/E cycles

10 – – years

Table 17. Power On Reset (PRES)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID.CLK#6 SR_POWER_UP Power supply slew rate 1 – 67 V/ms At power-up

SID185[9] VRISEIPOR Rising trip voltage 0.80 – 1.5 V

SID186[9] VFALLIPOR Falling trip voltage 0.70 – 1.4 V

Table 18. Brown-out Detect (BOD) for VCCD

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID190[9] VFALLPPOR BOD trip voltage in active and

sleep modes

1.48 – 1.62 V

SID192[9] VFALLDPSLP BOD trip voltage in Deep Sleep 1.11 – 1.5 V

SID231I‘DI smzaal‘ol S|D234 S|D236

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 18 of 30

SWD Interface

Internal Main Oscillator

Internal Low-Speed Oscillator

Note

10. Guaranteed by characterization.

Table 19. SWD Interface Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID213 F_SWDCLK1 3.3 V ≤ VDD ≤ 5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU

clock frequency

SID214 F_SWDCLK2 1.71 V ≤ VDD ≤ 3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU

clock frequency

SID215[10] T_SWDI_SETUP T = 1/f SWDCLK 0.25*T – – ns

SID216[10] T_SWDI_HOLD T = 1/f SWDCLK 0.25*T – – ns

SID217[10] T_SWDO_VALID T = 1/f SWDCLK – – 0.5*T ns

SID217A[10] T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns

Table 20. IMO DC Specifications

(Guaranteed by Design)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID218 IIMO1 IMO operating current at 48 MHz – – 250 µA

SID219 IIMO2 IMO operating current at 24 MHz – – 180 µA

Table 21. IMO AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID223 FIMOTOL1 Frequency variation at 24 and

32 MHz (trimmed)

––±2%2 V ≤ VDD ≤ 5.5 V, and

–25 °C ≤ TA ≤ 85 °C

SID223A FIMOTOLVCCD Frequency variation at 24 and

32 MHz (trimmed)

– – ±4 % All other conditions

SID226 TSTARTIMO IMO startup time – – 7 µs

SID228 TJITRMSIMO2 RMS jitter at 24 MHz – 145 – ps

Table 22. ILO DC Specifications

(Guaranteed by Design)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID231[10] IILO1 ILO operating current – 0.3 1.05 µA

SID233[10] IILOLEAK ILO leakage current – 2 15 nA

Table 23. ILO AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID234[10] TSTARTILO1 ILO startup time – – 2 ms

SID236[10] TILODUTY ILO duty cycle 40 50 60 %

SID237 FILOTRIM1 ILO frequency range 20 40 80 kHz

EYPREss PERIORM smaosl“J smacsml SID262W

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 19 of 30

Note

11. Guaranteed by characterization.

Table 24. External Clock Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID305[11] ExtClkFreq External clock input frequency 0 – 16 MHz

SID306[11] ExtClkDuty Duty cycle; measured at VDD/2 45 – 55 %

Table 25. Block Specs

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID262[11] TCLKSWITCH System clock source switching time 3 – 4 Periods

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 20 of 30

Ordering Information

The PSoC 4000 part numbers and features are listed in the following table.

Part Numbering Conventions

PSoC 4 devices follow the part numbering convention described in the following table. All fields are single-character alphanumeric (0,

1, 2, …, 9, A,B, …, Z) unless stated otherwise.

The part numbers are of the form CY8C4ABCDEF-XYZ where the fields are defined as follows.

Category

MPN

Features Package

Max CPU Speed

(MHz)

Flash (KB)

SRAM (KB)

UDB

Op-amp (CTBm)

CapSense

7-bit IDAC

8-bit IDAC

Comparators

TCPWM Blocks

SCB (I2C)

8-SOIC

16-SOIC

16-QFN

24-QFN

CY8C4013

CY8C4013SXI-4001682––––––114–––

CY8C4013SXI-4101682–––111114–––

CY8C4013SXI-4111682–––11111–4––

CY8C4013LQI-4111682–––11111––4–

CY8C4014

CY8C4014SXI-41116162–––11111–4––

CY8C4014SXI-420 16 16 2 – – 4111114–––

CY8C4014SXI-421 16 16 2 – – 411111–4––

CY8C4014LQI-421 16 16 2 – – 411111––4–

CY8C4014LQI-41216162–––11111–––4

CY8C4014LQI-422 16 16 2 – – 411111–––4

Other

CY8C4014LQI-SLT1 16 16 2 – – 411111––4–

CY8C4014LQI-SLT2 16 16 2 – – 411111–––4

Architecture

Cypress Prefix

Family Group within Architecture

Speed Grade

Flash Capacity

Package Code

Temperature Range

Peripheral Set

4: PSoC 4

1: 16MHz

4: 16KB

LQ: SSOP

I : Industrial

Examples CY8C 4 A EDCBFxx-x

0: 4000 Family

EYPREss PERIORM

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 21 of 30

The Field Values are listed in the following table:

Field Description Values Meaning

CY8C Cypress prefix

4 Architecture 4 PSoC 4

A Family 0 4000 Family

B CPU speed 1 16 MHz

448 MHz

C Flash capacity 3 8 KB

416 KB

532 KB

664 KB

7 128 KB

DE Package code SX SOIC

LQ QFN

F Temperature range I Industrial

XYZ Attributes code 000-999 Code of feature set in specific family

EYPREss PERIOPM

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 22 of 30

Packaging

Table 26. Package List

Spec ID# Package Description

BID#26 QFN-24 24-pin 4 x 4 x 0.6 mm QFN with 0.5-mm pitch

BID#33 QFN-16 16-pin 3 x 3 x 0.6 mm QFN with 0.5-mm pitch

BID#40 SOIC-16 16-pin (150 Mil) SOIC

BID#47 SOIC-8 8-pin (150 Mil) SOIC

Table 27. Package Characteristics

Parameter Description Conditions Min Typ Max Units

TAOperating ambient temperature –40 25.00 85 °C

TJOperating junction temperature –40 – 100 °C

TJA Package θJA (24-pin QFN) – 38.01 – °C/Watt

TJA Package θJA (16-pin QFN) – 49.6 – °C/Watt

TJA Package θJA (16-pin SOIC) – 142.14 – °C/Watt

TJA Package θJA (8-pin SOIC) – 197.8 – °C/Watt

Table 28. Solder Reflow Peak Temperature

Package Maximum Peak

Temperature Maximum Time at Peak Temperature

All 260 °C 30 seconds

Table 29. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020

Package MSL

All MSL 3

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PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 23 of 30

Package Outline Drawings

Figure 9. 24-pin QFN EPAD (Sawn) Package Outline

The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.

If not connected to ground, it should be electrically floating and not connected to any other signal.

Note

12. Dimensions of the QFN package drawings are in millimeters.

001-13937 *E

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PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 24 of 30

Figure 10. 16-pin QFN Package EPAD (Sawn)

Figure 11. 16-pin (150-mil) SOIC Package Outline

001-87187 **

Note

13. Dimensions of the QFN package drawings are in inches [millimeters].

51-85068 *E

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PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 25 of 30

Figure 12. 8-pin (150-mil) SOIC Package Outline

51-85066 *F

PERFORM

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 26 of 30

Acronyms

Table 30. Acronyms Used in this Document

Acronym Description

abus analog local bus

ADC analog-to-digital converter

AG analog global

AHB AMBA (advanced microcontroller bus archi-

tecture) high-performance bus, an ARM data

transfer bus

ALU arithmetic logic unit

AMUXBUS analog multiplexer bus

API application programming interface

APSR application program status register

ARM®advanced RISC machine, a CPU architecture

ATM automatic thump mode

BW bandwidth

CAN Controller Area Network, a communications

protocol

CMRR common-mode rejection ratio

CPU central processing unit

CRC cyclic redundancy check, an error-checking

protocol

DAC digital-to-analog converter, see also IDAC, VDAC

DFB digital filter block

DIO digital input/output, GPIO with only digital

capabilities, no analog. See GPIO.

DMIPS Dhrystone million instructions per second

DMA direct memory access, see also TD

DNL differential nonlinearity, see also INL

DNU do not use

DR port write data registers

DSI digital system interconnect

DWT data watchpoint and trace

ECC error correcting code

ECO external crystal oscillator

EEPROM electrically erasable programmable read-only

memory

EMI electromagnetic interference

EMIF external memory interface

EOC end of conversion

EOF end of frame

EPSR execution program status register

ESD electrostatic discharge

ETM embedded trace macrocell

FIR finite impulse response, see also IIR

FPB flash patch and breakpoint

FS full-speed

GPIO general-purpose input/output, applies to a PSoC

HVI high-voltage interrupt, see also LVI, LVD

IC integrated circuit

IDAC current DAC, see also DAC, VDAC

IDE integrated development environment

I2C, or IIC Inter-Integrated Circuit, a communications

protocol

IIR infinite impulse response, see also FIR

ILO internal low-speed oscillator, see also IMO

IMO internal main oscillator, see also ILO

INL integral nonlinearity, see also DNL

I/O input/output, see also GPIO, DIO, SIO, USBIO

IPOR initial power-on reset

IPSR interrupt program status register

IRQ interrupt request

ITM instrumentation trace macrocell

LCD liquid crystal display

LIN Local Interconnect Network, a communications

protocol.

LR link register

LUT lookup table

LVD low-voltage detect, see also LVI

LVI low-voltage interrupt, see also HVI

LVTTL low-voltage transistor-transistor logic

MAC multiply-accumulate

MCU microcontroller unit

MISO master-in slave-out

NC no connect

NMI nonmaskable interrupt

NRZ non-return-to-zero

NVIC nested vectored interrupt controller

NVL nonvolatile latch, see also WOL

opamp operational amplifier

PAL programmable array logic, see also PLD

Table 30. Acronyms Used in this Document (continued)

Acronym Description

EYPREss PERFORM

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 27 of 30

PC program counter

PCB printed circuit board

PGA programmable gain amplifier

PHUB peripheral hub

PHY physical layer

PICU port interrupt control unit

PLA programmable logic array

PLD programmable logic device, see also PAL

PLL phase-locked loop

PMDD package material declaration data sheet

POR power-on reset

PRES precise power-on reset

PRS pseudo random sequence

PS port read data register

PSoC®Programmable System-on-Chip™

PSRR power supply rejection ratio

PWM pulse-width modulator

RAM random-access memory

RISC reduced-instruction-set computing

RMS root-mean-square

RTC real-time clock

RTL register transfer language

RTR remote transmission request

RX receive

SAR successive approximation register

SC/CT switched capacitor/continuous time

SCL I2C serial clock

SDA I2C serial data

S/H sample and hold

SINAD signal to noise and distortion ratio

SIO special input/output, GPIO with advanced

features. See GPIO.

SOC start of conversion

SOF start of frame

SPI Serial Peripheral Interface, a communications

protocol

SR slew rate

SRAM static random access memory

SRES software reset

SWD serial wire debug, a test protocol

Table 30. Acronyms Used in this Document (continued)

Acronym Description

SWV single-wire viewer

TD transaction descriptor, see also DMA

THD total harmonic distortion

TIA transimpedance amplifier

TRM technical reference manual

TTL transistor-transistor logic

TX transmit

UART Universal Asynchronous Transmitter Receiver, a

communications protocol

UDB universal digital block

USB Universal Serial Bus

USBIO USB input/output, PSoC pins used to connect to

a USB port

VDAC voltage DAC, see also DAC, IDAC

WDT watchdog timer

WOL write once latch, see also NVL

WRES watchdog timer reset

XRES external reset I/O pin

XTAL crystal

Table 30. Acronyms Used in this Document (continued)

Acronym Description

EYPREss PERIORM

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 28 of 30

Document Conventions

Units of Measure

Table 31. Units of Measure

Symbol Unit of Measure

°C degrees Celsius

dB decibel

fF femto farad

Hz hertz

KB 1024 bytes

kbps kilobits per second

Khr kilohour

kHz kilohertz

kΩkilo ohm

ksps kilosamples per second

LSB least significant bit

Mbps megabits per second

MHz megahertz

MΩmega-ohm

Msps megasamples per second

µA microampere

µF microfarad

µH microhenry

µs microsecond

µV microvolt

µW microwatt

mA milliampere

ms millisecond

mV millivolt

nA nanoampere

ns nanosecond

nV nanovolt

Ωohm

pF picofarad

ppm parts per million

ps picosecond

s second

sps samples per second

sqrtHz square root of hertz

Vvolt

-5 ,5}: _=_==,=“‘ CYPRESS PERfORM F306”

PSoC® 4: PSoC 4000 Family

Datasheet

Document Number: 001-89638 Rev. *B Page 29 of 30

Revision History.

Description Title: PSoC® 4: PSoC 4000 Family Datasheet Programmable System-on-Chip (PSoC®)

Document Number: 001-89638

Revision ECN Orig. of

Change Submission

Date Description of Change

*B 4348760 WKA 04/16/2014 New PSoC 4000 Datasheet.

‘3’ «a! I CYPRESS VERFORM

Document Number: 001-89638 Rev. *B Revised April 16, 2014 Page 30 of 30

All products and company names mentioned in this document may be the trademarks of their respective holders.

PSoC® 4: PSoC 4000 Family

Datasheet

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