[VI/JXI/VI
MAXI/VI
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For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
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General Description
The MAX5102 parallel-input, voltage-output, dual 8-bit
digital-to-analog converter (DAC) operates from a single
+2.7V to +5.5V supply and comes in a space-saving
16-pin TSSOP package. Internal precision buffers
swing Rail-to-Rail®, and the reference input range
includes both ground and the positive rail. Both DACs
share a common reference input.
The MAX5102 has separate input latches for each of its
DACs. Data is transferred to the input latches from a
common 8-bit input port. The DACs are individually
selected through address input A0 and are updated by
bringing WR low.
The MAX5102 features a shutdown mode that reduces
current to 1nA, as well as a power-on reset mode that
resets all registers to code 00 hex on power-up.
Applications
Digital Gain and Offset Adjustment
Programmable Attenuators
Portable Instruments
Power-Amp Bias Control
Features
♦+2.7V to +5.5V Single-Supply Operation
♦Ultra-Low Supply Current
0.2mA while Operating
1nA in Shutdown Mode
♦Ultra-Small 16-Pin TSSOP Package
♦Ground to VDD Reference Input Range
♦Output Buffer Amplifiers Swing Rail-to-Rail
♦Power-On Reset Sets All Registers to Zero
MAX5102
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
________________________________________________________________ Maxim Integrated Products 1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDD OUTA
OUTB
GND
A0
D0
D1
D2
D3
TOP VIEW
MAX5102
TSSOP
REF
SHDN
D6
WR
D7
D5
D4
19-1565; Rev 0; 10/99
PART
MAX5102AEUE
MAX5102BEUE -40°C to +85°C
-40°C to +85°C
TEMP. RANGE PIN-PACKAGE
16 TSSOP
16 TSSOP
Pin Configuration
Ordering Information
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
INL
(LSB)
±1
±2
OUTA
OUTB
MAX5102
DAC A
DAC B
INPUT
LATCH A
INPUT
LATCH B
CONTROL
LOGIC
SHDNREF
A0
WR
D0–D7
Functional Diagram
[MAXI/VI
Code = FF hex
MAX5102
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = VREF = +2.7V to +5.5V, GND = 0V, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at
VDD = VREF = +3V and TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
D_, A0, WR, SHDN to GND ......................................-0.3V to +6V
REF to GND................................................-0.3V to (VDD + 0.3V)
OUT_ to GND ...........................................................-0.3V to VDD
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (TA= +70°C)
16-Pin TSSOP (derate 5.7mW/°C above +70°C) .......457mW
Operating Temperature Range
MAX5102_EUE ..............................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
VIN = VDD or GND
MAX5102A
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
RL= ∞
VDD = 2.7V to 3.6V,
VREF = 2.5V
Code = F0 hex
Code = F0 hex
Code = 00 hex
MAX5102B
Guaranteed monotonic
Code = 00 hex
Code = 00 hex, VDD = 2.7V to 5.5V
CONDITIONS
µA
±1.0
IIN
Input Current
V
0.8
VIL
Input Low Voltage
3V
2
VIH
Input High Voltage
V
0V
REF
Output Voltage Range
pF
15
Input Capacitance
kΩ
320 460 600
Input Resistance
V
0V
DD
Input Voltage Range
1
LSB
±1
INLIntegral Nonlinearity (Note 1)
Bits
8
Resolution
LSB
1
Power-Supply Rejection
LSB/°C
±0.001
Gain-Error Temperature
Coefficient
%
±1
Gain Error (Note 2)
µV/°C
±10
Zero-Code Temperature
Coefficient
±2
LSB
±1
DNLDifferential Nonlinearity (Note 1)
mV
±20
ZCEZero-Code Error
mV
10
Zero-Code-Error Supply
Rejection
UNITSMIN TYP MAXSYMBOLPARAMETER
pF
10
CIN
Input Capacitance
STATIC ACCURACY
REFERENCE INPUT
DAC OUTPUTS
DIGITAL INPUTS
Code = FF hex
VDD = 4.5V to 5.5V,
VREF = 4.096V
[MAXI/VI
MAX5102
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
_______________________________________________________________________________________ 3
Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.
Note 2: Gain error is: [100 (VF0,meas - ZCE - VF0,ideal) / VREF]. Where VF0,meas is the DAC output voltage with input code F0 hex,
and VF0,ideal is the ideal DAC output voltage with input code F0 hex (i.e., VREF ·240 / 256).
Note 3: Output settling time is measured from the 50% point of the falling edge of WR to ±1/2LSB of VOUT’s final value.
Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any
other DAC output. The measured channel has a fixed code of 80 hex.
Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight
data inputs with WR at VDD.
Note 6: RL= ∞, digital inputs at GND or VDD.
Note 7: Timing measurement reference level is (VIH + VIL) / 2.
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VREF = +2.7V to +5.5V, GND = 0V, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at
VDD = VREF = +3V and TA= +25°C.)
60
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
From code 00 to code F0 hex
REF = 0.5Vp-p, VREF(DC) = 1.5V,
VDD = 3V, -3dB bandwidth
To 1/2LSB, from code 00 to code F0 hex
Code 00 to code FF hex
Code 00 to code FF hex
IDD < 5µA
Code 80 hex to code 7F hex
To ±1/2LSB of final value of VOUT
ns
20
tWR
WR Pulse Width
ns
0
tDH
Data to WR Hold
ns
25
tDS
Data to WR Setup
ns
0
tAH
Address to WR Hold
ns
5
tAS
Address to WR Setup
µA
0.001 1
Shutdown Current
µA
190 360
IDD
Supply Current (Note 6)
V
2.7 5.5
VDD
Power-Supply Voltage
µs
20
tSDN
Time to Shutdown
µs
13
tSDR
Shutdown Recovery Time
V/µs
0.6
Output Voltage Slew Rate
µVRMS
60
Wideband Amplifier Noise
kHz
650
Multiplying Bandwidth
70
µs
6
Output Settling Time (Note 3)
nVs
500
Channel-to-Channel Isolation
(Note 4)
nVs
0.5
Digital Feedthrough (Note 5)
nVs
90
Digital-to-Analog Glitch Impulse
REF = 2.5Vp-p at 1kHz, VREF(DC) = 1.5V,
VDD = 3V, code FF hex
Signal-to-Noise plus Distortion
Ratio SINAD dB
REF = 2.5Vp-p at 10kHz, VREF(DC) = 1.5V,
VDD = 3V, code FF hex
DYNAMIC PERFORMANCE
POWER SUPPLIES
DIGITAL TIMING (Figure 1) (Note 7)
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[VI/JXIIVI
MAX5102
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD = VREF = +3V, RL= 10kΩ, CL= 100pF, code = FF hex, TA = +25°C, unless otherwise noted.)
0
0.4
0.2
0.8
0.6
1.0
1.2
0426810
DAC ZERO-CODE OUTPUT VOLTAGE
vs. SINK CURRENT
MAX5102 toc01
SINK CURRENT (mA)
VOUT (V)
VDD = VREF = 3V
VDD = VREF = 5V
0
2
1
4
3
5
6
0426810
DAC FULL-SCALE OUTPUT VOLTAGE
vs. SOURCE CURRENT
MAX5102 toc02
SOURCE CURRENT (mA)
VOUT (V)
VDD = VREF = 3V
VDD = VREF = 5V
100
130
120
110
150
140
190
180
170
160
200
-40 -20 0 20 40 60 80 100
SUPPLY CURRENT vs. TEMPERATURE
MAX5102 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
1 DAC AT CODE 00 OR F0
1 DAC AT CODE 00 (RL = ∞)
VDD = 5V; CODE = F0 HEX
VDD = 5V; CODE = 00
VDD = 3V; CODE = F0 HEX
VDD = 3V; CODE = 00
VDD = 3.0V
0
60
40
20
80
100
120
140
160
180
200
0 1.00.5 1.5 2.0 2.5 3.0
SUPPLY CURRENT vs.
REFERENCE VOLTAGE
MAX5102 toc04
REFERENCE VOLTAGE (V)
SUPPLY CURRENT (µA)
1 DAC AT CODE 00 OR F0
1 DAC AT CODE 00 (RL = ∞)
CODE = F0 HEX
CODE = 00 HEX
VDD = 3.0V
0
40
20
80
60
120
100
140
180
160
200
0 1.0 1.5 2.00.5 2.5 3.0 3.5 4.5.4.0 5.0
SUPPLY CURRENT vs.
REFERENCE VOLTAGE
MAX5102 toc05
REFERENCE VOLTAGE (V)
SUPPLY CURRENT (µA)
VDD = 5.0V
1 DAC AT CODE 00 OR F0
1 DAC AT CODE 00. (RL = ∞)
CODE = F0 HEX
CODE = 00 HEX
-90
-70
-80
-40
-50
-60
-10
-20
-30
0
0 1.00.5 1.5 2.0 2.5
MAX5102 toc06
REFERENCE AMPLITUDE (Vp-p)
THD + NOISE (dB)
DAC CODE = FF HEX
VREF = SINE WAVE CENTERED AT 1.5V
80kHz FILTER
20kHz REF SIGNAL
10kHz REF SIGNAL
1kHz REF SIGNAL
TOTAL HARMONIC DISTORTION
PLUS NOISE AT DAC OUTPUT
vs. REFERENCE AMPLITUDE
ADDRESS VALID
DATA VALID
tAS tWR
tDS- tDH-
tAH-
ADDRESS
DATA
WR
Figure 1. Timing Diagram
:nrm mm mmv
[MAXI/VI
MAX5102
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
_______________________________________________________________________________________ 5
-80
-60
-70
-50
-20
-10
-30
-40
0
1 10 100
TOTAL HARMONIC DISTORTION
PLUS NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
MAX5102 toc07
FREQUENCY (kHz)
THD + NOISE (dB)
DAC CODE = FF HEX
VREF = SINE WAVE CENTERED AT 1.5V
1kHz FREQUENCY
500kHz FILTER
REF = 1Vp-p
REF = 2Vp-p
REF = 0.5Vp-p
0
-90
0.01 1010.1
REFERENCE INPUT
FREQUENCY RESPONSE
-60
-80
-20
-40
10
-50
-70
-10
-30
MAX5100 toc08
FREQUENCY (MHz)
OUTPUT AMPLITUDE (dB)
CODE = FF HEX REF IS IVp-p SIGNAL
VREF = 1.5V
2
1
WORST-CASE 1LSB DIGITAL STEP CHANGE
(NEGATIVE)
MAX55102 toc09
2µs/div
CH1 = WR, 1V/div, CH2 = VOUTA, 50mV/div, AC-COUPLED
DAC CODE FROM 80 TO 7F HEX
2
1
WORST-CASE 1LSB DIGITAL STEP CHANGE
(POSITIVE)
MAX55102 toc10
1µs/div
CH1 = WR, 1V/div, CH2 = VOUTA, 50mV/div, AC-COUPLED
DAC CODE FROM 7F TO 80 HEX
2
1
DIGITAL FEEDTHROUGH GLITCH IMPULSE
(0 TO 1 DIGITAL TRANSITION)
MAX55102 toc11
20ns/div
CH1 = D7, 2V/div, CH2 = VOUTA, 1mV/div
0 TO 1 DIGITAL TRANSITION ON
ALL DATA BITS (WITH WR HIGH)
2
1
DIGITAL FEEDTHROUGH GLITCH IMPULSE
(1 TO 0 DIGITAL TRANSITION)
MAX55102 toc12
20ns/div
1 TO 0 DIGITAL TRANSITION ON
ALL DATA BITS (WITH WR HIGH)
CH1 = D7, 2V/div, CH2 = VOUTA, 1mV/div
2
1
POSITIVE SETTLING TIME
MAX55102 toc13
1µs/div
CH1 = WR = 2V/div, CH2 = VOUTA = 2V/div
DAC CODE FROM 10 TO F0 HEX
2
1
NEGATIVE SETTLING TIME
MAX55102 toc14
1µs/div
CH1 = WR, 2V/div, CH2 = VOUTA, 2V/div
DAC CODE FROM F0 TO 10 HEX
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0 32 64 96 128 160 192 224 256
INTEGRAL AND DIFFERENTIAL
NONLINEARITY vs. DIGITAL CODE
MAX5102 toc15
DIGITAL CODE
INL/DNL (LSB)
RL = ∞
DNL
INL
Typical Operating Characteristics (continued)
(VDD = VREF = +3V, RL= 10kΩ, CL= 100pF, code = FF hex, TA = +25°C, unless otherwise noted.)
[VI/IXIIVI
MAX5102
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
6 _______________________________________________________________________________________
Pin Description
DAC A Voltage OutputOUTA16
Data InputsD7–D05–12
DAC Address Select BitA013
GroundGND14
DAC B Voltage OutputOUTB15
Write Input (active low). Use WR to load data into the DAC input latch selected by A0.WR
4
Shutdown. Connect SHDN to GND for normal operation.SHDN3
PIN
Reference Voltage Input REF2
Positive Supply Voltage. Bypass VDD to GND using a 0.1µF capacitor.VDD
1
FUNCTIONNAME
Detailed Description
Digital-to-Analog Section
The MAX5102 uses a matrix decoding architecture for the
DACs. The external reference voltage is divided down by
a resistor string placed in a matrix fashion. Row and col-
umn decoders select the appropriate tab from the resistor
string to provide the needed analog voltages. The resistor
network converts the 8-bit digital input into an equivalent
analog output voltage in proportion to the applied refer-
ence voltage input. The resistor string presents a code-
independent input impedance to the reference and
guarantees a monotonic output.
These devices can be used in multiplying applications.
Their voltages are buffered by rail-to-rail op amps con-
nected in a follower configuration to provide a rail-to-rail
output (see Functional Diagram).
Low-Power Shutdown Mode
The MAX5102 features a shutdown mode that reduces
current consumption to 1nA. A high voltage on the
SHDN pin shuts down the DACs and the output ampli-
fiers. In shutdown mode, the output amplifiers enter a
high-impedance state. When bringing the device out of
shutdown, allow 13µs for the output to stabilize.
Output Buffer Amplifiers
The DAC outputs are internally buffered by precision
amplifiers with a typical slew rate of 0.6V/µs. The typical
settling time to ±1/2LSB at the output is 6µs when
loaded with 10kΩin parallel with 100pF.
Reference Input
The MAX5102 provides a code-independent input
impedance on the REF input. Input impedance is typi-
cally 460kΩin parallel with 15pF, and the reference
input voltage range is 0 to VDD. The reference input
accepts positive DC signals, as well as AC signals with
peak values between 0 and VDD. The voltage at REF
sets the full-scale output voltage for the DAC. The out-
put voltage (VOUT) for any DAC is represented by a
digitally programmable voltage source as follows:
VOUT = (NB·VREF) / 256
where NBis the numeric value of the DAC binary input
code.
Digital Inputs and Interface Logic
In the MAX5102, address line A0 selects the DAC that
receives data from D0–D7, as shown in Table 1. When
WR is low, the addressed DAC’s input latch is transpar-
ent. Data is latched when WR is high. The DAC outputs
(OUTA, OUTB) represent the data held in the two 8-bit
WR
H
L
LATCH STATE
Input data latched
L
X
A0
DAC A input latch transparent
L H DAC B input latch transparent
Table 1. MAX5102 Addressing Table
(partial list)
H = High state, L = Low state, X = Don’t care
[VI/JXIIVI
input latches. To avoid output glitches in the MAX5102,
ensure that data is valid before WR goes low. When the
device powers up (i.e., VDD ramps up), all latches are
internally preset with code 00 hex.
Applications Information
External Reference
The reference source resistance must be considerably
less than the reference input resistance. To keep within
1LSB error in an 8-bit system, RSmust be less than
RREF/256. Hence, maintain a value of RS< 1kΩto
ensure 8-bit accuracy. If VREF is DC only, bypass REF
to GND with a 0.1µF capacitor. Values greater than this
improve noise rejection.
Power Sequencing
The voltage applied to REF should not exceed VDD at
any time. If proper power sequencing is not possible,
connect an external Schottky diode between REF and
VDD to ensure compliance with the absolute maximum
ratings. Do not apply signals to the digital inputs before
the device is fully powered up.
Power-Supply Bypassing and
Ground Management
Digital or AC transient signals on GND can create noise
at the analog output. Return GND to the highest-quality
ground available. Bypass VDD with a 0.1µF capacitor,
located as close to VDD and GND as possible.
Careful PC board ground layout minimizes crosstalk
between the DAC outputs and digital inputs.
Chip Information
TRANSISTOR COUNT: 6848
MAX5102
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
_______________________________________________________________________________________ 7
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MAXIM
MAX5102
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
TSSOP.EPS
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