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INSTRUMENTS
Boomer®Aumo Power Ampmier Series
GND—t 25 —mgm ow
Mux Contrm— z 27 —an
Mute— 3 25 —ngM Du"
VJD— 4 25 —NC
DC Vm— S 24 —Shutduwn
GND— 6 23 —GND
M \n z— 7 22 —Bypass
Rxgm M 2— E Z1—HP Sense
Right Lme OM— 3 20 —GND
mnum—m ‘s—vm
GND— 1‘ ‘8 — NC
LeH In ‘— V2 ‘7 —LEM OLA"
Len Lme om— u ‘5 —v]D
GNU—1t ‘5—LEM BLAH
OBSOLETE
LM4849
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SNAS222 –MAY 2004
LM4849 Stereo 2W Audio Power Amplifiers
with DC Volume Control and Input Mux
Check for Samples: LM4849
1FEATURES DESCRIPTION
The LM4849 is a monolithic integrated circuit that
23• DC Volume Control Interface provides DC volume control, and stereo bridged
• Input Mux audio power amplifiers capable of producing 2W into
• Stereo Switchable Bridged/Single-Ended 4Ωwith less than 1.0% THD+N, or 2.2W into 3Ωwith
Power Amplifiers less than 1.0% THD+N.
• “Click and Pop” Suppression Circuitry Boomer™ audio integrated circuits were designed
specifically to provide high quality audio while
• Thermal Shutdown Protection Circuitry requiring a minimum amount of external components.
The LM4849 incorporates a DC volume control,
APPLICATIONS stereo bridged audio power amplifiers, and an input
• Portable and Desktop Computers mux making it optimally suited for multimedia
• Multimedia, LCD Monitors/TV monitors, portable radios, desktop, and portable
computer applications.
• Portable Radios, PDAs, and Portable TVs
The LM4849 features an externally controlled, low-
KEY SPECIFICATIONS power consumption shutdown mode, and both a
power amplifier and headphone mute for maximum
• POat 1% THD+N system flexibility and performance.
– Into 3Ω, 2.2W (Typ)
– Into 4Ω, 2.0W (Typ)
– Into 8Ω, 1.1W (Typ)
• Single-Ended Mode - THD+N at 85mW into
32Ω, 1.0% (Typ)
• Shutdown Current, 0.2µA (Typ)
Connection Diagram
Figure 1. HTSSOP Package
Top View
See Package Number PWP for HTSSOP
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Boomer is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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INSTRUMENTS
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage 6.0V
Storage Temperature -65°C to +150°C
Input Voltage −0.3V to VDD +0.3V
Power Dissipation Internally limited
ESD Susceptibility(3) 2500V
ESD Susceptibility(4) 250V
Junction Temperature 150°C
Vapor Phase (60 sec.) 215°C
Soldering Information Infrared (15 sec.) 220°C
θJA (typ)—PWP (exposed DAP)(5) 41°C/W
θJA (typ)—PWP (exposed DAP)(6) 54°C/W
θJA (typ)—PWP (exposed DAP)(7) 59°C/W
θJA (typ)—PWP (exposed DAP)(8) 93°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) If Military/Aerospace specified devices are required, please contact the Texas instruments Sales Office/Distributors for availability and
specifications.
(3) Human body model, 100pF discharged through a 1.5kΩresistor.
(4) Machine Model, 220pF–240pF discharged through all pins.
(5) The θJA given is for an MXA28A package whose exposed-DAP is soldered to an exposed 2in 2piece of 1 ounce printed circuit board
copper.
(6) The θJA given is for an MXA28A package whose exposed-DAP is soldered to a 2in2piece of 1 ounce printed circuit board copper on a
bottom side layer through 21 8mil vias.
(7) The θJA given is for an MXA28A package whose exposed-DAP is soldered to an exposed 1in2piece of 1 ounce printed circuit board
copper.
(8) The θJA given is for an MXA28A package whose exposed-DAP is not soldered to any copper.
Operating Ratings
Temperature Range −40°C ≤TA ≤85°C
TMIN ≤TA≤TMAX
Supply Voltage 2.7V≤VDD ≤5.5V
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Electrical Characteristics for Entire IC(1)(2)
The following specifications apply for VDD = 5V and TA= 25°C unless otherwise noted.
LM4849 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)
VDD Supply Voltage 2.7 V (min)
5.5 V (max)
IDD Quiescent Power Supply Current VIN = 0V, IO= 0A 15 30 mA (max)
ISD Shutdown Current Vshutdown = VDD 0.7 2.0 μA (max)
VIH VIN High on all Logic Inputs 0.8 x VDD V (min)
VIL VIN Low on all Logic Inputs 0.2 x VDD V (max)
(1) All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 49.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Limits are ensured to Texas Instruments'
AOQL (Average Outgoing Quality Level).
Electrical Characteristics for Volume Attenuators(1)(2)
The following specifications apply for VDD = 5V and TA= 25°C unless otherwise noted.
LM4849 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)
CRANGE Attenuator Range Gain with VDCVol = 5.0V, No Load ±0.75 dB (max)
CRANGE Attenuator Range Attenuation with VDCVol = 0V (BM & SE) -75 dB (min)
AMMute Attenuation Vmute = 5V, Bridged Mode (BM) -78 dB (min)
Vmute = 5V, Single-Ended Mode (SE) -78 dB (min)
(1) All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 49.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Limits are ensured to Texas Instruments'
AOQL (Average Outgoing Quality Level).
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Electrical Characteristics for Single-Ended Mode Operation
(1)(2)
The following specifications apply for VDD = 5V and TA= 25°C unless otherwise noted.
LM4849 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)
POOutput Power THD+N = 1.0%; f = 1kHz; RL= 32Ω85 mW
THD+N = 10%; f = 1 kHz; RL= 32Ω95 mW
THD+N Total Harmonic Distortion+Noise VOUT = 1VRMS, f=1kHz, RL= 10kΩ, AVD 0.065 %
= 1
PSRR Power Supply Rejection Ratio CB= 1.0 μF, f =120 Hz, VRIPPLE = 200 58 dB
mVrms
SNR Signal to Noise Ratio POUT =75 mW, R L= 32Ω, A-Wtd Filter 102 dB
Xtalk Channel Separation f=1kHz, CB= 1.0 μF 65 dB
(1) All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 49.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Limits are ensured to Texas Instruments'
AOQL (Average Outgoing Quality Level).
Electrical Characteristics for Bridged Mode Operation(1) (2)
The following specifications apply for VDD = 5V and TA= 25°C unless otherwise noted.
LM4849 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)
VOS Output Offset Voltage VIN = 0V, No Load ±50 mV (max)
POOutput Power THD + N = 1.0%; f=1kHz; RL= 3Ω(5) 2.2 W
THD + N = 1.0%; f=1kHz; RL= 4Ω(6) 2 W
THD = 1.5% (max);f = 1 kHz; 1.1 1.0 W (min)
RL= 8Ω
THD+N = 10%;f = 1 kHz; RL= 8Ω1.5 W
THD+N Total Harmonic Distortion+Noise PO= 1W, f = 1kHz, 0.2 %
RL= 8Ω, AVD = 2
PO= 340 mW, RL= 32Ω1.0 %
PSRR Power Supply Rejection Ratio CB= 1.0 µF, f = 120 Hz, 74 dB
VRIPPLE = 200 mVrms; RL= 8Ω
SNR Signal to Noise Ratio VDD = 5V, POUT = 1.1W, RL= 8Ω, A- 93 dB
Wtd Filter
Xtalk Channel Separation f=1kHz, CB= 1.0 μF 70 dB
(1) All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 49.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Limits are ensured to Texas Instruments'
AOQL (Average Outgoing Quality Level).
(5) When driving 3Ωloads from a 5V supply the LM4849MH exposed DAP must be soldered to the circuit board and forced-air cooled.
(6) When driving 4Ωloads from a 5V supply the LM4849MH exposed DAP must be soldered to the circuit board.
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L
L,
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LM4849
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Typical Application
Figure 2. Typical Application Circuit (MH pinout)
Truth Table for Logic Inputs(7)
Table 1. Truth Table
Single-Ended
Mute Mux Control HP Sense Inputs Selected Bridged Output Output
0 0 0 Left In 1, Right In 1 Vol. Adjustable -
0 0 1 Left In 1, Right In 1 Muted Vol. Adjustable
0 1 0 Left In 2, Right In 2 Vol. Adjustable -
0 1 1 Left In 2, Right In 2 Muted Vol. Adjustable
1 X X - Muted Muted
(7) If system beep is detected on the Beep in pin (pin 11) and beep is fed to inputs, the system beep will be passed through the bridged
amplifier regardless of the logic of the Mute, HP sense, or DC Volume Control pins.
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10
vDD : 5v
RL = so
Bridged Load
z
+
n
I
’— 0 1
o 010
100m I 3
Oumut Power (w
10
VDD : 5v
RL = 4n
Erldged Load 1: 20km
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E
+
D
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team 1 3
Output Power (W)
VD
vDD = 5v
Pa = M
R : an
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,; 1 Bridge Load
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Frequency (Hz)
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E,
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RL : 15m
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Q AW : 11)
0|
AVE: 2
0,010
20 mo Ik 10k 20k
Frequency (Hz)
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LM4849
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Typical Performance Characteristics
LM4849MH LM4849MH
THD+N vs Output Power THD+N vs Frequency
Figure 3. Figure 4.
LM4849MH LM4849MH
THD+N vs Output Power THD+N vs Frequency
Figure 5. Figure 6.
THD+N vs Frequency THD+N vs Frequency
Figure 7. Figure 8.
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INSTRUMENTS
VD VD
Vuu : 5v vDD : 5v
251: mW PD 75 mW
Rt : an Rt : 3m
3."ng mm smgVe mm
A I A I
5 5
— n I — n I
0,0VD 0,0VD
20 I00 Ik (OH NH 20 I00 Ik (OH NH
Frequency (Hz) Frequency (Hz)
VD VD
5V
VRMS
Rt : V m
Single Ended
A I A I
5 5
— n I — n I
BrVdgsd Lam
0,0VD 0,0VD
20 I00 Ik (OH NH 20 I00 Ik (OH NH
Frequency (Hz) Frequency (Hz)
VD VD
van : 5v
P0 - (50 mW
RL : Vsn
Endgzd Lnad
A ‘ A ‘
5 5
k D I k D I
van : 3v
P0 250 m
K : an
Endged Load
(mm (mm
70 we Ik Wk 20k
Frequency (Hz)
70 we Ik Wk 20k
Frequency (Hz)
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Typical Performance Characteristics (continued)
THD+N vs Frequency THD+N vs Frequency
Figure 9. Figure 10.
THD+N vs Frequency THD+N vs Frequency
Figure 11. Figure 12.
THD+N vs Frequency THD+N vs Frequency
Figure 13. Figure 14.
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INSTRUMENTS
.)
mum (
In
vDD = 3v
Pa = 20 MW
RL : 5211
my: Endzd
I
.)
k
g Av : ID
a I ' n I
SmgIe Ended
(mm (mm
20 Inc Ik (Wick 20 Inc Ik (amok
Frequency (Hz) Frequency (Hz)
In In
VDD : 5v
RL : an
Smgle [ma Bndged Load
I A ‘
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V 2
_ 5
Av 7 In E
n I AV : I 0 ‘
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Frequency (Hz)
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RL : Ien
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A 1
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a
E
0‘ : 20m
I 1kHz
o 010
(Om o I 1 mm M o 5
Cum“! POWS' (WI
Output Fuwer (W)
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Typical Performance Characteristics (continued)
THD+N vs Frequency THD+N vs Frequency
Figure 15. Figure 16.
THD+N vs Frequency THD+N vs Output Power
Figure 17. Figure 18.
THD+N vs Output Power THD+N vs Output Power
Figure 19. Figure 20.
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INSTRUMENTS
V 0m 0 1
Output Power (w)
vDD = 3v
RL = m
Bmgea Load
= 20kHz
10m 01
Output Power (W)
vDD =av
RL : ‘sn
Bndgsa Load
0: 20kHz
THD+N(%)
0 010
mm 01
output Powev (W)
02
05
u I 1 3
Output Vouage (VRMS)
10
vDD : av
RL = so
Budged Lnad
A 1
32: l: ZUkHz
,
a v: 20H:
’— 01
q = “(Hz
0 010
mm 01 o 8
Guam Power (W)
10
vDD = 3v
co“ 000w
RL = an
Sm eEnded
f= 20kHz
I: 2qu
01
0 010
10m 0 1 0 2
Oulpul Power (w)
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Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
Figure 21. Figure 22.
THD+N vs Output Power THD+N vs Output Power
Figure 23. Figure 24.
THD+N vs Output Power THD+N vs Output Power
Figure 25. Figure 26.
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10
vDD = av
co". : mom/F
HL : 320
- ‘ 5| \e Ended
i 1: 20kHz
2. r: 20km
E
F o ‘ ’\
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VDD : 5v
‘ 5 v: ‘ w:
M : 1
’g‘ ‘15 Erwdgad Lead
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Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
Figure 27. Figure 28.
THD+N vs Output Voltage THD+N vs Output Voltage
Line Out Pins Line Out Pins
Figure 29. Figure 30.
Output Power vs Output Power vs
Load Resistance Load Resistance
Figure 31. Figure 32.
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INSTRUMENTS
moo tn 5V AP
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Typical Performance Characteristics (continued)
Output Power vs Power Supply
Load Resistance Rejection Ratio
Figure 33. Figure 34.
Output Power vs
Dropout Voltage Load Resistance
Figure 35. Figure 36.
Noise Floor Noise Floor
Figure 37. Figure 38.
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n 0.7
"“ 0.5
.2“ 3
A v 0.5
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Typical Performance Characteristics (continued)
Volume Control Power Dissipation vs
Characteristics Output Power
Figure 39. Figure 40.
Power Dissipation vs
Output Power Power Derating Curve
Figure 41. Figure 42.
Output Power
Crosstalk vs Supply voltage
Figure 43. Figure 44.
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m5
Van 5v
« ‘ m
FL 3m Bridged Made
Smg‘z {ma
aw < an="" m="" 0‘25="" u="" o="" 075="" 005="" 4="" m="" mum="" unzs.="" -="" -="" -="" ,="" \="" v‘n="" 7="" 0v="" ‘0‘%="" mum="" mg‘e="" ended="" 0mm="" power="" (w)="" supp‘y="">OBSOLETE
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Typical Performance Characteristics (continued)
Output Power Supply Current
vs Supply Voltage vs Supply Voltage
Figure 45. Figure 46.
LM4849MH
Power Dissipation vs LM4849MH
Output Power Power Derating Curve
Figure 47. Figure 48.
These curves show the thermal dissipation ability of the LM4849MH at different ambient temperatures given these
conditions:
500LFPM + 2in2:The part is soldered to a 2in2, 1 oz. copper plane with 500 linear feet per minute of forced-air flow
across it.
2in2on bottom: The part is soldered to a 2in2, 1oz. copper plane that is on the bottom side of the PC board through
21 8 mil vias.
2in2:The part is soldered to a 2in2, 1oz. copper plane.
1in2:The part is soldered to a 1in2, 1oz. copper plane.
Not Attached: The part is not soldered down and is not forced-air cooled.
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APPLICATION INFORMATION
EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4849's exposed-DAP (die attach paddle) package (MH) provides a low thermal resistance between the
die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the
surrounding PCB copper traces, ground plane and, finally, surrounding air. The result is a low voltage audio
power amplifier that produces 2.1W at ≤1% THD with a 4Ωload. This high power is achieved through careful
consideration of necessary thermal design. Failing to optimize thermal design may compromise the LM4849's
high power performance and activate unwanted, though necessary, thermal shutdown protection.
The MH package must have its exposed DAP soldered to a grounded copper pad on the PCB. The DAP's PCB
copper pad is connected to a large plane of continuous unbroken copper. This plane forms a thermal mass and
heat sink and radiation area. Place the heat sink area on either outside plane in the case of a two-sided PCB, or
on an inner layer of a board with more than two layers. Connect the DAP copper pad to the inner layer or
backside copper heat sink area with 32(4x8) (MH) vias. The via diameter should be 0.012in–0.013in with a
1.27mm pitch. Ensure efficient thermal conductivity by plating-through and solder-filling the vias.
Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and
amplifier share the same PCB layer, a nominal 2.5in2(min) area is necessary for 5V operation with a 4Ωload.
Heatsink areas not placed on the same PCB layer as the LM4849 should be 5in2(min) for the same supply
voltage and load resistance. The last two area recommendations apply for 25°C ambient temperature. Increase
the area to compensate for ambient temperatures above 25°C. In systems using cooling fans, the LM4849MH
can take advantage of forced air cooling. With an air flow rate of 450 linear-feet per minute and a 2.5in2exposed
copper or 5.0in2inner layer copper plane heatsink, the LM4849MH can continuously drive a 3Ωload to full
power. The LM4849's power de-rating curve in the Typical Performance Characteristics shows the maximum
power dissipation versus temperature. Example PCB layouts for the HTSSOP package is shown in the
Demonstration Board Layout section.
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3ΩAND 4Ω
LOADS
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by a 4Ωload from 2.1W to 2.0W. This problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 2, the LM4849 output stage consists of two pairs of operational amplifiers, forming a two-
channel (channel A and channel B) stereo amplifier. (Though the following discusses channel A, it applies
equally to channel B.)
Figure 2 shows that the first amplifier's negative (-) output serves as the second amplifier's input. This results in
both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage of this phase
difference, a load is placed between −OUTA and +OUTA and driven differentially (commonly referred to as
“bridge mode”). This results in a differential gain of
AVD = 2 * (Rf/R i) (1)
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Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-
ended configuration: its differential output doubles the voltage swing across the load. This produces four
times the output power when compared to a single-ended amplifier under the same conditions. This increase in
attainable output power assumes that the amplifier is not current limited or that the output signal is not clipped.
To ensure minimum output signal clipping when choosing an amplifier's closed-loop gain, refer to the AUDIO
POWER AMPLIFIER DESIGN section.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing channel A's and channel B's outputs at half-supply. This eliminates the coupling capacitor that single
supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a single-ended configuration
forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power
dissipation and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. Equation 2
states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and
driving a specified output load.
PDMAX = (VDD)2/(2π2RL) Single-Ended (2)
However, a direct consequence of the increased power delivered to the load by a bridge amplifier is higher
internal power dissipation for the same conditions.
The LM4849 has two operational amplifiers per channel. The maximum internal power dissipation per channel
operating in the bridge mode is four times that of a single-ended amplifier. From Equation 3, assuming a 5V
power supply and a 4Ωload, the maximum single channel power dissipation is 1.27W or 2.54W for stereo
operation.
PDMAX = 4 * (VDD)2/(2π2RL) Bridge Mode (3)
The LM4849's power dissipation is twice that given by Equation 2 or Equation 3 when operating in the single-
ended mode or bridge mode, respectively. Twice the maximum power dissipation point given by Equation 3 must
not exceed the power dissipation given by Equation 4:
PDMAX′= (TJMAX −TA)/θJA (4)
The LM4849's TJMAX = 150°C. In the MH package soldered to a DAP pad that expands to a copper area of 2in2
on a PCB, the LM4849's θJA is 41°C/W. At any given ambient temperature TA, use Equation 4 to find the
maximum internal power dissipation supported by the IC packaging. Rearranging Equation 4 and substituting
PDMAX for PDMAX′results in Equation 5. This equation gives the maximum ambient temperature that still allows
maximum stereo power dissipation without violating the LM4849's maximum junction temperature.
TA= TJMAX – 2*PDMAX θJA (5)
For a typical application with a 5V power supply and an 4Ωload, the maximum ambient temperature that allows
maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 45°C
for the MH package.
TJMAX = PDMAX θJA + TA(6)
Equation 6 gives the maximum junction temperature TJMAX. If the result violates the LM4849's TJMAX of 150°C,
reduce the maximum junction temperature by reducing the power supply voltage or increasing the load
resistance. Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases.
If twice the value given by Equation 3 is greater than that of Equation 4, then decrease the supply voltage,
increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink
can be added to reduce θJA. The heat sink can be created using additional copper area around the package, with
connections to the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks
such as the Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the θJA is the sum
of θJC,θCS, and θSA. (θJC is the junction-to-case thermal impedance, θCS is the case-to-sink thermal impedance,
and θSA is the sink-to-ambient thermal impedance.) Refer to the Typical Performance Characteristics curves for
power dissipation information at lower output power levels.
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POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 10 µF in parallel with a 0.1 µF filter capacitor to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.0 µF tantalum bypass capacitance connected
between the LM4849's supply pins and ground. Do not substitute a ceramic capacitor for the tantalum. Doing so
may cause oscillation. Keep the length of leads and traces that connect capacitors between the LM4849's power
supply pin and ground as short as possible. Connecting a 1µF capacitor, CB, between the BYPASS pin and
ground improves the internal bias voltage's stability and improves the amplifier's PSRR. The PSRR
improvements increase as the bypass pin capacitor value increases. Too large a capacitor, however, increases
turn-on time and can compromise the amplifier's click and pop performance. The selection of bypass capacitor
values, especially CB, depends on desired PSRR requirements, click and pop performance (as explained in the
section, PROPER SELECTION OF EXTERNAL COMPONENTS), system cost, and size constraints.
PROPER SELECTION OF EXTERNAL COMPONENTS
Optimizing the LM4849's performance requires properly selecting external components. Though the LM4849
operates well when using external components with wide tolerances, best performance is achieved by optimizing
component values.
The LM4849 is unity-gain stable, giving a designer maximum design flexibility. The gain should be set to no more
than a given application requires. This allows the amplifier to achieve minimum THD+N and maximum signal-to-
noise ratio. These parameters are compromised as the closed-loop gain increases. However, low gain circuits
demand input signals with greater voltage swings to achieve maximum output power. Fortunately, many signal
sources such as audio CODECs have outputs of 1VRMS (2.83VP-P). Please refer to the AUDIO POWER
AMPLIFIER DESIGN section for more information on selecting the proper gain.
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires a high value input coupling capacitor (0.33µF in Figure 2). A
high value capacitor can be expensive and may compromise space efficiency in portable designs. In many
cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little
improvement by using a large input capacitor.
Besides affecting system cost and size, the input coupling capacitor has an effect on the LM4849's click and pop
performance. When the supply voltage is first applied, a transient (pop) is created as the charge on the input
capacitor changes from zero to a quiescent state. The magnitude of the pop is directly proportional to the input
capacitor's size. Higher value capacitors need more time to reach a quiescent DC voltage (usually VDD/2) when
charged with a fixed current. The amplifier's output charges the input capacitor through the feedback resistors,
(R1, 2, 7, 8). Thus, pops can be minimized by selecting an input capacitor value that is no higher than necessary
to meet the desired −3dB frequency.
As shown in Figure 2, the input resistors (R3, 4, 5, 6) and the input capacitors (CIN = 0.33µF) produce a −6dB
high pass filter cutoff frequency that is found using Equation 7.
(7)
As an example when using a speaker with a low frequency limit of 150Hz, the input coupling capacitor using
Equation 7, is 0.063µF. The 0.33µF input coupling capacitor shown in Figure 2 allows the LM4849 to drive high
efficiency, full range speaker whose response extends below 30Hz.
OPTIMIZING CLICK AND POP REDUCTION PERFORMANCE
The LM4849 contains circuitry that minimizes turn-on and shutdown transients or “clicks and pops”. For this
discussion, turn-on refers to either applying the power supply voltage or when the shutdown mode is deactivated.
While the power supply is ramping to its final value, the LM4849's internal amplifiers are configured as unity gain
buffers. An internal current source changes the voltage of the BYPASS pin in a controlled, linear manner. Ideally,
the input and outputs track the voltage applied to the BYPASS pin. The gain of the internal amplifiers remains
unity until the voltage on the bypass pin reaches 1/2 VDD . As soon as the voltage on the bypass pin is stable,
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the device becomes fully operational. Although the BYPASS pin current cannot be modified, changing the size of
CBypass alters the device's turn-on time and the magnitude of “clicks and pops”. Increasing the value of CBypass
reduces the magnitude of turn-on pops. However, this presents a tradeoff: as the size of CBypass increases, the
turn-on time increases. There is a linear relationship between the size of CBypass and the turn-on time. Here are
some typical turn-on times for various values of CBypass:
CBypass TON
0.01µF 2ms
0.1µF 20ms
0.22µF 44ms
0.47µF 94ms
1.0µF 200ms
RIGHT AND LEFT LINE OUT
Applications such as notebook computers can take advantage of a line output signal to connect to external
devices such as monitors or audio/visual equipment that sends or receives line level signals. The LM4849 has
two outputs which connect to the outputs of the internal input amplifiers that drive the volume control inputs.
These input amplifiers can drive loads of >1kΩ(such as powered speakers) with a rail-to-rail signal. Since the
output signal present on the RIGHT Line Out and LEFT Line Out pins is biased to VDD/2, coupling capacitors
need to be connected in series with the load. Typical values for the coupling capacitors are 0.33µF to 1.0µF. If
polarized coupling capacitors are used, connect their "+" terminals to the respective output pin.
Since the Line Out outputs precede the internal volume control, the signal amplitude will be equal to the input
signal's magnitude and cannot be adjusted. However, the input amplifier's closed-loop gain can be adjusted
using external resistors. These 20K resistors are shown in Figure 2 (R1 - R8 ) and they set each input amplifier's
gain to -1. Use Equation 8 to determine the input and feedback resistor values for a desired gain.
- Av= R2/ R3(8)
Adjusting the input amplifier's gain sets the minimum gain for that channel. Although the single ended outputs of
the Bridge Output Amplifiers can be used to drive line level outputs, it is recommended that the Right & Left Line
Outputs simpler signal path be used for better performance.
STEREO-INPUT MULTIPLEXER (STEREO MUX)
The LM4849 has two stereo inputs. The MUX CONTROL pin controls which stereo input is active. Applying 0V to
the MUX CONTROL pin selects stereo input 1. Applying VDD to the MUX CONTROL pin selects stereo input 2.
MICRO-POWER SHUTDOWN
The voltage applied to the SHUTDOWN pin controls the LM4849's shutdown function. Activate micro-power
shutdown by applying VDD to the SHUTDOWN pin. When active, the LM4849's micro-power shutdown feature
turns off the amplifier's bias circuitry, reducing the supply current. The logic threshold is typically VDD/2. The low
0.7 µA typical shutdown current is achieved by applying a voltage that is as near as VDD as possible, to the
SHUTDOWN pin. A voltage that is less than VDD may increase the shutdown current. The Logic Level Truth
Table shows the logic signal levels that activate and deactivate micro-power shutdown and headphone amplifier
operation.
There are a few ways to control the micro-power shutdown. These include using a single-pole, single-throw
switch, a microprocessor, or a microcontroller. When using a switch, connect an external 10kΩpull-up resistor
between the SHUTDOWN pin and VDD. Connect the switch between the SHUTDOWN pin and ground. Select
normal amplifier operation by closing the switch. Opening the switch connects the SHUTDOWN pin to VDD
through the pull-up resistor, activating micro-power shutdown. The switch and resistor ensures that the
SHUTDOWN pin will not float. This prevents unwanted state changes. In a system with a microprocessor or a
microcontroller, use a digital output to apply the control voltage to the SHUTDOWN pin. Driving the SHUTDOWN
pin with active circuitry eliminates the need for a pull up resistor.
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Table 2. Logic Level Truth Table for SHUTDOWN, HP-IN, and MUX Operation
SHUTDOWN MUX CHANNEL OPERATIONAL MODE
PIN HP-IN PIN SELECT PIN (MUX INPUT CHANNEL #)
Logic Low Logic Low Logic Low Bridged Amplifiers (1)
Logic Low Logic Low Logic High Bridged Amplifiers (2)
Logic Low Logic High Logic Low Single-Ended Amplifiers (1)
Logic Low Logic High Logic High Single-Ended Amplifiers (2)
Logic High X X Micro-Power Shutdown
MUTE FUNCTION
The LM4849 mutes the amplifier and DOCK outputs when VDD is applied to the MUTE pin. Applying 0V to the
MUTE pin returns the LM4849 to normal, unmated operation. Prevent unanticipated mute behavior by connecting
the MUTE pin to VDD or ground. Do not let the mute pin float.
HP SENSE FUNCTION ( Head Phone In )
Applying a voltage between 4V and VDD to the LM4849's HP-IN headphone control pin turns off the amps that
drive the left out "+" and right out "+" pins. This action mutes a bridged-connected load. Quiescent current
consumption is reduced when the IC is in this single-ended mode.
Figure 49 shows the implementation of the LM4849's headphone control function. With no headphones
connected to the headphone jack, the R1-R2 voltage divider sets the voltage applied to the HP Sense pin at
approximately 50mV. This 50mV puts the LM4849 into bridged mode operation. The output coupling capacitor
blocks the amplifier's half supply DC voltage, protecting the headphones. (The HP-IN threshold is set at 4V).
While the LM4849 operates in bridged mode, the DC potential across the load is essentially 0V. Therefore, even
in an ideal situation, the output swing cannot cause a false single-ended trigger. Connecting headphones to the
headphone jack disconnects the headphone jack contact pin from R2 and allows R1 to pull the HP Sense pin up
to VDD through R4. This enables the headphone function, turns off both of the "+" output amplifiers and mutes the
bridged speaker. The amplifier then drives the headphones, whose impedance is in parallel with resistors R2 and
R3. These resistors have negligible effect on the LM4849's output drive capability since the typical impedance of
headphones is 32Ω.
Figure 49 also shows the suggested headphone jack electrical connections. The jack is designed to mate with a
three-wire plug. The plug's tip and ring should each carry one of the two stereo output signals, whereas the
sleeve should carry the ground return. A headphone jack with one control pin contact is sufficient to drive the HP-
IN pin when connecting headphones.
A microprocessor or a switch can replace the headphone jack contact pin. When a microprocessor or switch
applies a voltage greater than 4V to the HP-IN pin, a bridge-connected speaker is muted and the single ended
output amplifiers will drive a pair of headphones.
Figure 49. Headphone Sensing Circuit (MH Pinout)
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DC VOLUME CONTROL
The LM4849 has an internal stereo volume control whose setting is a function of the DC voltage applied to the
DC VOL CONTROL pin.
The LM4849 volume control consists of 31 steps that are individually selected by a variable DC voltage level on
the volume control pin. The range of the steps, controlled by the DC voltage, are from 0dB - 78dB. Each gain
step corresponds to a specific input voltage range, as shown in table 2.
To minimize the effect of noise on the volume control pin, which can affect the selected gain level, hysteresis has
been implemented. The amount of hysteresis corresponds to half of the step width, as shown in Volume Control
Characterization Graph (DS200133-40).
For highest accuracy, the voltage shown in the 'recommended voltage' column of the table is used to select a
desired gain. This recommended voltage is exactly halfway between the two nearest transitions to the next
highest or next lowest gain levels.
The gain levels are 1dB/step from 0dB to -6dB, 2dB/step from -6dB to -36dB, 3dB/step from -36dB to -47dB,
4dB/step from -47db to -51dB, 5dB/step from -51dB to -66dB, and 12dB to the last step at -78dB.
Table 3. VOLUME CONTROL (see Table 2)
Voltage Range (% of VDD) Voltage Range (VDD = 5) Voltage Range (VDD = 3)
Gain (dB) Low High Recommended Low High Recommended Low High Recommended
0 77.5% 100.00% 100.000% 3.875 5.000 5.000 2.325 3.000 3.000
-1 75.0% 78.5% 76.875% 3.750 3.938 3.844 2.250 2.363 2.306
-2 72.5% 76.25% 74.375% 3.625 3.813 3.719 2.175 2.288 2.231
-3 70.0% 73.75% 71.875% 3.500 3.688 3.594 2.100 2.213 2.156
-4 67.5% 71.25% 69.375% 3.375 3.563 3.469 2.025 2.138 2.081
-5 65.0% 68.75% 66.875% 3.250 3.438 3.344 1.950 2.063 2.006
-6 62.5% 66.25% 64.375% 3.125 3.313 3.219 1.875 1.988 1.931
-8 60.0% 63.75% 61.875% 3.000 3.188 3.094 1.800 1.913 1.856
-10 57.5% 61.25% 59.375% 2.875 3.063 2.969 1.725 1.838 1.781
-12 55.0% 58.75% 56.875% 2.750 2.938 2.844 1.650 1.763 1.706
-14 52.5% 56.25% 54.375% 2.625 2.813 2.719 1.575 1.688 1.631
-16 50.0% 53.75% 51.875% 2.500 2.688 2.594 1.500 1.613 1.556
-18 47.5% 51.25% 49.375% 2.375 2.563 2.469 1.425 1.538 1.481
-20 45.0% 48.75% 46.875% 2.250 2.438 2.344 1.350 1.463 1.406
-22 42.5% 46.25% 44.375% 2.125 2.313 2.219 1.275 1.388 1.331
-24 40.0% 43.75% 41.875% 2.000 2.188 2.094 1.200 1.313 1.256
-26 37.5% 41.25% 39.375% 1.875 2.063 1.969 1.125 1.238 1.181
-28 35.0% 38.75% 36.875% 1.750 1.938 1.844 1.050 1.163 1.106
-30 32.5% 36.25% 34.375% 1.625 1.813 1.719 0.975 1.088 1.031
-32 30.0% 33.75% 31.875% 1.500 1.688 1.594 0.900 1.013 0.956
-34 27.5% 31.25% 29.375% 1.375 1.563 1.469 0.825 0.937 0.881
-36 25.0% 28.75% 26.875% 1.250 1.438 1.344 0.750 0.862 0.806
-39 22.5% 26.25% 24.375% 1.125 1.313 1.219 0.675 0.787 0.731
-42 20.0% 23.75% 21.875% 1.000 1.188 1.094 0.600 0.712 0.656
-45 17.5% 21.25% 19.375% 0.875 1.063 0.969 0.525 0.637 0.581
-47 15.0% 18.75% 16.875% 0.750 0.937 0.844 0.450 0.562 0.506
-51 12.5% 16.25% 14.375% 0.625 0.812 0.719 0.375 0.487 0.431
-56 10.0% 13.75% 11.875% 0.500 0.687 0.594 0.300 0.412 0.356
-61 7.5% 11.25% 9.375% 0.375 0.562 0.469 0.225 0.337 0.281
-66 5.0% 8.75% 6.875% 0.250 0.437 0.344 0.150 0.262 0.206
-78 0.0% 6.25% 0.000% 0.000 0.312 0.000 0.000 0.187 0.000
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AUDIO POWER AMPLIFIER DESIGN
Audio Amplifier Design: Driving 1W into an 8ΩLoad
The following are the desired operational parameters:
Power Output 1 WRMS
Load Impedance 8Ω
Input Level 1 VRMS
Input Impedance 20 kΩ
Bandwidth 100 Hz−20 kHz ± 0.25 dB
The design begins by specifying the minimum supply voltage necessary to obtain the specified output power.
One way to find the minimum supply voltage is to use the Output Power vs Supply Voltage curve in the Typical
Performance Characteristics section. Another way, using Equation 9, is to calculate the peak output voltage
necessary to achieve the desired output power for a given load impedance. To account for the amplifier's dropout
voltage, two additional voltages, based on the Dropout Voltage vs Supply Voltage in the Typical Performance
Characteristics curves, must be added to the result obtained by Equation 9. The result isEquation 10.
(9)
VDD ≥(VOUTPEAK+ (VODTOP + VODBOT)) (10)
The Output Power vs Supply Voltage graph for an 8Ωload indicates a minimum supply voltage of 4.6V. This is
easily met by the commonly used 5V supply voltage. The additional voltage creates the benefit of headroom,
allowing the LM4849 to produce peak output power in excess of 1W without clipping or other audible distortion.
The choice of supply voltage must also not create a situation that violates of maximum power dissipation as
explained above in the POWER DISSIPATION section.
After satisfying the LM4849's power dissipation requirements, the minimum differential gain needed to achieve
1W dissipation in an 8Ωload is found using Equation 11.
(11)
Thus, a minimum overall gain of 2.83 allows the LM4849's to reach full output swing and maintain low noise and
THD+N performance.
The last step in this design example is setting the amplifier's −3dB frequency bandwidth. To achieve the desired
±0.25dB pass band magnitude variation limit, the low frequency response must extend to at least one-fifth the
lower bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth
limit. The gain variation for both response limits is 0.17dB, well within the ±0.25dB desired limit. The results are
an
fL= 100Hz/5 = 20Hz (12)
and an
fH= 20kHz x 5 = 100kHz (13)
As mentioned in the PROPER SELECTION OF EXTERNAL COMPONENTS section, Ri(Right & Left) and Ci
(Right & Left) create a highpass filter that sets the amplifier's lower bandpass frequency limit. Find the coupling
capacitor's value using Equation 14.
Ci≥1/(2πRifL) (14)
The result is
1/(2π*20kΩ*20Hz) = 0.397μF (15)
Use a 0.39μF capacitor, the closest standard value.
The product of the desired high frequency cutoff (100kHz in this example) and the differential gain AVD,
determines the upper passband response limit. With AVD = 3 and fH= 100kHz, the closed-loop gain bandwidth
product (GBWP) is 300kHz. This is less than the LM4849's 3.5MHz GBWP. With this margin, the amplifier can
be used in designs that require more differential gain while avoiding performance,restricting bandwidth
limitations.
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