74HC,HCT191 Datasheet by NXP USA Inc.

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@ PHILIPS
DATA SHEET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT191
Presettable synchronous 4-bit
binary up/down counter
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
FEATURES
•Synchronous reversible counting
•Asynchronous parallel load
•Count enable control for synchronous expansion
•Single up/down control input
•Output capability: standard
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT191 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT191 are asynchronously presettable 4-bit
binary up/down counters. They contain four master/slave
flip-flops with internal gating and steering logic to provide
asynchronous preset and synchronous count-up and
count-down operation.
Asynchronous parallel load capability permits the counter
to be preset to any desired number. Information present on
the parallel data inputs (D0 to D3) is loaded into the counter
and appears on the outputs when the parallel load (PL)
input is LOW. As indicated in the function table, this
operation overrides the counting function.
Counting is inhibited by a HIGH level on the count enable
(CE) input. When CE is LOW internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input. The up/down (U/D) input signal determines
the direction of counting as indicated in the function table.
The CE input may go LOW when the clock is in either
state, however, the LOW-to-HIGH CE transition must
occur only when the clock is HIGH. Also, the U/D input
should be changed only when either CE or CP is HIGH.
Overflow/underflow indications are provided by two types
of outputs, the terminal count (TC) and ripple clock (RC).
The TC output is normally LOW and goes HIGH when a
circuit reaches zero in the count-down mode or reaches
“15” in the count-up-mode. The TC output will remain
HIGH until a state change occurs, either by counting or
presetting, or until U/D is changed. Do not use the TC
output as a clock signal because it is subject to decoding
spikes. The TC signal is used internally to enable the
RC output. When TC is HIGH and CE is LOW, the RC
output follows the clock pulse (CP). This feature simplifies
the design of multistage counters as shown in Figs 5
and 6.
In Fig.5, each RC output is used as the clock input to the
next higher stage. It is only necessary to inhibit the first
stage to prevent counting in all stages, since a HIGH on
CE inhibits the RC output pulse as indicated in the function
table. The timing skew between state changes in the first
and last stages is represented by the cumulative delay of
the clock as it ripples through the preceding stages. This
can be a disadvantage of this configuration in some
applications.
Fig.6 shows a method of causing state changes to occur
simultaneously in all stages. The RC outputs propagate
the carry/borrow signals in ripple fashion and all clock
inputs are driven in parallel. In this configuration the
duration of the clock LOW state must be long enough to
allow the negative-going edge of the carry/borrow signal to
ripple through to the last stage before the clock goes
HIGH. Since the RC output of any package goes HIGH
shortly after its CP input goes HIGH there is no such
restriction on the HIGH-state duration of the clock.
In Fig.7, the configuration shown avoids ripple delays and
their associated restrictions. Combining the TC signals
from all the preceding stages forms the CE input for a
given stage. An enable must be included in each carry
gate in order to inhibit counting. The TC output of a given
stage it not affected by its own CE signal therefore the
simple inhibit scheme of Figs 5 and 6 does not apply.
December 1990 3
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f=6ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi+∑ (CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay CP to QnCL= 15 pF; VCC = 5 V 22 22 ns
fmax maximum clock frequency 36 36 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 31 33 pF
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December 1990 4
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
3, 2, 6, 7 Q0 to Q3flip-flop outputs
4CE count enable input (active LOW)
5U/D up/down input
8 GND ground (0 V)
11 PL parallel load input (active LOW)
12 TC terminal count output
13 RC ripple clock output (active LOW)
14 CP clock input (LOW-to-HIGH, edge triggered)
15, 1, 10, 9 D0 to D3data inputs
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Isllon ”o 01 D: a: 11 FL _ 'ID a: I: 5 u comma m n I E? u c! Fm FLM no a. a, a, 7mm d a q d a q
December 1990 5
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
FUNCTION TABLE
TC AND RC FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
↑= LOW-to-HIGH CP transition
= one LOW level pulse
= TC goes LOW on a LOW-to-HIGH CP transition
OPERATING MODE INPUTS OUTPUTS
PL U/D CE CP DnQn
parallel load L
LX
XX
XX
XL
HL
H
count up H L I ↑X count up
count down H H I ↑X count down
hold (do nothing) HXHXXno change
INPUTS TERMINAL COUNT STATE OUTPUTS
U/D CE CP Q0Q1Q2Q3TC RC
H
L
L
L
H
H
H
H
L
H
H
L
X
X
X
X
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
H
H
H
H
H
Fig.4 Functional diagram.
mnEc‘nnN CONTROL fi/n Kc tr fi/n RC am no — - — H c: {—d cs cm —— c: a? c? mm: MNEUIDN _ _ _ CONTROL Um It in: ac c in: RC 1: —— — EMILE —0Ncs c: —0 cs ‘1' 0 or CLOCK DINECYIBN _ _ _ CONYIOL EMILE _ _ _ — U/n — Gm — Um _ __ ~r _ _ _ _ 9 n: ’— CP W: C? ‘3 new _ _ _ noun
December 1990 6
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
Fig.5 N-stage ripple counter using ripple clock.
Fig.6 Synchronous n-stage counter using ripple carry/borrow.
Fig.7 Synchronous n-stage counter with parallel gated carry/borrow.
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December 1990 7
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
Fig.8 Typical load, count and
inhibit sequence.
Sequence
Load (preset) to binary thirteen;
count up to fourteen, fifteen,
zero, one and two;
inhibit;
count down to one, zero, fifteen,
fourteen and thirteen.
Fig.9 Logic diagram.
December 1990 8
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL=50pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
72
26
21
220
44
37
275
55
47
330
66
56
ns 2.0
4.5
6.0
Fig.10
tPHL/ tPLH propagation delay
CP to TC 83
30
24
255
51
43
320
64
54
395
77
65
ns 2.0
4.5
6.0
Fig.10
tPHL/ tPLH propagation delay
CP to RC 47
17
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.11
tPHL/ tPLH propagation delay
CE to RC 33
12
10
130
26
22
165
33
28
195
39
33
ns 2.0
4.5
6.0
Fig.11
tPHL/ tPLH propagation delay
Dn to Qn
61
22
18
220
44
37
275
55
47
330
66
56
ns 2.0
4.5
6.0
Fig.12
tPHL/ tPLH propagation delay
PL to Qn
61
22
18
220
44
37
275
55
47
330
66
56
ns 2.0
4.5
6.0
Fig.13
tPHL/ tPLH propagation delay
U/D to TC 44
16
13
190
38
32
240
48
41
285
57
48
ns 2.0
4.5
6.0
Fig.14
tPHL/ tPLH propagation delay
U/D to RC 50
18
14
210
42
36
265
53
45
315
63
54
ns 2.0
4.5
6.0
Fig.14
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.15
tWclock pulse width
HIGH or LOW 125
25
21
28
10
8
155
31
26
195
39
33
ns 2.0
4.5
6.0
Fig.10
tWparallel load pulse width
LOW 100
20
17
22
8
6
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.15
December 1990 9
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
trem removal time
PL to CP 35
7
6
8
3
2
45
9
8
55
11
9
ns 2.0
4.5
6.0
Fig.15
tsu set-up time
U/D to CP 205
41
35
50
18
14
255
51
43
310
62
53
ns 2.0
4.5
6.0
Fig.17
tsu set-up time
Dn to PL 100
20
17
19
7
6
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.16
tsu set-up time
CE to CP 140
28
24
44
16
13
175
35
30
210
42
36
ns 2.0
4.5
6.0
Fig.17
thhold time
U/D to CP 0
0
0
−39
−14
−11
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.17
thhold time
Dn to PL 0
0
0
−11
−4
−3
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.16
thhold time
CE to CP 0
0
0
−28
−10
−8
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.17
fmax maximum clock pulse
frequency 4.0
20
24
11
33
39
3.2
16
19
2.6
13
15
MHz 2.0
4.5
6.0
Fig.10
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
December 1990 10
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
Dn
CP
U/D
CE, PL
0.5
0.65
1.15
1.5
December 1990 11
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
26 48 60 72 ns 4.5 Fig.10
tPHL/ tPLH propagation delay
CP to TC 32 51 64 77 ns 4.5 Fig.10
tPHL/ tPLH propagation delay
CP to RC 19 35 44 53 ns 4.5 Fig.11
tPHL/ tPLH propagation delay
CE to RC 19 33 41 50 ns 4.5 Fig.11
tPHL/ tPLH propagation delay
Dn to Qn
22 44 55 66 ns 4.5 Fig.12
tPHL/ tPLH propagation delay
PL to Qn
27 46 58 69 ns 4.5 Fig.13
tPHL/ tPLH propagation delay
U/D to TC 23 45 56 68 ns 4.5 Fig.14
tPHL/ tPLH propagation delay
U/D to RC 24 45 56 68 ns 4.5 Fig.14
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.15
tWclock pulse width
HIGH or LOW 16 9 20 24 ns 4.5 Fig.10
tWparallel load pulse width
LOW 22 11 28 33 ns 4.5 Fig.15
trem removal time
PL to CP 7 1 9 11 ns 4.5 Fig.15
tsu set-up time
U/D to CP 41 20 51 62 ns 4.5 Fig.17
tsu set-up time
Dn to PL 20 9 25 30 ns 4.5 Fig.16
tsu set-up time
CE to CP 30 18 38 45 ns 4.5 Fig.17
thhold time
U/D to CP 0−18 0 0 ns 4.5 Fig.17
thhold time
Dn to PL 0−5 0 0 ns 4.5 Fig.16
thhold time
CE to CP 0−10 0 0 ns 4.5 Fig.17
fmax maximum clock pulse
frequency 20 33 16 13 MHz 4.5 Fig.10
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December 1990 12
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
AC WAVEFORMS
Fig.10 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width and the
maximum clock pulse frequency.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.11 Waveforms showing the clock and count enable inputs (CP, CE) to ripple clock output (RC) propagation
delays.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.12 Waveforms showing the input (Dn) to output (Qn) propagation delays.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
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December 1990 13
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
Fig.13 Waveforms showing the input (PL) to output (Qn) propagation delays.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.14 Waveforms showing the up/down count input (U/D) to terminal count and ripple clock output (TC, RC)
propagation delays.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.15 Waveforms showing the parallel load input (PL) pulse width, removal time to clock (CP) and the output
(Qn) transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
December 1990 14
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter 74HC/HCT191
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.16 Waveforms showing the set-up and hold times from the parallel load input (PL) to the data input (Dn).
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the
clock (CP).
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.

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