MP2161A Datasheet by Monolithic Power Systems Inc.
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LOAD CURRENTUHA)
MP2161A
2A, 6V, 1.5MHz, 17μA IQ, COT
Synchronous Step-Down Converter
in 8-pin TSOT23
MP2161A Rev. 1.02 www.MonolihicPower.com 1
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The Future of Analog IC Technology
DESCRIPTION
The MP2161A is a monolithic, step-down,
switch-mode converter with built-in internal
power MOSFETs. It achieves a 2A continuous
output current from a 2.5V to 6V input voltage
range with excellent load and line regulation.
The output voltage is regulated as low as 0.6V.
The constant-on-time (COT) control scheme
provides fast transient response and eases loop
stabilization. Fault condition protection includes
cycle-by-cycle current limiting and thermal
shutdown.
The MP2161A is available in a small TSOT23-8
package and requires a minimum number of
readily available, standard, external
components.
The MP2161A is ideal for a wide range of
applications including high performance DSPs,
FPGAs, PDAs, and portable instruments.
FEATURES
Very Low IQ: 17A
Default 1.5MHz Switching Frequency
1.5% VFB Accuracy
EN and Power Good for Power Sequencing
Wide 2.5V to 6V Operating Input Range
Output Adjustable from 0.6V
Up to 2A Output Current
100% Duty Cycle in Dropout
110m and 60m Internal Power MOSFET
Switches
Cycle-by-Cycle Over-Current Protection
Short-Circuit Protection with Hiccup Mode
Stable with Low ESR Output Ceramic
Capacitors
Available in a TSOT23-8 Package
APPLICATIONS
Wireless/Networking Cards
Portable Instruments
Battery Powered Devices
Low Voltage I/O System Power
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP2161A
AGND PGND
FB
VIN
C1
10 F
EN
VIN
2.5V to 6V
VOUT
1.2V/ 2A
SW
C2
10 F
R1
200k
R2
200k
PG
EN
PG
OUT
L1
1H
l'l'll'j’
IAKRY
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ORDERING INFORMATION
Part Number* Package Top Marking
MP2161AGJ TSOT23-8 See Below
* For Tape & Reel, add suffix –Z (e.g. MP2161AGJ–Z)
TOP MARKING
AKR: Product code of MP2161AGJ
Y: Year code
PACKAGE REFERENCE
PG
VIN
SW
PGND
EN
FB
AGND
OUT
1
2
3
4
8
7
6
5
TOP VIEW
TSOT23-8
MIPS
TJ
MP2161A – 2A, 6V, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
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ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) .................................... 6.5V
VSW ......................................................................
-0.3V (-1.5V for <20ns&-4V for <8ns) to 6.5V
(10V for <10ns)
All other pins .................................-0.3V to 6.5 V
Junction temperature ................................150C
Lead temperature .....................................260C
Continuous power dissipation (TA = +25°C) (2)
……….….. ............................................... 1.25W
Storage temperature................ -65C to +150C
Recommended Operating Conditions (3)
Supply voltage (VIN) ...........................2.5V to 6V
Operating junction temp. (TJ). .. -40°C to +125°C
Thermal Resistance (4) θJA θJC
TSOT23-8.............................. 100 ..... 55... C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance JA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/JA. Exceeding the maximum allowable powe
r
dissipation will produce an excessive die temperature,
causing the regulator to go into thermal shutdown. Internal
thermal shutdown circuitry protects the device from
permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
““35”
(a)
MP2161A – 2A, 6V, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
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ELECTRICAL CHARACTERISTICS
VIN = 5V, TA = +25C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
2.5V ≤ VIN ≤ 6V, TA =
25oC -1.5 0.600 +1.5
Feedback voltage VFB
TA = -40oC to +85oC (6) -2.5 +2.5
V/%
Feedback current IFB V
FB = 0.6V 10 50 nA
PFET switch on resistance RDSON_P 110 m
NFET switch on resistance RDSON_N 60 m
Switch leakage VEN = 0V, VIN = 6V
VSW = 0V and 6V 0 1 A
PFET current limit 2.6 3.2 4.0 A
VIN = 5V, VOUT = 1.2V 166
On time TON VIN = 3.6V, VOUT = 1.2V 220 ns
VOUT = 1.2V, TA = 25oC -20 1500 +20 kHz/%
Switching frequency Fs TA = -40oC to +85oC(6) -25 1500 +25 kHz/%
Minimum off time(6) T
MIN-OFF 60 ns
Soft-start time TSS-ON V
OUT from 10% to 90% 0.6 1.15 1.7 ms
Power good upper trip threshold PGH FB voltage respect to the
regulation +10 %
Power good lower trip threshold PGL -10 %
Power good delay PGD 50 s
Power good sink current capability VPG-L Sink 1mA 0.4 V
Power good logic-high voltage VPG-H V
IN = 5V, VFB = 0.6V 4.9 V
Power good internal pull-up
resistor RPG 550 k
Under-voltage lockout threshold—
rising 2.15 2.3 2.45 V
Under-voltage lockout threshold—
hysteresis 260 mV
EN input logic-low voltage 0.4 V
EN input logic-high voltage 1.2 V
VEN = 2V 1.5 A
EN input current VEN = 0V 0 A
Supply current (shutdown) VEN = 0V, VIN = 3V 20 100 nA
Supply current (quiescent) VEN = 2V, VFB = 0.63V,
VIN = 5V 17 20 A
Thermal shutdown(5) 150
C
Thermal hysteresis(5) 30
C
NOTES:
5) Guaranteed by design.
6) Guaranteed by characterization test.
HIPS’
LlNE REGULATlON(%) CURRENTwA)
EFFIClENCV(%)
Quiescent Current vs.
Shutdown Current vs.
Input Voltage Input Voltage
40 0 003
0 0025
30 2
3 0 002
F
E
20 [I 0 0015
m
3 0.001
10
o 0005
0 0
2 25 3 35 4 4.5 5 556 2 2.5 3 3.5 4 4.5 5 5.5 6
lNPUTVOLTAGE (V) lNPUT VOLTAGE (V)
Line Regulation Case Temperature Rise
VlN:3V. VOUT:1 2v
0.2 50
0 15 45
a 40
0.1 I 35
0.05 § 30
° lowm E 25
70 05 E 20
“J 15
w
'0 1 lour=2A 8 m
-0.15 5
70.2 0
2.5 3 35 A 45 5 5.5 s 0 0.5 1 15 2 2.5
lNFUT VOLTAGE (V) OUTPUT CURRENT (A)
Efficiency Efficiency
5v/3.3v VW.1.8V VDUT
100 100
95 W=3 av
90 90 K-
55 E \
,
30 g 30* v‘ :5v ,7 vw:3 3v *
75 E
70 E 70
65 m
60 60
55
50 50
1 10 100 1000 10000 0 05 1 15 2 25
LOAD CURRENT(mA) low (A)
LOAD REGULATlON (%
CASE TEMP RISE (“C)
EFFlClENCY(°/a)
Load Regulation
0 10
0 06
0.06
0.04
0 D2
0 00
-0.02
70.04
70 06
-o as
-0.10
00 0.5 1.0 15
LOAD C URRE NT (A)
2.0
Case Temperature Rise
VlN:5V. VOUT:3 3V
Aummwbbw
momomcmo
0010
0 0.5 1 15 2
OUTPUT CURRENT (A)
2.5
Efficiency
5v le. 3.3V VOW
100
m
o
on
o
‘4
o
as
o
w
o
0 u 5 1
low (A)
15 2 25
MP2161A – 2A, 6V, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
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TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VOUT = 1.2V, L = 1.0µH, TA = +25ºC, unless otherwise noted.
l'l'IPj’
Reference Voltage
vs. Temperature
650
640
630
620
610
600
590
580
570
560
550
750 0 50 l 00 1 50
TEMPERATURE (“C)
REFERENCE VOLTAGE (mV)
MP2161A – 2A, 6V, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT = 1.2V, L = 1.0µH, TA = +25ºC, unless otherwise noted.
ll'll'j’
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V|_N Power-Up VIN Power-Up VIN Shutdown
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W L
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ViN L
2V/dlv __
V
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2ms/div ZOUmS/dlv
VIN Shutdown EN Start-Up EN Start-Up
with 2A Load without Load with 2A Load
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MP2161A – 2A, 6V, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT = 1.2V, L = 1.0µH, TA = +25ºC, unless otherwise noted.
"IFS
EN Shutdown
EN Shutdown
without Load with 2A Load
i1
VDW V ‘5...“
1V/dw m wfl,‘ m
VEN vEN
5V/dw 5“];le
VSW
V 5V/div
w
2min: "
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lA/dw. D
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mums/aw Wd” mus/aw
MP2161A – 2A, 6V, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT = 1.2V, L = 1.0µH, TA = +25ºC, unless otherwise noted
l'l'll'j’
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PIN FUNCTIONS
Pin # Name Description
1 PG
Power good indicator. The output of PG is an open drain with an internal pull-up resistor
to VIN. PG is pulled up to VIN when the FB voltage is within ±10% of the regulation level.
If FB voltage is out of that regulation range, it is low.
2 VIN
Supply voltage. The MP2161A operates from a +2.5V to +6V unregulated input. C1 is
needed to prevent large voltage spikes from appearing at the input.
3 SW
Switch output.
4 PGND
Power ground.
5 OUT
Input sense for output voltage.
6 AGND
Analogy ground for internal control circuit.
7 FB
Feedback. An external resistor divider from the output to AGND (tapped to FB) sets the
output voltage.
8 EN
On/off control.
"It
l'l'll'j’
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FUNCTIONAL BLOCK DIAGRAM
Main
Switch
(PCH)
Synchronous
Rectifier
(NCH)
Constant
On -Time
Pulse
PWM
Bias
&
Voltage
Reference
0.6 V
EN
FB
SW
COMP
+
-
VIN
+
+
-
FBCOMP EN
Driver
PDRV
NDRV
Soft start
PGND
AGND
OUT
PWM
COMP
+
-
COMP
+
-
0. 66 V
0. 54 V
PG
Hi-Z
FB for
Fixed Output
VIN
E.A.
+
-
+
Ramp
Generator
COMP
+
-
VOUT
RST
SW
Lo - Iq
Lo-Iq
Lo-Iq
Lo-Iq
Lo-Iq
V
TH
Figure 1: MP2161A Block Diagram
MIPS’
MP2161A – 2A, 6V, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
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OPERATION
The MP2161A uses constant-on-time (COT)
control with input voltage feed forward to stabilize
the switching frequency over the full input range.
At light load, the MP2161A employs a proprietary
control of the low-side switch and inductor
current to eliminate ringing on the switching node
and improve efficiency.
Constant-On-time (COT) Control
Compared to fixed frequency PWM control,
constant-on-time (COT) control offers the
advantage of a simpler control loop and faster
transient response. By using input voltage feed
forward, the MP2161A maintains a nearly
constant switching frequency across the input
and output voltage range. The on time of the
switching pulse is estimated with Equation (1):
OUT
ON
IN
V
T0.667s
V
(1)
To prevent inductor current runaway during load
transient, the MP2161A fixes the minimum off
time at 60ns. However, this minimum off time
limit will not affect operation of the MP2161A in
steady state.
Light-Load Operation
In a light-load condition, the MP2161A uses a
proprietary control scheme to save power and
improve efficiency. The MP2161A turns off the
low-side switch when the inductor current starts
to reverse. Then the MP2161A works in
discontinuous conduction mode (DCM) operation.
There is a zero current cross circuit to detect if
the inductor current starts to reverse.
Considering the internal circuit propagation time,
the typical delay is 50ns. This means that with
this delay the inductor current will still fall after
the ZCD is triggered. If the inductor current falling
slew rate is fast (Vo voltage is high or close to
Vin), the low-side MOSFET (LS-FET) is turned
off, and the inductor current may be negative.
This phenomenon prevents the MP2161A from
entering DCM operation, even with no load. If
DCM mode is required, the off time of the LS-
FET in CCM should be longer than 100ns (2
times the propagation delay). For example, if Vin
is 3.6V and Vo is 3.3V, the off time in CCM is
55ns. It is difficult to enter DCM at light load.
Using a smaller inductor can improve this
condition and make it easier to enter DCM.
Enable (EN)
When the input voltage is greater than the under-
voltage lockout threshold (UVLO), typically 2.3V,
the MP2161A is enabled by pulling EN higher
than 1.2V. Floating or pulling EN down to ground
disables the MP2161A. There is an internal 1M
resistor from EN to ground.
Soft Start (SS)
MP2161A has built-in soft start that ramps up the
output voltage in a controlled slew rate, avoiding
overshoot at start-up. The soft-start time is about
1.15ms typically.
Power GOOD Indicator
MP2161A has an open drain with a 550k pull-
up resistor pin for a power good indicator (PG).
When FB is within +/-10% of the regulation
voltage (e.g., 0.6V), PG is pulled up to VIN by the
internal resistor. If the FB voltage is out of the +/-
10% window, PG is pulled down to ground by an
internal MOSFET. The MOSFET has a maximum
Rdson of less than 400.
Current Limit
MP2161A has a typical 3.2A current limit for the
high-side switch. When the high-side switch hits
the current limit, the MP2161A reaches the
hiccup threshold until the current decreases. This
prevents the inductor current from continuing to
build up, which results in damage to the
components.
Short Circuit and Recovery
The MP2161A enters short-circuit protection
mode when the current limit is reached. It tries to
recover from the short circuit with hiccup mode.
In short-circuit protection, the MP2161A disables
the output power stage, discharges a soft-start
capacitor, and then automatically tries to soft
start again. If the short-circuit condition remains
after the soft start ends, the MP2161A repeats
this operation cycle until the short circuit
disappears, and the output rises back to
regulation level.
l'I'IPj’
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APPLICATION INFORMATION
COMPONENT SELECTION
Setting the Output Voltage
An external resistor divider is used to set the
output voltage (see Typical Application on page
1). The feedback resistor R1 cannot be too
large or too small considering the trade-off
between a dynamic circuit and stability in the
circuit. Choose R1 around 120k to 200k. R2
is then given using Equation (2):
out
R1
R2 V1
0.6
(2)
The feedback circuit is shown in Figure 2.
R1
R2
Vout
FB
MP2161A
Figure 2: Feedback Network
Table 1 lists the recommended resistor values
for common output voltages.
Table 1—Resistor Selection for Common Output
Voltages
VOUT (V) R1 (kΩ) R2 (kΩ)
1.0 200(1%) 300(1%)
1.2 200(1%) 200(1%)
1.8 200(1%) 100(1%)
2.5 200(1%) 63.2(1%)
3.3 200(1%) 44.2(1%)
Selecting the Inductor
A 0.68µH to 2.2µH inductor is recommended for
most applications. For highest efficiency, the
inductor DC resistance should be less than
15m. For most designs, the inductance value
can be derived from Equation (3):
OUT IN OUT
1
IN L OSC
V(VV)
LVIf
(3)
Where IL is the inductor ripple current.
Choose the inductor current to be
approximately 30% of the maximum load
current. The maximum inductor peak current is
calculated using Equation (4):
2
I
II L
LOAD)MAX(L
(4)
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous, therefore a capacitor is required
to supply the AC current to the step-down
converter while maintaining the DC input
voltage. Use low ESR capacitors for the best
performance. Ceramic capacitors with X5R or
X7R dielectrics are highly recommended
because of their low ESR and small
temperature coefficients. For most applications,
a 10µF capacitor is sufficient. For a higher
output voltage, a 47µF capacitor may be
needed for a more stable system.
Since the input capacitor absorbs the input
switching current, it requires an adequate ripple
current rating. The RMS current in the input
capacitor can be estimated with Equation (5)
and Equation (6):
IN
OUT
IN
OUT
LOAD1C V
V
1
V
V
II (5)
The worse case condition occurs at VIN = 2VOUT,
where:
2
I
ILOAD
1C (6)
For simplification, choose an input capacitor
with an RMS current rating greater than half of
the maximum load current.
The input capacitor can be electrolytic, tantalum,
or ceramic. When using electrolytic or tantalum
capacitors, a small, high-quality ceramic
capacitor (e.g., 0.1F) should be placed as
close to the IC as possible. When using
ceramic capacitors, make sure they have
enough capacitance to provide sufficient charge
to prevent excessive voltage ripple at the input.
The input voltage ripple caused by capacitance
can be estimated with Equation (7):
LOAD OUT OUT
IN IN
SIN
IV V
V1
fC1V V
(7)
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aaélé if”
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Selecting the Output Capacitor
The output capacitor (C2) is required to
maintain the DC output voltage. Ceramic
capacitors are recommended. Low ESR
capacitors are preferred to keep the output
voltage ripple low. The output voltage ripple can
be estimated with Equation (8):
OUT OUT
OUT ESR
S1 IN S
VV 1
V1R
fL V 8fC2
(8)
Where L1 is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
When using ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is
caused mainly by the capacitance. For
simplification, the output voltage ripple can be
estimated with Equation (9):
OUT OUT
OUT 2
IN
S1
VV
V1
V
8f L C2
(9)
When using tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. For simplification, the
output ripple can be approximated with
Equation (10):
OUT OUT
OUT ESR
IN
S1
VV
V1R
fL V
(10)
The characteristics of the output capacitor
affect the stability of the regulation system.
PCB Layout Guidelines
Efficient PCB layout of the switching power
supplies is critical for proper IC function. A poor
layout design can result in poor line or load
regulation and stability issues. For best results,
please refer to Figure 3 and follow the
guidelines below:
1. Place the high current paths (GND, VIN,
and SW) very close to the device with
short, direct, and wide traces.
2. Place the input capacitor as close as
possible to the VIN and GND pins.
3. Place the external feedback resistors
next to FB.
4. Keep the switching node (SW) short and
away from the feedback network.
8
7
6
5
L1
C2
C2A
R1
R4
R3
R2
1
2
3
4
OUT
VIN
GND
SW
C1C1A
Figure 3: Recommended PCB Layout
Design Example
Table 2 is a design example following the
application guidelines for the specifications:
Table 2: Design Example
VIN 5V
VOUT 1.2V
fSW 1500kHz
The detailed application schematic is shown in
Figure 4. The typical performance and circuit
waveforms have been shown in the “Typical
Performance Characteristics” section. For more
device applications, please refer to the related
evaluation board datasheets.
l'l'IPj’
H-
MP2161A – 2A, 6V, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
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TYPICAL APPLICATION CIRCUITS
MP2161A
AGND PGND
FB
VIN
C1
10 F
EN
VIN
2.5V to 6V
VOUT
1.2V/ 2A
SW
C2
10 F
R1
200k
R2
200k
PG
EN
PG
OUT
L1
1H
Figure 4: Typical Application Circuit
l'l'll'j’
AAAAAAAAA
EEEEEEEEEEEEEEEEEEEEEE
MP2161A – 2A, 6V, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
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PACKAGE INFORMATION
TSOT23-8
FRONT VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER
FORMING) SHALL BE 0.10 MILLIMETERS MAX.
5) JEDEC REFERENCE IS MO-193, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP MARK
FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK)
TOP VIEW RECOMMENDED LAND PATTERN
SEATING PLANE
SIDE VIEW
DETAIL ''A''
SEE DETAIL ''A''
IAAAA
PIN 1 ID
See note 7
EXAMPLE
TOP MARK
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