MCP6N16 Datasheet by Microchip Technology

MCP6N16 RTD Tem eralure Sensor MICROCHIP

 2014 Microchip Technology Inc. DS20005318A-page 1

MCP6N16

Features:

• High DC Precision:

-V

OS: ±17 µV (maximum, GMIN = 100)

-TC

1: ±60 nV/°C (maximum, GMIN = 100)

- CMRR: 112 dB (minimum, GMIN = 100,

VDD =5.5V)

- PSRR: 110 dB (minimum, GMIN =100,

VDD =5.5V)

-g

E: ±0.15% (maximum, GMIN = 10, 100)

• Flexible:

- Minimum Gain (GMIN) Options:

1, 10 and 100 V/V

- Rail-to-Rail Input and Output

- Gain Set by Two External Resistors

• Bandwidth: 500 kHz (typical, Gain = GMIN =1, 10)

• Power Supply:

-V

DD: 1.8V to 5.5V

-I

Q: 1.1 mA (typical)

- Power Savings (Enable) Pin: EN

• Enhanced EMI Protection:

- Electromagnetic Interference Rejection Ratio

(EMIRR): 111 dB at 2.4 GHz

• Extended Temperature Range: -40°C to +125°C

Typical Applications:

• High-Side Current Sensor

• Wheatstone Bridge Sensors

• Difference Amplifier with Level Shifting

• Power Control Loops

Design Aids:

• SPICE Macro Model

• Microchip Advanced Part Selector (MAPS)

• Application Notes

Description:

Microchip Technology Inc. offers the single Zero-Drift

MCP6N16 instrumentation amplifier (INA) with Enable

pin (EN) and three minimum gain options (GMIN). The

internal offset correction gives high DC precision: it has

very low offset and offset drift, and negligible 1/f noise.

Two external resistors set the gain, minimizing gain

error and drift over temperature. The reference voltage

(VREF) shifts the output voltage (VOUT).

The MCP6N16 is designed for single-supply operation,

with rail-to-rail input (no common mode crossover

distortion) and output performance. The supply voltage

range (1.8V to 5.5V) is low enough to support many

portable applications. All devices are fully specified

from -40°C to +125°C. Each part has EMI filters at the

input pins, for good EMI rejection (EMIRR).

These parts have three minimum gain options (1, 10

and 100 V/V). This allows the user to optimize the input

offset voltage and input noise for different applications.

Typical Application Circuit

Package Types

VOUT

20 kΩ

100Ω

2.49 kΩ

68.1ΩRTD

4.99 kΩ

VDD

MCP6N16-100

10 µF

100Ω

RTD Temperature Sensor

4.99 kΩ4.99 kΩ

MCP6N16

MSOP

VIP

VIM

VSS

VOUT

VFG

5VREF

VDD

MCP6N16

3×3 DFN *

VIP

VIM

VSS

VOUT

VFG

5VREF

VDD

* Includes Exposed Thermal Pad (EP); see Table 3-1.

Zero-Drift Instrumentation Amplifier

=55v was:

MCP6N16

DS20005318A-page 2  2014 Microchip Technology Inc.

Minimum Gain Options

Table 1 shows key specifications that differentiate

between the different minimum gain (GMIN) options.

See Section 1.0 “Electrical Characteristics”,

Section 6.0 “Packaging Information” and Product

Identification System for further information on GMIN.

Figures 1 to 3 show input offset voltage versus

temperature for the three gain options (GMIN =1, 10,

100 V/V).

FIGURE 1: Input Offset Voltage vs.

Temperature, with GMIN =1.

FIGURE 2: Input Offset Voltage vs.

Temperature, with GMIN =10.

FIGURE 3: Input Offset Voltage vs.

Temperature, with GMIN = 100.

TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS

Part No.

MIN

(V/V)

Nom.

VOS

(±μV)

Max.

TC1

(±nV/°C)

Max.

TA= -40 to +125°C

CMRR

(dB)

Min.

VDD =5.5V

PSRR

(dB)

Min.

VDMH

(V)

Min.

GBWP

(MHz)

Typ.

Eni

(μVP-P)

Typ.

f = 0.1 to 10 Hz

eni

(nV/√Hz)

Typ.

f < 500 Hz

MCP6N16-001 1 85 1800 89 91 2.7 0.50 19 900

MCP6N16-010 10 22 180 103 104 0.27 5.0 2.2 105

MCP6N16-100 100 17 60 112 110 0.027 35 0.93 45

Note 1: GMIN is the minimum stable gain (GDM), for a given part option. In other words, GDM ≥GMIN.

-1

ffset Voltage (µV)

-40

-30

-20

-50 -25 0 25 50 75 100 125

Input

Ambient Temperature (°C)

GMIN = 1

28 Samples

VDD = 5.5V

VCM = VDD/2

NPBW = 3 mHz

(µV)

oltag

-1

ffset

-2

nput

GMIN = 10

28 Samples

55V

-3

DD =

VCM = VDD/2

NPBW = 3 mHz

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

(µV)

oltag

-1

ffset

-2

nput

GMIN = 100

28 Samples

=55V

-3

VCM = VDD/2

NPBW = 3 mHz

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

 2014 Microchip Technology Inc. DS20005318A-page 3

MCP6N16

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD –V

SS ............................................................................................................................................................................................................................................ 6.5V

Current at Input Pins (Note 1) ........................................................................................................................................................................................................... ±2 mA

Analog Inputs (VIP and VIM)(Note 1) .................................................................................................................................................................. VSS – 1.0V to VDD +1.0V

All Other Inputs and Outputs ............................................................................................................................................................................... VSS – 0.3V to VDD +0.3V

Difference Input Voltage............................................................................................................................................................................................................. |VDD –V

SS|

Output Short-Circuit Current ...................................................................................................................................................................................................... Continuous

Current at Output and Supply Pins .................................................................................................................................................................................................. ±30 mA

Storage Temperature ......................................................................................................................................................................................................... -65°C to +150°C

Maximum Junction Temperature ......................................................................................................................................................................................................+150°C

ESD protection on all pins (HBM, MM)..................................................................................................................................................................................... ≥4kV,400V

Note 1: See Section 4.3.1.2 “Input Voltage Limits” and Section 4.3.1.3 “Input Current Limits”.

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

MCP6N16

DS20005318A-page 4  2014 Microchip Technology Inc.

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS = GND, VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2, RL=10kΩ

to VL, GDM =G

MIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

Parameters Sym. Min. Typ. Max. Units GMIN Conditions

Input Offset

Input Offset Voltage VOS -85 — +85 µV 1 TA=+25°C

-22 — +22 10

-17 — +17 100

Input Offset Voltage Drift –

Linear Temp. Co.

TC1-1800 — +1800 nV/°C 1 TA= -40°C to +125°C (Note 2)

-180 — +180 10

-60 — +60 100

Input Offset Voltage Drift –

Quadratic Temp. Co.

TC2—±560—pV/°C

21T

A= -40°C to +125°C

—±63— 10

—±69— 100

Input Offset Aging ∆VOS — ±1.0 — µV 1 408 hr Life Test at +150°C,

measured at +25°C

—±0.8— 10

—±0.7— 100

Power Supply Rejection Ratio PSRR 91 109 — dB 1

104 122 — 10

110 128 — 100

Output Offset

Output Offset Voltage VOSO 0µVall

Input Current and Impedance (Note 3)

Input Bias Current IB-100 ±2 +100 pA all

Across Temperature — 20 — TA=+85°C

Across Temperature 0 250 2000 TA=+125°C

Note 1: VCM =(V

IP +V

IM)/2, VDM =(V

IP –V

IM) and GDM =1+R

F/RG

2: For Design Guidance only; not tested.

3: These specifications apply to the VIP

, VIM input pair (use VCM) and to the VREF

, VFG input pair (use VREF instead).

4: This specification applies to the VIP

, VIM, VREF and VFG pins individually.

5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.

6: See Section 1.5 “Explanation of DC Error Specifications”.

 2014 Microchip Technology Inc. DS20005318A-page 5

MCP6N16

Input Offset Current IOS -800 ±300 +800 pA all

Across Temperature — ±320 — TA=+85°C

Across Temperature -1500 ±350 +1500 TA=+125°C

Common Mode Input Impedance ZCM —10

13||10 — Ω||pF

Differential Input Impedance ZDIFF —10

13||4 —

Input Common Mode Voltage (VCM or VREF) (Note 3)

Input Voltage Range (Note 4, Note 5)VIVL —V

SS –0.25 V

SS –0.15 V all

VIVH VDD +0.15 V

DD +0.30 —

Common Mode Rejection Ratio CMRR 80 98 — dB 1 VCM =V

IVL to VIVH, VDD =1.8V

94 112 — 10

103 121 — 100

89 107 — 1 VCM =V

IVL to VIVH, VDD =5.5V

103 121 — 10

112 130 — 100

Common Mode Rejection Ratio at VREF CMRR2 83 101 — dB 1 VREF = 0.2V to VDD –0.2V,

VDD =1.8V

98 116 — 10

102 120 — 100

94 112 — 1 VREF = 0.2V to VDD –0.2V,

VDD =5.5V

109 127 — 10

115 133 — 100

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS = GND, VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2, RL=10kΩ

to VL, GDM =G

MIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

Parameters Sym. Min. Typ. Max. Units GMIN Conditions

Note 1: VCM =(V

IP +V

IM)/2, VDM =(V

IP –V

IM) and GDM =1+R

F/RG

2: For Design Guidance only; not tested.

3: These specifications apply to the VIP

, VIM input pair (use VCM) and to the VREF

, VFG input pair (use VREF instead).

4: This specification applies to the VIP

, VIM, VREF and VFG pins individually.

5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.

6: See Section 1.5 “Explanation of DC Error Specifications”.

MCP6N16

DS20005318A-page 6  2014 Microchip Technology Inc.

Common Mode Nonlinearity (Note 6)INLCM -550 — +550 ppm 1 VCM =V

IVL to VIVH, VDD =1.8V

-75 — +75 10

-20 — +20 100

-310 — +310 1 VCM =V

IVL to VIVH, VDD =5.5V

-35 — +35 10

-10 — +10 100

Input Differential Voltage (VDM) (Note 3)

Differential Input Voltage Range (Note 5)VDML — -3.4/GMIN -2.7/GMIN VallV

DD ≥2.9V, VREF =V

DD,

VOUT within ±0.2%

VDMH +2.7/GMIN +3.4/GMIN —V

DD ≥2.9V, VREF =0V,

VOUT within ±0.2%

Differential Gain Error (Note 6)gE—±0.03—%1V

DD = 1.8V, VREF =V

DD/2,

VDM =±(0.7V)/G

MIN

— ±0.02 — % 10, 100

—±0.03— 1V

DD = 5.5V, VREF =V

DD/2,

VDM = ±(2.55V)/GMIN

— ±0.02 — 10, 100

-0.25 ±0.04 +0.25 % 1 VDD = 5.5V, VREF =0.2V,

VDM = 0 to (2.7V)/GMIN

-0.15 ±0.02 +0.15 % 10, 100

-0.25 ±0.04 +0.25 % 1 VDD = 5.5V, VREF =5.3V,

VDM = 0 to (-2.7V)/GMIN

-0.15 ±0.02 +0.15 % 10, 100

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS = GND, VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2, RL=10kΩ

to VL, GDM =G

MIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

Parameters Sym. Min. Typ. Max. Units GMIN Conditions

Note 1: VCM =(V

IP +V

IM)/2, VDM =(V

IP –V

IM) and GDM =1+R

F/RG

2: For Design Guidance only; not tested.

3: These specifications apply to the VIP

, VIM input pair (use VCM) and to the VREF

, VFG input pair (use VREF instead).

4: This specification applies to the VIP

, VIM, VREF and VFG pins individually.

5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.

6: See Section 1.5 “Explanation of DC Error Specifications”.

VDM Mm D VREF VDM GMW VD VDM NHN

 2014 Microchip Technology Inc. DS20005318A-page 7

MCP6N16

Differential Gain Drift (Note 6)∆gE/∆TA— ±3 — ppm/°C all VDD = 1.8V, VREF =V

DD/2,

VDM =±(0.7V)/G

MIN

—±4— V

DD = 5.5V, VREF =V

DD/2,

VDM = ±(2.55V)/GMIN

—±4— V

DD = 5.5V, VREF =0.2V,

VDM = 0 to (2.7V)/GMIN

—±3— V

DD = 5.5V, VREF =5.3V,

VDM = 0 to (-2.7V)/GMIN

Differential Nonlinearity (Note 6)INLDM —±300—ppmallV

DD = 1.8V, VREF =V

DD/2,

VDM =±(0.7V)/G

MIN

—±150— V

DD = 5.5V, VREF =V

DD/2,

VDM = ±(2.55V)/GMIN

—±300— V

DD = 5.5V, VREF =0.2V,

VDM = 0 to (2.7V)/GMIN

—±300— V

DD = 5.5V, VREF =5.3V,

VDM = 0 to (-2.7V)/GMIN

DC Open-Loop Gain AOL 84 102 — dB 1 VDD =1.8V,

VOUT = 0.2V to 1.6V

100 118 — 10

108 126 — 100

95 113 — 1 VDD =5.5V,

VOUT = 0.2V to 5.3V

111 129 — 10

119 137 — 100

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS = GND, VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2, RL=10kΩ

to VL, GDM =G

MIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

Parameters Sym. Min. Typ. Max. Units GMIN Conditions

Note 1: VCM =(V

IP +V

IM)/2, VDM =(V

IP –V

IM) and GDM =1+R

F/RG

2: For Design Guidance only; not tested.

3: These specifications apply to the VIP

, VIM input pair (use VCM) and to the VREF

, VFG input pair (use VREF instead).

4: This specification applies to the VIP

, VIM, VREF and VFG pins individually.

5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.

6: See Section 1.5 “Explanation of DC Error Specifications”.

MCP6N16

DS20005318A-page 8  2014 Microchip Technology Inc.

Output

Minimum Output Voltage Swing VOL —V

SS +3 — mV all R

L=10kΩ, VDD =1.8V,

VDM =-V

DD/(2GMIN),

VREF =V

DD/2 – 0.9V

—V

SS +6 — R

L=10kΩ, VDD =5.5V,

VDM =-V

DD/(2GMIN),

VREF =V

DD/2 – 1V

—V

SS +60 V

SS + 250 RL=1kΩ, VDD =5.5V,

VDM =-V

DD/(2GMIN),

VREF =V

DD/2 – 1V

Maximum Output Voltage Swing VOH —V

DD –3 — mV R

L=10kΩ, VDD =1.8V,

VDM =V

DD/(2GMIN),

VREF =V

DD/2 + 0.9V

—V

DD –6 — R

L=10kΩ, VDD =5.5V,

VDM =V

DD/(2GMIN),

VREF =V

DD/2 + 1V

VDD –250 V

DD –60 — R

L=1kΩ, VDD =5.5V,

VDM =V

DD/(2GMIN),

VREF =V

DD/2 + 1V

Output Short-Circuit Current ISC —±10—mAV

DD =1.8V

—±35— V

DD =5.5V

Power Supply

Supply Voltage VDD 1.8 — 5.5 V all

Quiescent Current per Amplifier IQ0.5 1.1 1.6 mA IO=0

POR Trip Voltage VPRL 0.9 1.27 — V

VPRH —1.331.6V

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS = GND, VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2, RL=10kΩ

to VL, GDM =G

MIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).

Parameters Sym. Min. Typ. Max. Units GMIN Conditions

Note 1: VCM =(V

IP +V

IM)/2, VDM =(V

IP –V

IM) and GDM =1+R

F/RG

2: For Design Guidance only; not tested.

3: These specifications apply to the VIP

, VIM input pair (use VCM) and to the VREF

, VFG input pair (use VREF instead).

4: This specification applies to the VIP

, VIM, VREF and VFG pins individually.

5: Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.

6: See Section 1.5 “Explanation of DC Error Specifications”.

 2014 Microchip Technology Inc. DS20005318A-page 9

MCP6N16

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2,

RL=10kΩ to VL, CL= 60 pF, GDM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

Parameters Sym.

Min.

Typ.

Max.

Units GMIN Conditions

AC Response

Gain-Bandwidth Product GBWP — 0.5 — MHz 1

—5 — 10

— 35 — 100

Phase Margin PM — 70 — ° all

Open-Loop Output Impedance ROL —1.6 —kΩ

Power Supply Rejection Ratio PSRR — 80 — dB 1 f = 1 kHz

—98 — 10

— 123 — 100

Common Mode Rejection Ratio

at VCM and VREF

CMRR, CMRR2 — 83 — dB 1 f = 10 kHz

—80 — 10

— 140 — 100

Step Response (see Section 4.1.4 “AC Performance”)

Slew Rate SR Note 1 V/µs all

Start-Up Time tSTR —2 —ms1G

DM = 1000, VDD power up to 0.1% VOUT settling (Note 3, Note 4)

—0.3 — 10

— 0.2 — 100

Overdrive Recovery,

Input Common Mode

tIRC —1 —µsallV

IP =VIM =V

IVH + 0.5V to VDD – 1V (or VIVL – 0.5V to 1V),

90% of VOUT change (IB≤2mA) (Note 4)

Overdrive Recovery,

Input Differential Mode

tIRD —10 — G

MINVDM =G

MINVDMH + 0.5V to 0V (or GMINVDML – 0.5V to 0V),

VREF = 1V (or VDD – 1V), 90% of VOUT change (Note 4)

Overdrive Recovery, Output tOR —180 — G

DMVDM = 1.5V to 0V (or -1.5V to 0V),

VREF =V

DD – 1V (or 1V), 90% of VOUT change (Note 4)

Note 1: The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandwidth.

2: These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMD tone at DC, a residual tone at 100 Hz and

other IMD tones and clock tones.

3: High gains behave differently; see Section 4.4.4 “Offset at Power-Up”.

4: tSTR, tSTL, tIRC, tIRD and tOR include some uncertainty due to clock edge timing.

MCP6N16

DS20005318A-page 10  2014 Microchip Technology Inc.

Noise

Input Noise Voltage Density eni —900 —nV/√Hz 1 f = 500 Hz

—105 — 10

— 45 — 100

Input Noise Voltage Eni —19 —µV

P-P 1 f = 0.1 Hz to 10 Hz

—2.2 — 10

— 0.93 — 100

— 5.9 — 1 f = 0.01 Hz to 1 Hz

—0.69 — 10

— 0.30 — 100

Input Current Noise Density ini —7 —fA/√Hz all f = 1 kHz

Output Noise Voltage Density eno 0nV/√Hz

Output Noise Voltage Eno 0µV

P-P

Amplifier Distortion (Note 2)

Intermodulation Distortion (AC) IMD — 5 — µVPK all VCM tone = 100 mVPK at 100 Hz

EMI Protection

EMI Rejection Ratio EMIRR — 103 — dB all VIN =0.1V

PK, f = 400 MHz

—106 — V

IN =0.1V

PK, f = 900 MHz

—106 — V

IN =0.1V

PK, f = 1800 MHz

— 111 — VIN =0.1V

PK, f = 2400 MHz

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2,

RL=10kΩ to VL, CL= 60 pF, GDM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

Parameters Sym.

Min.

Typ.

Max.

Units GMIN Conditions

Note 1: The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandwidth.

2: These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMD tone at DC, a residual tone at 100 Hz and

other IMD tones and clock tones.

3: High gains behave differently; see Section 4.4.4 “Offset at Power-Up”.

4: tSTR, tSTL, tIRC, tIRD and tOR include some uncertainty due to clock edge timing.

 2014 Microchip Technology Inc. DS20005318A-page 11

MCP6N16

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS = GND, VCM =V

DD/2, VDM =0V, V

REF =V

DD/2, VL=V

DD/2,

RL=10kΩ to VL, CL=60 pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

Parameters Sym. Min. Typ. Max. Units GMIN Conditions

EN Low Specifications

EN Logic Threshold, Low VIL ——0.2V

DD Vall

EN Input Current, Low IENL — -10 — pA EN = 0V

GND Current ISS -8 -2 — µA EN = 0V, VDD =5.5V

Amplifier Output Leakage IO(LEAK) —-1—nA EN=0V

EN High Specifications

EN Logic Threshold, High VIH 0.8VDD ——Vall

EN Input Current, High IENH —10—pA EN=V

EN Dynamic Specifications

EN Input Hysteresis VHYST —0.16VDD —Vall

EN Input Resistance RPD —1013 —Ω

EN Low to Amplifier Output High Z Turn-Off Time tOFF —0.1 2µs EN=0.2V

DD to VOUT =0.1(V

DD/2), VL=0V

EN High to Amplifier Output On Time tON — 12 100 VDD = 1.8V, EN = 0.8VDD to VOUT =0.9(V

DD/2), VL=0V

— 30 100 VDD = 5.5V, EN = 0.8VDD to VOUT =0.9(V

DD/2), VL=0V

EN Low to EN High hold time tENLH 50 — — Minimum time before releasing EN (Note 1)

EN High to EN Low setup time tENHL 50 — — Minimum time before exerting EN (Note 1)

POR Dynamic Specifications

VDD ↓ to Output Off tPHL —10—µsallV

L=0V, V

DD = 1.8V to VPRL – 0.1V step, 90% of VOUT change

VDD ↑ to Output On tPLH —100 —V

L=0V, V

DD = 0V to VPRH + 0.1V step, 90% of VOUT change

Note 1: For design guidance only; not tested.

MCP6N16

DS20005318A-page 12  2014 Microchip Technology Inc.

TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = 1.8V to 5.5V, VSS = GND.

Parameters Sym. Min. Typ. Max. Units Conditions

Temperature Ranges

Specified Temperature Range TA-40 — +125 °C

Operating Temperature Range TA-40 — +125 Note 1

Storage Temperature Range TA-65 — +150

Thermal Package Resistances

Thermal Resistance, 8L-DFN (3×3) θJA —57 — °C/W

Thermal Resistance, 8L-MSOP θJA —211 —

Note 1: Operation must not cause TJ to exceed the Absolute Maximum Junction Temperature specification (+150°C).

 2014 Microchip Technology Inc. DS20005318A-page 13

MCP6N16

1.3 Timing Diagrams

FIGURE 1-1: Amplifier Start-Up Timing Diagram.

FIGURE 1-2: Common Mode Input Overdrive Recovery Timing Diagram.

FIGURE 1-3: Differential Mode Input Overdrive Recovery Timing Diagram.

FIGURE 1-4: Output Overdrive Recovery Timing Diagram.

FIGURE 1-5: POR Timing Diagram.

FIGURE 1-6: EN Timing Diagram.

VDD

VOUT

1.001 VREF

0.999 VREF

1.8V to 5.5V

1.8V

tSTR

VOUT

tIRC

VCM VIVH +0.5V VDD –1V

VREF

tIRC

VIVL –0.5V

VREF

VOUT

tIRD

VREF

GDMVDM

VREF

GMINVDMH +0.5V

VOH

tIRD

VDD –1V

VREF

GMINVDML –0.5V

VOL

VOUT

tOR

VREF

GMINVDM

VDD –1V

VREF

1.5V

VOH

tOR

VREF

-1.5V

VOL

VOUT

tPHL

VDD

VPRL –0.1V

High Z

1.8V

tPLH

VPRH +0.1V

High Z

VOUT

tOFF

High Z

tON

tENLH tENHL

High Z

MCP6N16

DS20005318A-page 14  2014 Microchip Technology Inc.

1.4 DC Test Circuits

1.4.1 INPUT OFFSET TEST CIRCUIT

Figure 1-7 is a simple circuit that can test the INA’s

input offset errors and input voltage range (VE, VIVL and

VIVH; see Section 1.5.1 “Input Offset Related

Errors” and Section 1.5.2 “Input Offset Common

Mode Nonlinearity”). U2 is part of a control loop that

forces VOUT to equal VCNT

; U1 can be set to any bias

point.

FIGURE 1-7: Simple Test Circuit for

Common Mode (Input Offset).

When MCP6N16 is in its normal range of operation, the

DC output voltages are (where VE is the sum of input

offset errors and gE is the gain error):

EQUATION 1-1:

Table 1-5 shows the resulting behavior for different

GMIN options.

1.4.2 DIFFERENTIAL GAIN TEST CIRCUIT

Figure 1-8 is a simple circuit that can test the INA’s

differential gain error, nonlinearity and input voltage

range (gE, INLDM, VDML and VDMH; see Section 1.5.3

“Differential Gain Error and Nonlinearity”). RF and

RG are 0.01% for accurate gain error measurements.

The output voltages are (where VE is the sum of input

offset errors and gE is the gain error):

EQUATION 1-2:

FIGURE 1-8: Simple Test Circuit for

Differential Mode.

For different values of VREF

, VDM sweeps over different

ranges to keep VREF

, VFG and VOUT within their ranges.

Table 1-6 shows the recommended RF and RG; they

produce a 10 kΩ load. VL can usually be left open.

1.4.3 DYNAMIC TESTING OF INPUT

BEHAVIOR

The circuit in Figure 1-8 can test the input’s dynamic

behavior (i.e., IMD, tSTR, tSTL, tIRC, tIRD and tOR);

measure the output at VOUT

, instead of at VM.

TABLE 1-5: RESULTS

GMIN

(V/V)

Nom.

(kΩ)

Typ.

GDM

(kV/V)

Typ.

GDMVOS

(±mV)

Max.

(kHz)

Typ.

at VOUT

(Hz)

Typ.

at VM

1 100 1.00 85 0.50 0.50

10 402 4.02 88 1.2

100 68 8.7

RGRF

100 nF

VDD

2.2 µF

VREF

31.6 kΩ

10 µF CCNT

MCP6N16

MCP6H01

VCNT

31.6 kΩ

RCNT

31.6 kΩ

OUT

2.2 nF

100Ω

VCM

2.2 nF

100Ω

GDM 1R

FRG



VOUT VCNT

VMVREF GDM 1g

+VE

TABLE 1-6: SELECTING RF AND RG

GMIN

(V/V)

Nom.

(kΩ)

Nom.

(kΩ)

Nom.

GDM

(V/V)

Nom.

1 0 Open 1.0000

10 10.0 || 90.9 1.00 10.009

100 10.0 || 1000 100 100.01

GDM 1R

FRG



VMVREF G+ DM 1g

+VDM VE

+=

VOUT VREF GDM 1g

+VDM VE

++=

63.4 kΩ

100Ω

VCM +V

DM/2

1.0 µF

VOUT

100 nF

VDD

2.2 µF

VREF

VCM –V

DM/2

MCP6N16

 2014 Microchip Technology Inc. DS20005318A-page 15

MCP6N16

1.5 Explanation of DC Error

Specifications

1.5.1 INPUT OFFSET RELATED ERRORS

The input offset error (VE) is extracted from input offset

measurements (see Section 1.4.1 “Input Offset Test

Circuit”), based on Equation 1-1:

EQUATION 1-3:

VE has several terms, which assume a linear response

to changes in VDD, VSS, VCM, VOUT and TA (all of which

are in their specified ranges):

EQUATION 1-4:

Equation 1-2 shows how VE affects VOUT

1.5.2 INPUT OFFSET COMMON MODE

NONLINEARITY

The input offset error (VE) changes nonlinearly with

VCM. Figure 1-9 shows VE vs. VCM, as well as a linear

fit line (VE_LIN) based on VOS and CMRR. The INA is in

standard conditions (∆VOUT =0, V

DM =0, etc.). V

CM is

swept from VIVL to VIVH. The test circuit is in

Section 1.4.1 “Input Offset Test Circuit” and VE is

calculated using Equation 1-3.

FIGURE 1-9: Input Offset Error vs.

Common Mode Input Voltage.

Based on the measured VE data, we obtain the

following linear fit:

EQUATION 1-5:

The remaining error (∆VE) is described by the Common

Mode Nonlinearity spec:

EQUATION 1-6:

The same common mode behavior applies to VE when

VREF is swept, instead of VCM, since both input stages

are designed the same:

EQUATION 1-7:

VEVMVREF

–GDM 1g

+



Where:

PSRR, CMRR, CMRR2 and AOL are in

units of V/V

∆TA is in units of °C

TC1 is in units of V/°C

VDM =0

VEVOS



VDD



VSS

–

PSRR

---------------------------------



VCM

CMRR

-----------------



VREF

CMRR2

--------------------+++=



VOUT

AOL

-----------------



TATC1



VE, VE_LIN (V)

VCM (V)

VIVL VIVH

VDD/2

VE_LIN

VE

Where:

VE_LIN VOS VCM VDD 2



–CMRR



VOS V2

1CMRR



V3V1

–VIVH VIVL

–



Where:

INLCMH max



VIVH VIVL

–





VEVEVE_LIN

–=

INLCML min



VIVH VIVL

–



INLCM INLCMH INLCMH INLCML



INLCML otherwise



VE_LIN2 VOS VREF VDD 2



–CMRR2



INLCMH2 max



VE2

VIVH VIVL

–



INLCML2 min



VE2

VIVH VIVL

–



Where:



VE2 VEVE_LIN2

–=

INLCM2 INLCMH2 INLCMH2 INLCML2



INLCML2 otherwise



MCP6N16

DS20005318A-page 16  2014 Microchip Technology Inc.

1.5.3 DIFFERENTIAL GAIN ERROR AND

NONLINEARITY

The differential errors are extracted from differential

gain measurements (see Section 1.4.2 “Differential

Gain Test Circuit”), based on Equation 1-2. These

errors are the differential gain error (gE) and the input

offset error (VE, which changes nonlinearly with VDM):

EQUATION 1-8:

These errors are adjusted for the expected output, then

referred back to the input, giving the differential input

error (VED) as a function of VDM:

EQUATION 1-9:

Figure 1-10 shows VED vs. VDM, as well as a linear fit

line (VED_LIN) based on VED and gE. The INA is in

standard conditions (∆VOUT =0, etc.). V

DM is swept

from VDML to VDMH.

FIGURE 1-10: Differential Input Error vs.

Differential Input Voltage.

Based on the measured VED data, we obtain the

following linear fit:

EQUATION 1-10:

Note that the VE value measured here is not as

accurate as the one obtained in Section 1.5.1 “Input

Offset Related Errors”.

The remaining error (∆VED) is described by the

Differential Nonlinearity spec:

EQUATION 1-11:

GDM 1R

FRG



VMGDM 1g

+VDM V+ E

=

VED VMGDM

VDM

–=

VED, VED_LIN (V)

VDM (V)

VDML VDMH

VED_LIN

VED

VED

Where:

VED_LIN 1g

+VEgEVDM

gEV3V1

–VDMH VDML

–



1–=

VEV21g

+



Where:

INLDMH max VED

VDMH VDML

–=

VED VED VED_LIN

–=

INLDML min VED

VDMH VDML

–=

INLDM INLDMH INLDMH INLDML

=

INLDML otherwise=

25 5mm“ emema 15-/. o-/. 2n Smalls v .ssv o reuse: emema 35v. 15-/. o-/. 2n Smalls v .uv o reuse: emema 35v. 15-/. o-/. 25 Samvlu

 2014 Microchip Technology Inc. DS20005318A-page 17

MCP6N16

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

2.1 DC Precision

FIGURE 2-1: Input Offset Voltage, with

GMIN =1.

FIGURE 2-2: Input Offset Voltage, with

GMIN = 10.

FIGURE 2-3: Input Offset Voltage, with

GMIN = 100.

FIGURE 2-4: Input Offset Voltage Drift,

with GMIN =1.

FIGURE 2-5: Input Offset Voltage Drift,

with GMIN =10.

FIGURE 2-6: Input Offset Voltage Drift,

with GMIN =100.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

30%

GMIN = 1

28 Samples

25%

ence

28 Samples

TA= +25°C

NPBW = 3 mHz

20%

ccur

=18V

10%

15%

ge of

VDD = 5.5V

10%

rcent

-12-10-8-6-4-2 0 2 4 6 81012

Input Offset Voltage (µV)

10%

15%

20%

25%

30%

35%

40%

45%

-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0

Percentage of Occurrences

Input Offset Voltage (µV)

GMIN = 10

28 Samples

TA= +25°C

NPBW = 3 mHz

VDD = 5.5V

VDD = 1.8V

10%

20%

30%

40%

50%

60%

-1.0 -0.6 -0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0

Percentage of Occurrences

Input Offset Voltage (µV)

GMIN = 100

28 Samples

TA= +25°C

NPBW = 3 mHz

VDD = 5.5V

VDD = 1.8V

35%

40%

GMIN = 1

28 Samples

30%

35%

ence

28 Samples

TA= -40 to +125°C

NPBW = 3 mHz

25%

ccur

VDD = 1.8V

=55V

20%

ge of

10%

rcent

-600 -400 -200 0 200 400 600

Input Offset Voltage Drift; TC

(nV/°C)

35%

40%

GMIN = 10

28 Samples

30%

35%

ence

28 Samples

TA= -40 to +125°C

NPBW = 3 mHz

25%

ccur

VDD = 5.5V

=18V

20%

ge of

10%

rcent

-40 -30 -20 -10 0 10 20 30 40

Input Offset Voltage Drift; TC

(nV/°C)

35%

40%

GMIN = 100

28 Samples

30%

35%

ence

28 Samples

TA= -40 to +125°C

NPBW = 3 mHz

25%

ccur

20%

ge of

VDD = 5.5VVDD = 1.8V

10%

rcent

-16 -12 -8 -4 0 4 8 12 16

Input Offset Voltage Drift; TC

(nV/°C)

Hence 0! 15 5mm“ .mm ano 4m) n Ann son 12m) 'Gmn an small: Jan .12n 4n n n An an 120 1st: Valuna o rence o! -15-/. 15v. ‘ my. 40% 2: Samplu Azn Ann n M An an 0 2n 4n

MCP6N16

DS20005318A-page 18  2014 Microchip Technology Inc.

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-7: Quadratic Input Offset

Voltage Drift, with GMIN =1.

FIGURE 2-8: Quadratic Input Offset

Voltage Drift, with GMIN =10.

FIGURE 2-9: Quadratic Input Offset

Voltage Drift, with GMIN = 100.

FIGURE 2-10: Input Offset Voltage vs.

Output Voltage, with GMIN =1.

FIGURE 2-11: Input Offset Voltage vs.

Output Voltage, with GMIN =10.

FIGURE 2-12: Input Offset Voltage vs.

Output Voltage, with GMIN = 100.

50%

55%

GMIN = 1

28 Samples

40%

45%

rrenc

28 Samples

TA= -40 to +125°C

NPBW = 3 mHz

30%

35%

Occu

VDD = 1.8V

=55V

20%

25%

age o

10%

15%

ercen

1200

800

400

800

1200

800

400

800

1200

Quadratic Input Offset Voltage Drift;

(pV/°C

)

30%

GMIN = 10

28 Samples

20%

25%

rrenc

28 Samples

TA= -40 to +125°C

NPBW = 3 mHz

15%

20%

Occu

1.8V

10%

15%

age o

1.8V

VDD = 5.5V

ercen

160

120

160

120

160

Quadratic Input Offset Voltage Drift;

(pV/°C

)

45%

GMIN = 100

28 Sam

les

30%

35%

40%

rrenc

TA= -40 to +125°C

NPBW = 3 mHz

25%

30%

Occu

VDD = 5.5V

VDD = 1.8V

15%

20%

age o

10%

ercen

120

100

120

100

Quadratic Input Offset Voltage Drift;

(pV/°C

)

Representative Part

MIN

(µV)

MIN

NPBW = 2 Hz

oltag

-5

ffset

-15

-10

put

VDD = 1.8V VDD = 5.5V

-25

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Representative Part

MIN

(µV)

MIN

NPBW = 2 Hz

oltag

-5

ffset

VDD = 1.8V VDD = 5.5V

-15

-10

put

-25

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Representative Part

MIN

100

(µV)

MIN

100

NPBW = 2 Hz

oltag

-5

ffset

VDD = 1.8V VDD = 5.5V

-15

-10

put

-25

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

40 Vnnaga o = .30 .as-c Van - Van

 2014 Microchip Technology Inc. DS20005318A-page 19

MCP6N16

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-13: Input Offset Voltage vs.

Power Supply Voltage, with VCM = 0V and

GMIN =1.

FIGURE 2-14: Input Offset Voltage vs.

Power Supply Voltage, with VCM = 0V and

GMIN = 10.

FIGURE 2-15: Input Offset Voltage vs.

Power Supply Voltage, with VCM = 0V and

GMIN = 100.

FIGURE 2-16: Input Offset Voltage vs.

Power Supply Voltage, with VCM =V

DD and

GMIN =1.

FIGURE 2-17: Input Offset Voltage vs.

Power Supply Voltage, with VCM =V

DD and

GMIN = 10.

FIGURE 2-18: Input Offset Voltage vs.

Power Supply Voltage, with VCM =V

DD and

GMIN = 100.

-10

ffset Voltage (µV)

Representative Part

VCM = VSS

GMIN = 1

NPBW = 2 Hz

-50

-40

-30

-20

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Input

Power Supply Voltage (V)

+125°C

+85°C

+25°C

-40°C

Representative Part

= V

(µV)

GMIN = 10

NPBW = 2 Hz

oltag

-5

ffset

-15

nput

+125°C

-25

+25°C

-40°C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Power Supply Voltage (V)

Representative Part

= V

(µV)

GMIN = 100

NPBW = 2 Hz

oltag

-5

ffset

-15

nput

+125°C

-25

+25°C

-40°C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Power Supply Voltage (V)

Representative Part

= V

(µV)

GMIN = 1

NPBW = 2 Hz

oltag

-10

ffset

-30

-20

nput

+125°C

+85

-40

+85

+25°C

-40°C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Power Supply Voltage (V)

Representative Part

= V

(µV)

GMIN = 10

NPBW = 2 Hz

oltag

-5

ffset

-15

nput

+125°C

-25

+85°C

+25°C

-40°C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Power Supply Voltage (V)

Representative Part

= V

(µV)

GMIN = 100

NPBW = 2 Hz

oltag

-5

ffset

-15

nput

+125°C

+85

-25

+85

+25°C

-40°C

0.00.51.01.52.02.53.03.54.04.55.05.56.06.5

Power Supply Voltage (V)

.0 «MW e 20 _ E a > xmo»- G I c = JD .50 m um...“ w 2“ E >° o :4“ m .5“ 40 Voltage 0 = .30

MCP6N16

DS20005318A-page 20  2014 Microchip Technology Inc.

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-19: Input Offset Voltage vs.

Common Mode Voltage, with VDD = 1.8V and

GMIN =1.

FIGURE 2-20: Input Offset Voltage vs.

Common Mode Voltage, with VDD = 1.8V and

GMIN = 10.

FIGURE 2-21: Input Offset Voltage vs.

Common Mode Voltage, with VDD = 1.8V and

GMIN = 100.

FIGURE 2-22: Input Offset Voltage vs.

Common Mode Voltage, with VDD = 5.5V and

GMIN =1.

FIGURE 2-23: Input Offset Voltage vs.

Common Mode Voltage, with VDD = 5.5V and

GMIN = 10.

FIGURE 2-24: Input Offset Voltage vs.

Common Mode Voltage, with VDD = 5.5V and

GMIN = 100.

-10

ffset Voltage (µV)

Representative Part

VDD = 1.8V

GMIN = 1

NPBW = 2 Hz

-50

-40

-30

-20

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

Input

Input Common Mode Voltage (V)

+125°C

+85°C

+25°C

-40°C

Representative Part

= 1.

(µV)

GMIN = 10

NPBW = 2 Hz

oltag

-10

ffset

-30

-20

nput

+125°C

+85

-40

+85

+25°C

-40°C

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

Input Common Mode Voltage (V)

Representative Part

= 1.

(µV)

GMIN = 100

NPBW = 2 Hz

oltag

-10

ffset

-30

-20

nput

+125°C

+85

-40

+85

+25°C

-40°C

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

Input Common Mode Voltage (V)

Representative Part

= 5.5V

(µV)

GMIN = 1

NPBW = 2 Hz

oltag

-10

ffset

-30

-20

nput

+125°C

-40

+25°C

-40°C

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Input Common Mode Voltage (V)

Representative Part

= 5.5V

(µV)

GMIN = 10

NPBW = 2 Hz

oltag

-10

ffset

-30

-20

nput

+125°C

+85

-40

+85

+25°C

-40°C

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Input Common Mode Voltage (V)

Representative Part

= 5.5V

(µV)

GMIN = 100

NPBW = 2 Hz

oltag

-10

ffset

-30

-20

nput

+125°C

-40

+25°C

-40°C

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Input Common Mode Voltage (V)

 2014 Microchip Technology Inc. DS20005318A-page 21

MCP6N16

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-25: Input Offset Voltage vs.

Reference Voltage, with GMIN =1.

FIGURE 2-26: Input Offset Voltage vs.

Reference Voltage, with GMIN = 10.

FIGURE 2-27: Input Offset Voltage vs.

Reference Voltage, with GMIN = 100.

FIGURE 2-28: CMRR, with GMIN =1.

FIGURE 2-29: CMRR, with GMIN =10.

FIGURE 2-30: CMRR, with GMIN =100.

-30

-25

-20

-15

-10

-5

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Input Offset Voltage (µV)

Reference Voltage (V)

Representative Part

GMIN = 1

TA= +25°C

NPBW = 2 Hz

VDD = 1.8V VDD = 5.5V

-30

-25

-20

-15

-10

-5

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Input Offset Voltage (µV)

Reference Voltage (V)

Representative Part

GMIN = 10

TA= +25°C

NPBW = 2 Hz

VDD = 1.8V VDD = 5.5V

-30

-25

-20

-15

-10

-5

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Input Offset Voltage (µV)

Reference Voltage (V)

Representative Part

GMIN = 100

TA= +25°C

NPBW = 2 Hz

VDD = 1.8V VDD = 5.5V

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

60%

-12 -8 -4 0 4 8 12

Percentage of Occurrences

1/CMRR (µV/V)

410 Samples

TA= +25°C

GMIN = 1

NPBW = 2.5 Hz

VDD = 5.5V

VDD = 1.8V

10%

15%

20%

25%

30%

35%

40%

45%

50%

-5-4-3-2-1012345

Percentage of Occurrences

1/CMRR (µV/V)

310 Samples

TA= +25°C

GMIN = 10

NPBW = 2.5 Hz

VDD = 5.5V

VDD = 1.8V

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

60%

65%

70%

-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0

Percentage of Occurrences

1/CMRR (µV/V)

410 Samples

TA= +25°C

GMIN = 100

NPBW = 2.5 Hz

VDD = 5.5V

VDD = 1.8V

m. n - as'c .1” "Paw- 2.5m n - as-c m. n - as'c .1” "Paw- 2.5m o 4% emema a7. 30% v. - are 0% 2117- n . are .m. NPaw- 2.5m o 1 2v. 8% emema 4% a7.

MCP6N16

DS20005318A-page 22  2014 Microchip Technology Inc.

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-31: CMRR2, with GMIN =1.

FIGURE 2-32: CMRR2, with GMIN = 10.

FIGURE 2-33: CMRR2, with GMIN = 100.

FIGURE 2-34: PSRR, with GMIN =1.

FIGURE 2-35: PSRR, with GMIN =10.

FIGURE 2-36: PSRR, with GMIN = 100.

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

-10-8-6-4-2 0 2 4 6 810

Percentage of Occurrences

1/CMRR2 (µV/V)

410 Samples

TA= +25°C

GMIN = 1

NPBW = 2.5 Hz

VDD = 5.5V

VDD = 1.8V

50%

55%

310 Samples

=+25

45%

ences

= +25

GMIN = 10

NPBW = 2.5 Hz

30%

35%

ccur

20%

25%

30%

ge of

VDD = 5.5V

10%

15%

20%

rcent

10%

VDD = 1.8V

-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8

1/CMRR2 (µV/V)

80%

90%

410 Samples

=+25

70%

80%

ences

= +25

GMIN = 100

NPBW = 2.5 Hz

50%

60%

ccur

40%

ge of

VDD = 5.5V

20%

30%

rcent

18V

10%

DD =

-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8

1/CMRR2 (µV/V)

18%

20%

410 Samples

+25

14%

16%

18%

ences

+25

VDD = 1.8V to 5.5V

GMIN = 1

NPBW

2.5 Hz

12%

14%

ccur

NPBW 2.5 Hz

10%

ge of

rcent

-5-4-3-2-1012345

1/PSRR (µV/V)

18%

20%

310 Samples

+25

14%

16%

18%

ences

+25

VDD = 1.8V to 5.5V

GMIN = 10

NPBW

2.5 Hz

12%

14%

ccur

NPBW 2.5 Hz

10%

ge of

rcent

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

1/PSRR (µV/V)

20%

22%

410 Samples

+25

16%

18%

ences

+25

VDD = 1.8V to 5.5V

GMIN = 100

NPBW

2.5 Hz

12%

14%

ccur

NPBW 2.5 Hz

10%

12%

ge of

rcent

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

1/PSRR (µV/V)

11a Inn an 1‘ . .zs-c “1 011a Inn an soy. ercema o-/. 1‘ . .zs-c 11a Inn an Gum-10H

 2014 Microchip Technology Inc. DS20005318A-page 23

MCP6N16

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-37: DC Open-Loop Gain, with

GMIN =1.

FIGURE 2-38: DC Open-Loop Gain, with

GMIN = 10.

FIGURE 2-39: DC Open-Loop Gain, with

GMIN = 100.

FIGURE 2-40: CMRR vs. Ambient

Temperature.

FIGURE 2-41: CMRR2 vs. Ambient

Temperature.

FIGURE 2-42: PSRR vs. Ambient

Temperature.

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

-10-8-6-4-2 0 2 4 6 810

Percentage of Occurrences

1/A

(µV/V)

410 Samples

TA= +25°C

GMIN = 1

NPBW = 2.5 Hz

VDD = 5.5V

VDD = 1.8V

50%

55%

310 Samples

=+25

45%

ences

= +25

GMIN = 10

NPBW = 2.5 Hz

30%

35%

ccur

20%

25%

30%

ge of

VDD = 5.5V

10%

15%

20%

rcent

10%

VDD = 1.8V

-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8

1/A

(µV/V)

80%

90%

410 Samples

=+25

70%

80%

ences

= +25

GMIN = 100

NPBW = 2.5 Hz

50%

60%

ccur

40%

ge of

VDD = 5.5V

20%

30%

rcent

18V

10%

DD =

-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8

1/A

(µV/V)

145

150

GMIN = 100, VDD = 5.5V

= 1.

135

140

125

130

(dB)

110

115

120

MRR

100

105

110

100

GMIN = 10, VDD = 5.5V

VDD = 1.8V

GMIN = 1, VDD = 5.5V

VDD = 1.8V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

145

150

135

140

125

130

(dB)

110

115

120

MRR

100

105

110

GMIN = 100, VDD = 5.5V

VDD = 1.8V

100

GMIN = 10, VDD = 5.5V

VDD = 1.8V

GMIN = 1, VDD = 5.5V

VDD = 1.8V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

145

150

MIN

= 100

135

140

MIN

125

130

(dB)

GMIN = 10

110

115

120

PSRR

GMIN = 1

100

105

110

100

VDD = 1.8V to 5.5V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

[PA I: ﬁ Ann son a ann ms 2 Ann 0.04 ,0. . 3, sun 71mm 7an

MCP6N16

DS20005318A-page 24  2014 Microchip Technology Inc.

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-43: DC Open-Loop Gain vs.

Ambient Temperature.

FIGURE 2-44: Input Bias and Offset

Currents vs. Common Mode Input Voltage, with

TA= +85°C.

FIGURE 2-45: Input Bias and Offset

Currents vs. Common Mode Input Voltage, with

TA= +125°C.

FIGURE 2-46: Input Bias and Offset

Currents vs. Ambient Temperature, with

VDD =5.5V.

FIGURE 2-47: Input Bias Current

Magnitude vs. Input Voltage (below VSS).

FIGURE 2-48: Gain Error vs. Ambient

Temperature.

100

105

110

115

120

125

130

135

140

145

150

-50 -25 0 25 50 75 100 125

DC Open-Loop Gain; A

(dB)

Ambient Temperature (°C)

GMIN = 10, VDD = 5.5V

= 1.8V

GMIN = 1, VDD = 5.5V

VDD = 1.8V

GMIN = 100, VDD = 5.5V

VDD = 1.8V

500

600

)

Representative Part

300

400

nts (p

VDD = 5.5V

100

200

Curr

-100

Offse

400

-300

-200

t Bias,

600

-500

400

Inpu

IOS

600

0.00.51.01.52.02.53.03.54.04.55.05.56.0

Common Mode Input Voltage (V)

800

1,000

)

Representative Part

125

400

600

nts (p

125

VDD = 5.5V

200

400

Curr

-200

Offse

600

-400

t Bias,

IOS

1 000

-800

600

Inpu

000

0.00.51.01.52.02.53.03.54.04.55.05.56.0

Common Mode Input Voltage (V)

1000

)

nts (p

| I

100

Curr

Offse

t Bias,

Inpu

25 45 65 85 105 125

Ambient Temperature (°C)

1.E-11

1.E-10

1.E-9

1.E-8

1.E-7

1.E-6

1.E-5

1.E-4

1.E-3

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Bias Current Magnitude (A)

Input Voltage (V)

-40°C

+25°C

+85°C

+125°C

10p

100µ

10µ

1µ

100n

10n

100p

0.08

0.10

GMIN = 100;

1.8V

Representative Parts

004

0.06

1.8V

VDD = 5.5V

0.02

or (%)

-0.02

0.00

in Er

0.06

-0.04

010

-0.08

0.06

GMIN = 1;

VDD = 1.8V

VDD = 5.5V

GMIN = 10;

VDD = 1.8V

VDD = 5.5V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Nanwguengmnal‘: q' a =- Gum- mu

 2014 Microchip Technology Inc. DS20005318A-page 25

MCP6N16

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-49: Gain Error, with GMIN =1.

FIGURE 2-50: Gain Error, with GMIN = 10.

FIGURE 2-51: Gain Error, with GMIN = 100.

14%

16%

405 Samples

MIN

= 1

12%

14%

rrenc

MIN

VDD = 1.8V VDD = 5.5V

10%

Occu

age o

ercen

-0.1

-0.0

0.0

0.1

Gain Error (%)

16%

18%

306 Samples

MIN

= 10

12%

14%

rrenc

MIN

10%

12%

Occu

age o

ercen

DD = 1.8V

DD = 5.5V

-0.1

-0.0

0.0

0.1

Gain Error (%)

16%

18%

386 Samples

MIN

= 100

12%

14%

rrenc

MIN

10%

12%

Occu

age o

ercen

DD = 1.8V

DD = 5.5V

-0.1

-0.0

0.0

0.1

Gain Error (%)

m R. n n n n 4 2 n 9 7 2 ﬂ. 0. 0. > 8552 E. 3.5 5...... 5...». 3% T. v“ . ru m \ I s a. 1. 4. n. ... ... n n. n. 4 a 2 n 1 A A > :5 w 255 .5. 52...... n > 25.5.. .2. 5.5

MCP6N16

DS20005318A-page 26  2014 Microchip Technology Inc.

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

2.2 Other DC Voltages and Currents

FIGURE 2-52: Input Voltage Range

Headroom vs. Ambient Temperature.

FIGURE 2-53: Normalized Differential Input

Voltage Range vs. Ambient Temperature.

FIGURE 2-54: Output Voltage Headroom

vs. Output Current Magnitude.

FIGURE 2-55: Output Voltage Headroom

vs. Ambient Temperature.

FIGURE 2-56: Supply Current vs. Power

Supply Voltage.

FIGURE 2-57: Supply Current vs. Common

Mode Input Voltage.

0.4

1st Wafer Lot

0.2

adro

VIVH –V

0.1

ge H

)

-0.1

0.0

ge Ra

)

-0.2

t Volt

VIVL –V

-0.3

Inp

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

4.0

4.2

)

1st Wafer Lot

MIN

DMH

MIN

DML

3.8

l Inpu

DMH

)

MIN

DMH

MIN

DML

RTO

3.4

erenti

;

MIN

= 1

100

3.0

3.2

d Dif

ange

;

MIN

2.6

2.8

rmaliz

ltage

2.4

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

100

)

100

m (m

VDD = 1.8V

eadro

VDD –V

OH VDD = 5.5V

tage

ut Vo

VOL –V

Out

0.1 1 10

Output Current Magnitude (mA)

100

)

VDD = 5.5V

= 1 k

m (m

VDD –V

eadro

tage

VOL –V

ut Vo

Out

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

1.1

1.2

0.9

1.0

+125

0.7

0.8

ent (

+125

+85°C

+25°C

0.5

0.6

ly Cur

0.3

0.4

Supp

0.1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Power Supply Voltage (V)

1.1

1.2

0.9

1.0

VDD = 1.8V

VDD = 5.5V

0.7

0.8

rent (

0.5

0.6

ly Cur

0.3

Sup

0.1

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Common Mode Input Voltage (V)

m n a .2; .35.

 2014 Microchip Technology Inc. DS20005318A-page 27

MCP6N16

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-58: Output Short-Circuit Current

vs. Power Supply Voltage.

FIGURE 2-59: Power-On Reset Trip

Voltages.

FIGURE 2-60: Power-On Reset Trip

Voltages vs. Temperature.

rent (

it Cu

+125°C

+85

-10

t-Circ

+85

+25°C

-40°C

-20

t Sho

-40

Outp

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Power Supply Voltage (V)

15%

20%

25%

30%

35%

40%

45%

50%

age of Occurrences

VPRH

VPRL

103 Samples

1 Wafer Lot

TA= +25°C

10%

15%

1.20

1.22

1.24

1.26

1.28

1.30

1.32

1.34

1.36

1.38

1.40

Percen

Power-On Reset Trip Voltages (V)

150

1.55

1.60

(V)

1 Wafer Lot

1.40

1.45

ltages

1.30

1.35

1.40

rip Vo

PRH

115

1.20

1.25

eset

VPRL

1.05

1.10

r-On

090

0.95

1.00

Pow

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

4 m 5 m n s 5.6 z, s 320 53323 Emu-u a . . 5. 40¢ 5.5.5.6 m a o o

MCP6N16

DS20005318A-page 28  2014 Microchip Technology Inc.

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

2.3 Frequency Response

FIGURE 2-61: CMRR vs. Frequency.

FIGURE 2-62: PSRR vs. Frequency.

FIGURE 2-63: Open-Loop Gain vs.

Frequency.

FIGURE 2-64: Normalized Gain-Bandwidth

Product vs. Ambient Temperature.

FIGURE 2-65: Phase Margin vs. Ambient

Temperature.

FIGURE 2-66: Closed-Loop Output

Impedance vs. Frequency.

120

130

100

110

(dB)

MRR

100

MIN =

100

GMIN = 10

GMIN = 1

1.E+04 1.E+05 1.E+06

Frequency (Hz)

10k 100k 1M

110

120

100

(dB)

PSRR

100

MIN =

100

GMIN = 10

GMIN = 1

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

1k 10k 100k 1M

240

-210

-180

-150

-120

-90

-60

100

120

Gain Phase; A

(°)

p Gain Magnitude;

| (dB)

AOL;

GMIN = 100

-330

-300

-270

240

-60

-40

-20

1.E+3 1.E+4 1.E+5 1.E+6 1.E+7

Open-Loo

Open-Lo

Frequency (Hz)

GMIN = 10

GMIN = 1

|AOL|;

GMIN = 100

GMIN = 10

GMIN = 1

1k 10k 100k 1M 10M

500

VDD = 5.5V

450

widt

(kHz)

400

n Ban

P/G

300

350

ed Ga

; GB

250

300

rmali

oduc

200

250

MIN =

GMIN = 10

GMIN = 100 VDD = 1.8V

200

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

VDD = 5.5V

)

rgin (

se M

MIN

GMIN = 10

GMIN = 100

VDD = 1.8V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

1.E+3

1.E+4

d-Loop Output

pedance ()

10k

MIN

= 1, 10, 100

1.E+1

1.E+2

1.E+3 1.E+4 1.E+5 1.E+6

Clos

Frequency (Hz)

100

MIN

= 1

MIN

= 10

MIN

= 100

1k 10k 100k 1M

1n vm . 5.5V 9 7 ' m a 5 5 .mn' ’ “‘ an 5 1 5 .mn n an m van-ssv m Inn m n: m '” an E w “‘ an 5 .mn 5n an m vm-ssv 5n .« v. 5n

 2014 Microchip Technology Inc. DS20005318A-page 29

MCP6N16

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-67: Gain Peaking vs.

Normalized Capacitive Load.

FIGURE 2-68: EMIRR vs. Frequency, with

VIN =100mV

PK.

FIGURE 2-69: EMIRR vs. Input Voltage,

with f = 400 MHz.

FIGURE 2-70: EMIRR vs. Input Voltage,

with f = 900 MHz.

FIGURE 2-71: EMIRR vs. Input Voltage,

with f = 1800 MHz.

FIGURE 2-72: EMIRR vs. Input Voltage,

with f = 2400 MHz.

)

MIN

ing (d

=10

MIN

GDM = 1

Peak

GMIN = 100

= 100

MIN

=10

GDM = 10

= 20

Gai

= 100

= 200

= 500

10 100 1,000

Normalized Capacitive Load; C

MIN

(pF)

130

140

VIN = 100 mVPK, at VIP or VREF

120

130

100

110

(dB)

MIR

GMIN = 1

MIN =

GMIN = 100

1.E+07 1.E+08 1.E+09 1.E+10

Frequency (Hz)

10M 100M 1G 10G

130

140

f = 400 MHz

= 5.5V

120

130

at V

REF

100

110

(dB)

MIR

GMIN = 1

GMIN = 10

= 100

at VIP

MIN

= 100

0.01 0.1 1

Input Voltage (V

)

130

140

f = 900 MHz

= 5.5V

120

130

at V

100

110

(dB)

MIR

GMIN = 1

GMIN = 10

= 100

at VREF

MIN

= 100

0.01 0.1 1

Input Voltage (V

)

130

140

f = 1800 MHz

= 5.5V

120

130

at V

REF

100

110

(dB)

REF

MIR

GMIN = 1

GMIN = 10

= 100

at VIP

MIN

= 100

0.01 0.1 1

Input Voltage (V

)

130

140

f = 2400 MHz

= 5.5V

120

130

at VREF

100

110

(dB)

MIR

GMIN = 1

=10

MIN

GMIN = 100

0.01 0.1 1

Input Voltage (V

)

' Rusldunl m pe rum RTI (u E .. 5 n —: >° a "Paw-mm z . V mm \ mm. Mm v . a M wrvvvy anw m ‘ 1m. ‘ \ E A g): o 1 ~ upgwgm h 5 W'W‘V/WWr

MCP6N16

DS20005318A-page 30  2014 Microchip Technology Inc.

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

2.4 Noise

FIGURE 2-73: Input Noise Voltage Density

and Integrated Input Noise Voltage vs.

Frequency.

FIGURE 2-74: Input Noise Voltage Density

vs. Input Common Mode Voltage.

FIGURE 2-75: Intermodulation Distortion

vs. Frequency with VCM Disturbance (see

Figure 1-8).

FIGURE 2-76: Intermodulation Distortion

vs. Frequency with VDD Disturbance

(see Figure 1-8).

FIGURE 2-77: Input Noise Voltage vs.

Time, with 1 Hz and 10 Hz Filters and GMIN =1.

FIGURE 2-78: Input Noise Voltage vs.

Time, with 1 Hz and 10 Hz Filters and GMIN =10.

1.E+5

1.E+6

1.E+3

1.E+4

Input Noise Voltage

P-P

)

ise Voltage Density

(V/¥Hz)

eni;

GMIN = 1

GMIN = 10

GMIN = 100

1µ

20µ

20m

10µ 10m

Eni(0 Hz to f);

GMIN = 1

GMIN = 10

GMIN = 100

1.E+3

1.E+4

1.E+1

1.E+2

1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5

Integrate

Input No

Frequency (Hz)

0.1 1 10 100 1k 10k 100k

100n

10n

100µ

10µ

1E+3

1µ

ensit

f = 100 Hz

tage

MIN

GMIN = 10

GMIN = 100

1E+2

ise Vo

(V/¥

100n

ut No

1E+1

10n

1E+1

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Common Mode Input Voltage (V)

10n

100

ctrum, RTI (µV

)

Residual

100 Hz

Tone

60 Hz

Harmonics

VCM tone = 100 mVPK, f = 100 Hz

IMD

Tone

at DC GMIN = 1

MIN

= 10

0.1

1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5

IMD Sp

Frequency (Hz)

MIN

GMIN = 100

110 100 1k 100k10k

100

Ridl

VDD tone = 100 mVPK, f = 100 Hz

(

µV

)

100 Hz

Tone

IMD

Tone

at DC GMIN = 1

, RTI

(

ctru

MIN

= 10

D Sp

MIN

GMIN = 100

1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5

Frequency (Hz)

110 100 1k 100k10k

ise Voltage; eni(t)

(5 µV/div)

GMIN = 1

NPBW = 10 Hz

0 20 40 60 80 100 120 140 160 180 200

Input N

Time (s)

NPBW = 1 Hz

GMIN = 10

;

(t)

ltage

;

/div)

oise

(0.5 µ

NPBW = 10 Hz

put N

NPBW = 10 Hz

NPBW = 1 Hz

0 20 40 60 80 100 120 140 160 180 200

Time (s)

 2014 Microchip Technology Inc. DS20005318A-page 31

MCP6N16

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-79: Input Noise Voltage vs.

Time, with 1 Hz and 10 Hz Filters and

GMIN = 100.

GMIN = 100

(t)

tage;

iv)

ise Vo

.2 µV/

ut No

(

NPBW = 10 Hz

NPBW = 1 Hz

0 20 40 60 80 100 120 140 160 180 200

Time (s)

a :5 58 a _ 58 4 j 2. s. 4. n. s. 5. 1. 7. a. 1 n 4 4 4 s s s u n. u m m u 5 . __ e> =_ . 3...: 5222.53 a 55.5 a z m cmw=9> G = A 5 5 n n n 7. u w 5 n M 2 u m 5 2 591...; a s

MCP6N16

DS20005318A-page 32  2014 Microchip Technology Inc.

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

2.5 Time Response

FIGURE 2-80: Input Offset Voltage vs.

Time with Temperature Change.

FIGURE 2-81: Input Offset Voltage vs.

Time at Power-Up.

FIGURE 2-82: The MCP6N16 Shows No

Phase Reversal vs. Common Mode Input

Overdrive, with VDD =5.5V.

FIGURE 2-83: The MCP6N16 Shows No

Phase Reversal vs. Differential Input Overdrive,

with VDD =5.5V.

FIGURE 2-84: The MCP6N16 Shows No

Phase Reversal vs. Output Overdrive to VSS.

FIGURE 2-85: The MCP6N16 Shows No

Phase Reversal vs. Output Overdrive to VDD.

100

125

100

NPBW = 1.3 Hz

(°C)

(µV)

ratur

oltag

GMIN = 1

GMIN = 10

MIN

= 100

TSEN

-50

-25

Temp

ffset

MIN

125

-100

-75

enso

put

VOS

175

-150

125

-10

175

0 20 40 60 80 100 120 140 160 180

Time (s)

150

200

GDM = 1000

100

150

(µV)

e (V)

GMIN = 1

GMIN = 10

100

oltag

Volta

MIN =

100

010

ffset

uppl

VOS

-505

nput

ower

150

-100

VDD

150

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Time (ms)

2.7

2.8

2.9

3.0

3.1

3.2

ut Voltage (V)

ode Input Voltage (V)

VDD = 5.5V

VCM

2.4

2.5

2.6

2.7

-1

012345678910

Out

Common

Time (ms)

VOUT;

GMIN = 1

GMIN = 10

GMIN = 100

VDD = 5.5V

)

l Mod

(V)

VDM

tage (

renti

ut Vo

d Diff

ltage;

-1

Out

maliz

put V

VOUT;

-2

MIN

GMIN = 10

GMIN = 100

012345678910

Time (ms)

2.0

2.2

0.0

0.2

1.6

1.8

-0.4

-0.2

)

tial

(V)

GDMVDM

1.4

-0.6

tage (

iffere

VOUT;

GMIN = 1

GMIN = 10

1.0

-1.0

ut Vo

lized

ltage;

GMIN = 100

0.6

-1.4

Out

orm

put V

0.2

-1.8

012345678910

Time (ms)

5.3

5.5

1.8

2.0

4.9

5.1

1.4

1.6

)

ntial

(V)

4.5

4.7

1.0

1.2

ltage (

iffere

;

4.3

4.5

0.8

1.0

ut Vo

lized

ltage

;

OUT;

GMIN = 1

GMIN = 10

100

3.9

0.4

Out

Norm

put V

MIN =

100

3.5

0.0

012345678910

Time (ms)

F7773 mu :3 was: _..> 9.20

 2014 Microchip Technology Inc. DS20005318A-page 33

MCP6N16

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-86: Small Signal Step

Response.

FIGURE 2-87: Large Signal Step

Response.

FIGURE 2-88: Differential Input Overdrive

Recovery vs. Time.

FIGURE 2-89: Differential Input Overdrive

Recovery Time vs. Normalized Gain.

FIGURE 2-90: Output Overdrive Recovery

vs. Time.

FIGURE 2-91: Output Overdrive Recovery

Time vs. Normalized Gain.

V/div)

(10 m

GMIN = 1

GMIN = 10

100

oltag

MIN =

100

tput

0 5 10 15 20 25 30 35 40 45 50

Time (µs)

5.0

5.5

4.0

4.5

)

3.0

3.5

tage (

GMIN = 1

GMIN = 10

2.5

3.0

ut Vo

GMIN = 100

1.5

Out

0.5

0 5 10 15 20 25 30 35 40 45 50

Time (µs)

2.5

3.0

3.5

4.0

4.5

5.0

5.5

ut Voltage (V)

GMIN = 1

GMIN = 10

GMIN = 100

VDD = 5.5V

0.0

0.5

1.0

1.5

0 50 100 150 200 250

Out

Time (µs)

100

1000

110

Differential Input Overdrive

Recovery Time (µs)

Normalized Gain; GDM/GMIN

GMIN = 1

GMIN = 10

GMIN = 100

VDD = 5.5V

5.0

5.5

4.0

4.5

)

3.0

3.5

tage (

MIN

= 1

2.5

3.0

ut Vo

MIN

GMIN = 10

GMIN = 100

1.5

Out

0.5

0 50 100 150 200 250 300 350 400 450 500 550 600

Time (µs)

100

1000

110

Output Overdrive Recovery

Time (µs)

Normalized Gain; G

MIN

GMIN = 1

GMIN = 10

GMIN = 100

VDD = 5.5V

Recovery from VSS and VDD

MCP6N16

DS20005318A-page 34  2014 Microchip Technology Inc.

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

FIGURE 2-92: Power Supply On and Off

and Output Voltage vs. Time.

1.8

2.0

(V)

VL= 0V

1.4

1.6

ltage

1.0

1.2

tput V

MIN

GMIN = 10

GMIN = 100

0.8

1.0

ly, O

0.4

r Sup

VOUT

0.0

Pow

Off Off

0 20 40 60 80 100 120 140 160 180 200

Time (ms)

1 # W , w # 5. , v F x m m u. n. w w <1 3......”="" 1="" l="" «.55="" liza—m="">< 0="" ﬂags.—="" :0="" 4.0.6.2.="" .="" 5.92.3.5="0.0." a:="" .n.2="" .n="" 5="" a="" .="" 23=""> 323m»: :5: 3532.350 = _ _u z

 2014 Microchip Technology Inc. DS20005318A-page 35

MCP6N16

Note: Unless otherwise indicated, TA=+25°C, V

DD = 1.8V to 5.5V, VSS =GND, V

CM =V

DD/2, VDM =0V,

VREF =V

DD/2, VL=V

DD/2, RL=10kΩ to VL, CL=60pF, G

DM =G

MIN and EN = VDD; see Figures 1-7 and 1-8.

2.6 Enable Response

FIGURE 2-93: Enable and Output Voltages

vs. Time, with VDD =1.8V.

FIGURE 2-94: Enable and Output Voltages

vs. Time, with VDD =5.5V.

FIGURE 2-95: Normalized Enable Input

Trip and Hysteresis Voltages vs. Ambient

Temperature.

FIGURE 2-96: Enable Turn-On Time vs.

Ambient Temperature.

FIGURE 2-97: Power Supply Current in

Shutdown vs. Power Supply Voltage.

FIGURE 2-98: Output Leakage Current in

Shutdown vs. Output Voltage.

1.8

2.0

)

VDD = 1.8V

= 0V

1.4

1.6

es (V

)

INA

turns on

INA

turns off

1.0

1.2

Volta

EN VOUT

turns on

turns off

0.6

0.8

utpu

MIN

= 100

0.4

0.6

able,

MIN

GMIN = 10

GMIN = 1

0.0

0 20 40 60 80 100 120 140 160 180 200

Time (µs)

5.5

6.0

)

VDD = 5.5V

= 0V

4.5

5.0

es (V

)

INA INA

3.0

3.5

Volta

turns on turns off

2.0

2.5

3.0

utpu

VOUT

1.0

1.5

able,

GMIN = 1

MIN

0.0

0.5

MIN

GMIN = 100

0 20 40 60 80 100 120 140 160 180 200

Time (µs)

0.7

/V)

VDD = 1.8V

VIH_TRIP/VDD

Input

ges (

0.4

nable

s Volt

VIL_TRIP/VDD

0.3

ized E

teres

VHYST/VDD

0.2

orma

nd Hy

0.1

Trip

VDD = 5.5V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

-50 -25 0 25 50 75 100 125

Enable Turn-On Time (µs)

Ambient Temperature (°C)

GMIN = 1

GMIN = 10

GMIN = 100

VDD =1.8V

VDD =5.5V

GMIN = 1

GMIN = 10

GMIN = 100

2.0

2.5

EN = 0V

1.5

rent

)

0.5

ly Cur

wn (µ

-40°C

+25

IDD

-0.5

0.0

Sup

hutd

+25

+85°C

+125°C

-1.5

-1.0

Powe

-2.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Power Supply Voltage (V)

1.E-7

)

EN = 0V

= 5.5V

100n

1.E-8

nt (A

)

+125°C

10n

1.E-9

Curr

+85°C

1.E-10

eakag

100p

1.E-11

tput

+25°C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Output Voltage (V)

MCP6N16

DS20005318A-page 36  2014 Microchip Technology Inc.

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

3.1 Digital Enable Input (EN)

This input (EN) is a CMOS, Schmitt-triggered input.

When it is low, it puts the part in a low-power state.

When high, the part operates normally. The EN pin

must not be left floating.

3.2 Analog Signal Inputs (VIP

, VIM)

The non-inverting and inverting inputs (VIP and VIM) are

high-impedance CMOS inputs with low bias currents.

3.3 Power Supply Pins (VSS, VDD)

The positive power supply (VDD) is 1.8V to 5.5V higher

than the negative power supply (VSS). For normal

operation, the other pins are between VSS and VDD.

Typically, these parts are used in a single (positive)

supply configuration. In this case, VSS is connected to

ground and VDD is connected to the supply; VDD will

need bypass capacitors.

3.4 Analog Reference Input (VREF)

The analog reference input (VREF) is the non-inverting

input of the second input stage; it shifts VOUT to its

desired range. The external gain resistor (RG) is

connected to this pin. It is a high-impedance CMOS

input with low bias current.

3.5 Analog Feedback Input (VFG)

The analog feedback input (VFG) is the inverting input

of the second input stage. The external feedback

components (RF and RG) are connected to this pin. It is

a high-impedance CMOS input with low bias current.

3.6 Analog Output (VOUT)

The analog output (VOUT) is a low impedance voltage

output. It represents the differential input voltage

(VDM =V

IP –V

IM), with gain G

DM and is shifted by

VREF

. The external feedback resistor (RF) is connected

to this pin.

3.7 Exposed Thermal Pad (EP)

There is an internal connection between the exposed

thermal pad (EP) and the VSS pin; they must be

connected to the same potential on the printed circuit

board (PCB).

This pad can be connected to a PCB ground (VSS)

plane region to provide a larger heat sink. This

improves the package thermal resistance (θJA).

TABLE 3-1: PIN FUNCTION TABLE

MCP6N16

Symbol Description

MSOP DFN

11 EN Enable Input

22 V

IM Inverting Input

33 V

IP Non-inverting Input

44 V

SS Negative Power Supply

55V

REF Reference Input

66 V

FG Feedback Input

77V

OUT Output

88 V

DD Positive Power Supply

— 9 EP Exposed Thermal Pad (EP); must be connected to VSS.

 2014 Microchip Technology Inc. DS20005318A-page 37

MCP6N16

4.0 APPLICATIONS

The MCP6N16 instrumentation amplifier (INA) is

manufactured using Microchip’s state of the art CMOS

process. Its low cost, low power and high speed make

it ideal for battery-powered applications.

4.1 Basic Performance

4.1.1 STANDARD CIRCUIT

Figure 4-1 shows the standard circuit configuration for

these INAs. When the inputs and output are in their

specified ranges, the output voltage is approximately:

EQUATION 4-1:

FIGURE 4-1: Standard Circuit.

For normal operation, keep:

•V

, VIM, VREF and VFG between VIVL and VIVH

•V

IP –V

IM (i.e., VDM) between VDML and VDMH

•V

OUT between VOL and VOH

4.1.2 ANALOG ARCHITECTURE

Figure 4-2 shows the block diagram for these INAs,

without details on chopper-stabilized operation.

FIGURE 4-2: MCP6N16 Block Diagram.

The input signal is applied to GM1. Equation 4-2 shows

the relationships between the input voltages (VIP and

VIM) and the common mode and differential voltages

(VCM and VDM).

EQUATION 4-2:

The negative feedback loop includes GM2, RM4, RF and

. These blocks set the DC open-loop gain (AOL) and

the nominal differential gain (GDM):

EQUATION 4-3:

AOL is very high, so I4 is very small and I1+I

2≈0. This

makes the differential inputs to GM1 and GM2 equal in

magnitude and opposite in polarity. Ideally, this gives:

EQUATION 4-4:

For an ideal part, changing VCM, VSS or VDD produces

no change in VOUT. VREF shifts VOUT as needed.

The different GMIN options change GM1, GM2 and the

internal compensation capacitor. This results in the

performance trade-offs shown in Tabl e 1.

4.1.3 DC ERRORS

Section 1.5 “Explanation of DC Error

Specifications” defines some of the DC error

specifications. These errors are internal to the INA, and

can be summarized as follows:

EQUATION 4-5:

VOUT



VREF +G

DMVDM

Where:

GDM =1+R

F/R

VOUT

VIP

VDD

VIM

VREF

VFG

MCP6N16

VSS

VDD

VIP

VIM

GM1

VIP

VIM

VFG

VOUT

VREF

RM4

GM2

ΣI2

VREF

MCP6N16 RR

VIP VCM VDM 2



VIM VCM VDM 2



–=

VCM VIP VIM

+2



VDM VIP VIM

–=

AOL GM2RM4

GDM 1R

FRG



VFG VREF

–VDM

VOUT VDMGDM VREF

Where:

VOUT VREF GDM 1g

+VDM



VED

++=

DM 1g

+VE



++

Where:

PSRR, CMRR, CMRR2 and AOL are in

units of V/V

∆TA is in units of °C

TC1 is in units of V/°C

VDM =0

VEVOS



VDD



VSS

–

PSRR

---------------------------------



VCM

CMRR

-----------------



VREF

CMRR2

--------------------+++=



VOUT

AOL

-----------------



TATC1





VED INLDM VDMH VDML

–





VEINLCM VIVH VIVL

–



Wu?

MCP6N16

DS20005318A-page 38  2014 Microchip Technology Inc.

The nonlinearity specifications (INLCM and INLDM)

describe errors that are nonlinear functions of VCM and

VDM, respectively. They give the maximum excursion

from linear response over the entire common mode

and differential ranges.

The input bias current and offset current specifications

(IB and IOS), together with a circuit’s external input

resistances, give an additional DC error. Figure 4-3

shows the resistors that set the DC bias point.

FIGURE 4-3: DC Bias Resistors.

The resistors at the main input (RIP and RIM) and its

input bias currents (IBP and IBM) give the following

changes in the INA’s bias voltages:

EQUATION 4-6:

The change in VCM (∆VCM) can affect the input range,

for large RIP or RIM. The best design results when RIP

and RIM are equal and small:

EQUATION 4-7:

The resistors at the feedback input (RR, RF and RG)

and its input bias currents (IBR and IBF) give the

following changes in the INA’s bias voltages:

EQUATION 4-8:

The change in VREF (∆VREF) can affect the input range,

for large RR or RF

. The best design results when

GDMRR and RF are equal (i.e., RR = RF||RG) and small:

EQUATION 4-9:

4.1.4 AC PERFORMANCE

The bandwidth of these amplifiers depends on GDM

and GMIN:

EQUATION 4-10:

The bandwidth at the maximum output swing is called

the Full Power Bandwidth (fFPBW). It is limited by the

Slew Rate (SR) for many amplifiers, but is close to fBW

for these parts:

EQUATION 4-11:

VOUT

VIP

VDD

VIM

VREF

RIP

RIM

IBP

IBM VFG

IBF

IBR

MCP6N16

Where:

CMRR is in units of V/V



VIP IBPRIP

–IBIOS 2



+–RIP



VIM IBMRIM

–IBIOS 2



––RIM



VCM



VIP



VIM

+2



I–BRIP RIM

+2



I–OS RIP RIM

–4





VDM



VIP



VIM

–=

–RIP RIM

–IOS RIP RIM

+2



–=



VOUT GDM



VDM



VCM CMRR



+=

Where:

RIP =RIM



RTOL = tolerance of RIP and RIM



VOUT GDM



VDM



DM 2IB



RTOL IOS

–RIP





VFG



VREF





VOUT IB2 RFGDMRR

–IOS2 RFGDMRR

+2





due to high AOL



VREF IBRRR

–IB2 IOS2 2



+–RR

IB2 meets the IB specification

IOS2 meets the IOS specification

IB2 ≠ IB, in general

IOS2 ≠ IOS, in general

Where:

GDMRR=RF



RTOL = tolerance of RR, RF and RG

VOUT 2IB2RTOL IOS2

+RF



Where:

fBW = -3 dB bandwidth

fGBWP = Gain-Bandwidth product

fBW fGBWP GDM



0.50 MHzGMIN GDM



,



0.35 MHzGMIN GDM



,



GMIN =1, 10

GMIN =100

Where:

VO= Maximum output voltage swing

VOH –V

fFPBW SR









, for these parts

Where:

7GM1+ + , i+ i iiGm i 46 Wﬁﬁ i A2 7 E + + ,GW, 07 . . 7:GA1 r + ,7GA2

 2014 Microchip Technology Inc. DS20005318A-page 39

MCP6N16

4.1.5 NOISE PERFORMANCE

As shown in Figure 2-73, the noise density is white at

low frequencies; the 1/f noise is negligible for almost all

applications. As a result, the time domain data in

Figures 2-77,2-78 and 2-79 is well behaved.

4.2 Overview of Zero-Drift Operation

Figure 4-4 shows a simplified diagram of the MCP6N16

zero-drift INAs. This diagram will be used to explain

how low voltage errors are reduced in this architecture

(much better VOS, TC1 (∆VOS/∆TA), CMRR, CMRR2,

PSRR, AOL and 1/f noise).

FIGURE 4-4: Simplified Zero-Drift INA Functional Diagram.

4.2.1 BUILDING BLOCKS

The Main Amplifiers (GM1 and GM2) are designed for

high gain and bandwidth, with a differential topology.

The main input pairs (+ and - pins at the top left) are for

the higher frequency portion of the input signal. The

auxiliary input pair (+ and - pins at the bottom left of

GM1) is for the low frequency portion of the input signal

and corrects the INA’s input offset voltage. Both inputs

are added together internally.

The Auxiliary Amplifiers (GA1 and GA2), the Chopper

Input Switches and the Chopper Output Switches

provide a high DC gain to the input signal. DC errors

are modulated to higher frequencies and white noise to

low frequencies.

The Low-Pass Filter reduces high-frequency content,

including harmonics of the Chopping Clock.

The Output Buffer (RM4) converts current to voltage

and drives external loads at the VOUT pin.

The Oscillator runs at fCLK = 200 kHz. Its output is

divided by 8, to produce the Chopping Clock rate of

fCHOP =25kHz.

The internal POR part starts the part in a known good

state, protecting against power supply brown-outs. The

Digital Control block outputs clocks and POR events.

4.2.2 CHOPPING ACTION

Figure 4-5 shows the amplifier connections for the first

phase of the Chopping Clock and Figure 4-6 shows

them for the second phase. The slow voltage errors

alternate in polarity, making the average error small.

FIGURE 4-5: First Chopping Clock Phase;

Simplified Diagram.

VIP

VIM GM1

VOUT

RM4

GA1

Chopper

Input

Switches

Chopper

Output

Switches

Oscillator

Low-Pass

Filter

Digital Control

VFG

VREF

GA2

Chopper

Input

Switches

POR

GM2

VIP

VIM

GA1

VFG

VREF

GA2

Low-Pass

Filter

MCP6N16

DS20005318A-page 40  2014 Microchip Technology Inc.

FIGURE 4-6: Second Chopping Clock

Phase; Simplified Diagram.

4.2.3 INTERMODULATION DISTORTION

(IMD)

These INAs will show intermodulation distortion (IMD)

products when an AC signal is present.

The signal and clock can be decomposed into sine

wave tones (Fourier series components). These tones

interact with the zero-drift circuitry’s nonlinear response

to produce IMD tones at sum and difference

frequencies. Each of the square wave clock’s

harmonics has a series of IMD tones centered on it.

See Figures 2-75 and 2-76.

4.3 Other Functional Blocks

4.3.1 RAIL-TO-RAIL INPUTS

Each input stage uses one PMOS differential pair at the

input. The output of each differential pair is processed

using current mode circuitry. The inputs show no

crossover distortion vs. common mode voltage.

With this topology, the inputs (VIP and VIM) operate

normally down to VSS – 0.15V and up to VDD +0.15V

at room temperature (see Figure 2-52). The input offset

voltage (VOS) is measured at VCM =V

SS –0.15V and

VDD + 0.15V (at +25°C) to ensure proper operation.

4.3.1.1 Phase Reversal

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply

voltages. Figure 2-82 shows an input voltage

exceeding both supplies with no phase inversion.

The input devices also do not exhibit phase inversion

when the differential input voltage exceeds its limits;

see Figure 2-83.

4.3.1.2 Input Voltage Limits

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the voltages at

the input pins (see Section 1.1 “Absolute Maximum

Ratings †”). This requirement is independent of the

current limits discussed later on.

The ESD protection on the inputs can be depicted as

shown in Figure 4-7. This structure was chosen to

protect the input transistors against many (but not all)

overvoltage conditions, and to minimize input bias

current (IB).

FIGURE 4-7: Simplified Analog Input ESD

Structures.

The input ESD diodes clamp the inputs when they try

to go more than one diode drop below VSS. They also

clamp any voltages that go too far above VDD; their

breakdown voltage is high enough to allow normal

operation, but not low enough to protect against slow

over-voltage (beyond VDD) events. Very fast ESD

events (that meet the specification) are limited so that

damage does not occur.

VIP

VIM

GA1

VFG

VREF

GA2

Low-Pass

Filter

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIP

VSS

Input

Stage

Bond

Pad VIM

INA Input

 2014 Microchip Technology Inc. DS20005318A-page 41

MCP6N16

In some applications, it may be necessary to prevent

excessive voltages from reaching the INA inputs.

Figure 4-8 shows one approach to protecting these

inputs. D1 and D2 may be small signal silicon diodes,

Schottky diodes for lower clamping voltages or

diode-connected FETs for low leakage.

FIGURE 4-8: Protecting the Analog Inputs

Against High Voltages.

4.3.1.3 Input Current Limits

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

into the input pins (see Section 1.1 “Absolute

Maximum Ratings †”). This requirement is

independent of the voltage limits previously discussed.

Figure 4-9 shows one approach to protecting these

inputs. The resistors R1 and R2 limit the possible

current in or out of the input pins (and into D1 and D2).

The diode currents will dump onto VDD.

FIGURE 4-9: Protecting the Analog Inputs

Against High Currents.

It is also possible to connect the diodes to the left of the

resistor R1 and R2. In this case, the currents through

the diodes D1 and D2 need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (VIP and VIM)

should be very small.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the common

mode voltage (VCM) is below ground (VSS); see

Figure 2-47.

4.3.1.4 Input Voltage Ranges

Figure 4-10 shows possible input voltage values

(VSS = 0V). Lines with a slope of +1 have constant VDM

(e.g., the VDM = 0 line). Lines with a slope of -1 have

constant VCM (e.g., the VCM =V

DD/2 line).

For normal operation, VIP and VIM must be kept within

the region surrounded by the thick blue lines. The

horizontal and vertical blue lines show the limits on the

individual inputs. The blue lines with a slope of +1 show

the limits on VDM; the larger GMIN is, the closer they are

to the VDM = 0 line.

The input voltage range specifications (VIVL and VIVH)

change with the supply voltages (VSS and VDD,

respectively). The differential input range specifications

(VDML and VDMH) change with minimum gain (GMIN).

Temperature also affects these specifications.

FIGURE 4-10: Input Voltage Ranges.

To take full advantage of VDML and VDMH, set VREF

(see Figures 1-7 and 1-8) so that the output (VOUT) is

centered between the supplies (VSS and VDD). Also set

the gain (GDM) to keep VOUT within its range.

VDD

MCP6N16

min(R1,R

2)>VSS –min(V

1,V

2mA

VDD

MCP6N16

min(R1,R

2)> max(V1,V

2)–V

2mA

VIP

VIM

VDM =0

VIVH

VIVL

VIVH

VIVL

VDM=VDMH

VCM =V

DD/2

VDM =V

DML

VDD

MCP6N16

DS20005318A-page 42  2014 Microchip Technology Inc.

4.3.2 ENABLE

This input (EN) is a CMOS, Schmitt-triggered input.

When it is low, it puts the part in a low-power state and

the output is put into a high-impedance state. When

high, the part operates normally.

If the EN pin is left floating, the amplifier will not operate

properly.

4.3.3 RAIL-TO-RAIL OUTPUT

The Minimum Output Voltage (VOL) and Maximum

Output Voltage (VOH) specifications describe the

widest output swing that can be achieved under the

specified load conditions.

The output can also be limited when VIP or VIM exceeds

VIVL or VIVH or when VDM exceeds VDML or VDMH.

4.4 Applications Tips

4.4.1 INPUT OFFSET VOLTAGE OVER

TEMPERATURE

Table 1 gives both the linear and quadratic temperature

coefficients (TC1 and TC2) of input offset voltage. The

input offset voltage can be estimated as follows:

EQUATION 4-12:

These specifications show these INA’s intrinsic

performance. The plots of input offset voltage versus

temperature on the second page (Figures 1 to 3) show

the typical behavior for a few parts from the first wafer

lot.

In most designs, other effects will dominate the circuit

temperature performance; see Section 4.4.13 “PCB

Design for DC Precision” for more details.

4.4.2 NOISE EFFECT ON OFFSET

VOLTAGE

The input noise (eni) makes measured offset values

(VOS) vary in a random manner. Lower noise requires

a lower noise power bandwidth (NPBW; see AN1228,

mentioned in 5.3 “Application Notes”), which

increases measurement time. In the offset-related

specifications (AOL, CMRR, CMRR2 and PSRR) and

plots, the various values of NPBW were chosen to

trade off time versus accuracy of results.

4.4.3 DC GAIN PLOTS

Figures 2-28 to 2-39 are histograms of the reciprocals

(in units of µV/V) of CMRR, PSRR and AOL,

respectively. They represent the change in input offset

voltage (VOS) with a change in common mode input

voltage (VCM), power supply voltage (VDD) and output

voltage (VOUT).

The 1/AOL histogram is centered near 0 µV/V because

the measurements are dominated by the INA’s input

noise. The negative values shown represent noise and

tester limitations, not unstable behavior. Production

tests make multiple VOS measurements, which

validates an INA's stability; an unstable part would

show greater VOS variability, or the output would stick

at one of the supply rails.

4.4.4 OFFSET AT POWER-UP

When these parts power up, the input offset (VOS)

starts at its uncorrected value (usually less than

±10 mV). Circuits with high DC gain can cause the

output to reach one of the two rails. In this case, the

time to a valid output is delayed by an output overdrive

time (like tODR), in addition to a start-up time (like tSTR).

It can be simple to avoid this extra start-up time.

Reducing the gain is one method. Adding a capacitor

across the feedback resistor (RF) is another method.

4.4.5 SOURCE RESISTANCES

The input bias currents have two significant

components: switching glitches that dominate at room

temperature and below, and input ESD diode leakage

currents that dominate at +85°C and above.

Make the resistances seen by the inputs small and

equal. This minimizes the output offset caused by the

input bias currents.

The inputs should see a resistance on the order of 10Ω

to 1 kΩ at high frequencies (i.e., above 1 MHz). This

helps minimize the impact of switching glitches, which

are very fast, on overall performance. In some cases, it

may be necessary to add resistors in series with the

inputs to achieve this improvement in performance.

Small input resistances at the inputs may be needed for

high gains. Without them, parasitic capacitances might

cause positive feedback and instability.

4.4.6 SOURCE CAPACITANCE

The capacitances seen by the inputs should be small.

Large input capacitances and source resistances,

together with high gain, can lead to positive feedback

and instability.

VOS TA

 VOS TC1



TTC



++=

Where:

TA= -40°C to +125°C

∆T=T

A–25°C

VOS(TA) = Input offset voltage at TA

VOS = Input offset voltage at +25°C

TC1= Linear temperature coefficient

TC2= Quadratic temperature coefficient

 2014 Microchip Technology Inc. DS20005318A-page 43

MCP6N16

4.4.7 MINIMUM STABLE GAIN

There are three options for different Minimum Stable

Gains (1, 10 and 100 V/V; see Ta b l e 1 ). The differential

gain (GDM) needs to be greater than or equal to GMIN

in order to maintain stability.

Picking a part with higher GMIN has the advantages of

lower input noise voltage density (eni), lower input

offset voltage (VOS) and increased gain-bandwidth

product (GBWP). The differential input voltage range

(VDML and VDMH) is lower for higher GMIN, but supports

a reasonable output voltage range.

4.4.8 CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage amplifiers. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth

reduces. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. Lower gains (GDM) exhibit greater sensitivity

to capacitive loads.

When driving large capacitive loads with these

instrumentation amps (e.g., > 80 pF), a small series

resistor at the output (RISO in Figure 4-11) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

FIGURE 4-11: Output Resistor, RISO

Stabilizes Large Capacitive Loads.

Figure 4-12 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CLGMIN/GDM), where

GDM is the circuit’s differential gain (1 + RF/RG) and

GMIN is the minimum stable gain.

FIGURE 4-12: Recommended RISO Values

for Capacitive Loads.

After selecting RISO for the circuit, double check the

resulting frequency response peaking and step

response overshoot on the bench. Modify RISO’s value

until the response is reasonable.

4.4.9 GAIN RESISTORS

Figure 4-13 shows a simple gain circuit with the INA’s

input capacitances at the feedback inputs (VREF and

VFG). These capacitances interact with RG and RF to

modify the gain at high frequencies. The equivalent

capacitance acting in parallel to RG is CG=C

DM +C

plus any board capacitance in parallel to RG

. CG will

cause an increase in GDM at high frequencies, which

reduces the phase margin of the feedback loop (i.e.,

reduce the feedback loop’s stability).

FIGURE 4-13: Simple Gain Circuit with

Parasitic Capacitances.

RISO

VOUT

VDD

VREF

VFG

MCP6N16

1,000

()

ed R

men

Reco

100

10p

100

10 100 1,000 10,000

Normalized Load Capacitance; C

MIN

(F)

10p 100p 1n 10n

10p

VOUT

VDD

VREF

VFG

CDM

CCM

MCP6N16

DS20005318A-page 44  2014 Microchip Technology Inc.

In this data sheet, RF+R

G=10kΩ for most gains (0Ω

for GDM = 1); see Table 1-6. This choice gives good

phase margin. In general, RF (Figure 4-13) needs to

meet the following limits to maintain stability:

EQUATION 4-13:

4.4.10 EMI REJECTION RATIO (EMIRR)

Electromagnetic interference (EMI) can be coupled to

an INA through electromagnetic induction or radiation,

or by conduction. INAs are most sensitive to EMI at

their input pins.

EMIRR describes an INA’s EMI robustness. Internal

passive filters in these parts improve the EMIRR, when

good PCB layout techniques are used. EMIRR is

defined to be:

EQUATION 4-14:

4.4.11 REDUCING UNDESIRED NOISE

AND SIGNALS

Reduce undesired noise and signals with:

• Low bandwidth signal filters:

- Minimizes random analog noise

- Reduces interfering signals

• Good PCB layout techniques:

- Minimizes crosstalk

- Minimizes parasitic capacitances and

inductances that interact with fast switching

edges

• Good power supply design:

- Isolation from other parts

- Filtering of interference on supply line(s)

4.4.12 SUPPLY BYPASS

With these INAs, the Power Supply pin (VDD for single

supply) should have a local bypass capacitor (i.e.,

0.01 µF to 0.1 µF) within 2 mm for good high-frequency

performance. Surface mount, multilayer ceramic

capacitors, or their equivalent, should be used.

These INAs require a bulk capacitor (i.e., 1.0 µF or

larger) within 100 mm to provide large, slow currents.

This bulk capacitor can be shared with other nearby

analog parts as long as crosstalk through the supplies

does not prove to be a problem.

4.4.13 PCB DESIGN FOR DC PRECISION

In order to achieve DC precision on the order of ±1 µV,

many physical errors need to be minimized. The design

of the printed circuit board (PCB), the wiring, and the

thermal environment have a strong impact on the

precision achieved. A poor PCB design can easily be

more than 100 times worse than the MCP6N16 op

amps’ minimum and maximum specifications.

4.4.13.1 PCB Layout

Any time two dissimilar metals are joined together, a

temperature dependent voltage appears across the

junction (the Seebeck or thermojunction effect). This

effect is used in thermocouples to measure

temperature. The following are examples of

thermojunctions on a PCB:

• Components (resistors, INAs, …) soldered to a

copper pad

• Wires mechanically attached to the PCB

• Jumpers

• Solder joints

•PCB vias

Typical thermojunctions have temperature to voltage

conversion coefficients of 1 to 100 µV/°C (sometimes

higher).

Microchip’s AN1258 (“Op Amp Precision Design: PCB

Layout Techniques” – DS01258) contains in-depth

information on PCB layout techniques that minimize

thermojunction effects. It also discusses other effects,

such as crosstalk, impedances, mechanical stresses

and humidity.

4.4.13.2 Crosstalk

DC crosstalk causes offsets that appear as a larger

input offset voltage. Common causes include:

• Common mode noise (remote sensors)

• Ground loops (current return paths)

• Power supply coupling

Interference from the mains (usually 50 Hz or 60 Hz),

and other AC sources, can also affect the DC

performance. Nonlinear distortion can convert these

signals to multiple tones, including a DC shift in voltage.

Where:



0.25

GDM



GMIN

fGBWP = Gain-Bandwidth Product

CG=C

DM +C

CM + (PCB stray capacitance)

RF0=

For GDM =1:



GDM



fGBWPCG

------------------------------



For GDM >1:

EMIRR dB 20 VRF



VOS

-------------





log



Where:

VRF = Peak Input Voltage of EMI (VPK)

∆VOS = Input Offset Voltage Shift (V)

 2014 Microchip Technology Inc. DS20005318A-page 45

MCP6N16

When the signal is sampled by an ADC, these AC

signals can also be aliased to DC, causing an apparent

shift in offset.

To reduce interference:

- Keep traces and wires as short as possible

- Use shielding

- Use ground plane (at least a star ground)

- Place the input signal source near to the DUT

- Use good PCB layout techniques

- Use a separate power supply filter (bypass

capacitors) for these zero-drift INAs

4.4.13.3 Miscellaneous Effects

Keep the resistances seen by the input pins as small

and as near to equal as possible, to minimize bias

current-related offsets.

Make the (trace) capacitances seen by the input pins

small and equal. This is helpful in minimizing switching

glitch-induced offset voltages.

Bending a coax cable with a radius that is too small

causes a small voltage drop to appear on the center

conductor (the triboelectric effect). Make sure the

bending radius is large enough to keep the conductors

and insulation in full contact.

Mechanical stresses can make some capacitor types

(such as some ceramics) output small voltages. Use

more appropriate capacitor types in the signal path and

minimize mechanical stresses and vibration.

Humidity can cause electrochemical potential voltages

to appear in a circuit. Proper PCB cleaning helps, as

does the use of encapsulants.

4.5 Typical Applications

4.5.1 HIGH INPUT IMPEDANCE

DIFFERENCE AMPLIFIER

Figure 4-14 shows the MCP6N16 used as a difference

amplifier. The inputs are high-impedance and give

good CMRR performance.

FIGURE 4-14: Difference Amplifier.

4.5.2 DIFFERENCE AMPLIFIER FOR

VERY LARGE COMMON MODE

SIGNALS

Figure 4-15 uses the MCP6N16 INA as a difference

amplifier for signals with a very large common mode

component. The input resistor dividers (R1 and R2)

ensure that the INA’s inputs are within their normal

range of operation. The capacitors (C1 and C2) set the

same voltage division ratio for high-frequency signals

(e.g., a voltage step). C2 includes the INA’s CCM. R1

and R2’s tolerances affect CMRR.

FIGURE 4-15: Difference Amplifier with

Very Large Common Mode Component.

4.5.3 RTD TEMPERATURE SENSOR

Figure 4-16 shows an RTD temperature sensor circuit,

which measures over the -55°C to +155°C range. The

sensor chosen changes from 78Ω to 159Ω over this

range. The 2.49 kΩ and 4.99 kΩ resistors set the

current through the RTD and 68.1Ω resistor. The INA

provides a high-differential gain. The 10 µF capacitor

filters common mode interference on the bridge.

FIGURE 4-16: RTD Temperature Sensor.

VOUT

VIP

VDD

VIM

VREF

VFG

MCP6N16

VOUT

VDD

VREF

VFG

C1C2

MCP6N16

VOUT

20 kΩ

100Ω

2.49 kΩ

68.1ΩRTD

4.99 kΩ

VDD

MCP6N16-100

10 µF

100Ω

4.99 kΩ4.99 kΩ

MCP6N16

DS20005318A-page 46  2014 Microchip Technology Inc.

4.5.4 WHEATSTONE BRIDGE

Figure 4-17 shows the MCP6N16 INA used to

condition the signal from a Wheatstone bridge (e.g.,

strain gage). The overall INA gain is set at 1001 V/V.

The best GMIN option to pick, for this gain, is 100 V/V

(MCP6N16-100).

FIGURE 4-17: Wheatstone Bridge

Amplifier.

4.5.5 HIGH SIDE CURRENT DETECTOR

Figure 4-18 shows the MCP6N16 INA used to detect

and amplify the high side current in a power supply

design. U1’s low offset voltage makes it possible to

reduce RSH, which saves power and minimizes

temperature effects. U1’s supply current is included in

the measurement. The INA’s gain is set at 101 V/V, so

VOUT changes 1.01V for every 1A change in IDD.

FIGURE 4-18: High Side Current Detector.

VOUT

VREF

VFG

100 kΩ

VDD

RW1

RW2

RW1 U1

MCP6N16-100

10 µF

100Ω

RSH

VPS = +1.8V to 5.5V

VOUT

VREF

VFG

10.0 kΩ

100Ω

MCP6N16-100

VPS

IPS

IDD

IPS =I

L+I

IPS =(V

PS –V

L)/(10 mΩ)

=(V

OUT –V

REF)/((10 mΩ)(101V/V))

10 mΩ

 2014 Microchip Technology Inc. DS20005318A-page 47

MCP6N16

5.0 DESIGN AIDS

Microchip provides the basic design aids needed for

the MCP6N16 instrumentation amplifiers.

5.1 Microchip Advanced Part Selector

(MAPS)

MAPS is a software tool that helps efficiently identify

Microchip devices that fit a particular design

requirement. Available at no cost from the Microchip

website at www.microchip.com/maps, the MAPS is an

overall selection tool for Microchip’s product portfolio

that includes Analog, Memory, MCUs and DSCs. Using

this tool, a customer can define a filter to sort features

for a parametric search of devices and export

side-by-side technical comparison reports. Helpful links

are also provided for Data sheets, Purchase and

Sampling of Microchip parts.

5.2 Analog Demonstration Board

Microchip offers a broad spectrum of Analog

Demonstration and Evaluation Boards that are

designed to help customers achieve faster time

to market. For a complete listing of these boards

and their corresponding user’s guides and technical

information, visit the Microchip web site at

www.microchip.com/analog tools.

5.3 Application Notes

The following Microchip Application Notes are

available on the Microchip web site at

www.microchip.com/appnotes and are recommended

as supplemental reference resources.

•AN884: “Driving Capacitive Loads With Op

Amps”, DS00884

•AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

•AN1177: “Op Amp Precision Design: DC

Errors”, DS01177

•AN1228: “Op Amp Precision Design: Random

Noise”, DS01228

• AN1258: “Op Amp Precision Design: PCB Layout

Techniques”, DS01258

Some of these application notes, and others, are listed

in the design guide:

•“Signal Chain Design Guide”, DS21825

NNN

MCP6N16

DS20005318A-page 48  2014 Microchip Technology Inc.

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC® designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Product Number Code

MCP6N16-001E/MF DADV

MCP6N16T-001E/MF DADV

MCP6N16-010E/MF DADW

MCP6N16T-010E/MF DADW

MCP6N16-100E/MF DADX

MCP6N16T-100E/MF DADX

DADV

1423

256

8-Lead MSOP (3x3 mm) Example

8-Lead DFN (3x3 mm) Example

N16010

423256

8-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9mm Body [DFN] SEATWNG PLANE (A3) — NOTE 1 7 TOP VIEW // // 4-90;. (DATUM A) (DATUM B) AIBI _ 007 ‘ axn $005g BOTTOM VIEW chmchip Techno‘ogy Drawing No (20470626 SheeM cl:

 2014 Microchip Technology Inc. DS20005318A-page 49

MCP6N16

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

8-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9mm Body [DFN] NOTE 2 Unns MILLIMETERS Dimenslon Lnnils MlN l NOM l MAX Number 01 Pins N 8 Pllcn e 0.55 BSC Overall Helght A 0.30 0.90 1.00 Slandoll A1 0.00 0.02 0.05 Contact Thlckness A3 0 20 REF Overall Lengln D 3.00 550 Exposed Pad Wldm E2 1.34 l . l 1.60 Overall Widln E 3.00 BSC Exposed Pad Lengm 02 1.50 . 2.40 Comacthdth b 0.25 0.30 0.35 Conlael Lenglh L 0.20 0.30 0.55 Comacl-lo-Exposed Pad K 0.20 . . Noles. 1. Pin 1 ylsual lndex lealure may vary, om must be located Wltl’llrl (he hatched area. 2 Package may have one or more exposed lle bars at ends 3. Package IS saw slngulaled 4. Dlmensionlng and Iolerancing per ASME Yl4.5M 580 Basic Dimensmn. Theoreneally exael value shown wilhoul leleranoes. REF Relerence Dlmenslon, usually wlthoul lolerance, for lnfcrmallon purposes only Mlcrochip Technology Drawlng No. 00470620 sneel 2 012

MCP6N16

DS20005318A-page 50  2014 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

8-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9mm Body [DFN] WZ SILK SCREEN RECOMMENDED LAND PATTERN Umts MILUMETERS Dtmension Ltmtts MIN | NOM \ MAX Contact Fttcn E 0.65 850 Opttonal Center Pad Wtdtn W2 2.40 Opuonal Center Pad Length 12 1.55 Contact Pad Spacmg (:1 3.10 Contact Fad Width (xe) x1 0.35 Contact Fad Length (X8) W 0.55 Di5|anoe Between Pads 6 0 so Notes: 1 Dimenstoning and toterancing per ASME v14 5M BSC Easlc Dlmenston Theorehca‘ly exact value shown wtthoui lo‘erances Mlcmcmp Technology Drawmg Nu. 504-20525

 2014 Microchip Technology Inc. DS20005318A-page 51

MCP6N16

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

8-Lead Plastic Micro Small Outline Package (MS) [MSOP] l—l 2X |ﬂ QDZDH E .7 NX b ---E TOP VIEW Q 010 C _ SEATING PLANE _T—l J SIDE VIEW A1 * j/ SEE DETAlLC _ ﬁx END VIEW Microchlp Technology Drawmg C0441“; Sheet 1 cl 2

MCP6N16

DS20005318A-page 52  2014 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

B-Lead Plastic Micro Small Outline Package (MS) [MSOP] SEATING PLANE Notes: _ _GAUGE PLANE 0L L ‘P (U) DETAIL c Unrls MILLlMETERS Dlmension errls MlN NOM MAX Number oi Plns N | a l Pllch e 0 65 830 Overall Helghl A - - 1 10 Molded Package Thickness A2 0 75 D 85 0 95 Standoff Al 0 DD - 0 15 Overall Width E 4 90 BSC Molded Package Wldlh El 3 00 880 Overall Length D 3 00 BSC Fool Lengln L o 40 | 0 60 l 0 so Footprint L1 0 95 REF Fool Angle W 0“ , 8" Lead Thickness c o as , o 23 Lead width b o 22 , 0 4o 1 Pin 1 visual index leatuve may vary‘ bul musl be localed wrlnrn lhe hatched area 2 Dimenslons D and El do ncl include mold llasn or prolrusions. Mold ﬂash or protrusions shall not exceed 0.15mi per side 3 Dimensrdning and lolerarlclng per ASME v14 5M asc. Basre Dlmension. Thearellcally exacl value sndwn wimdul tolerances. REF: Relerence Dlmenslnnr usually without tolerance, lor inlormation purposes only. Microchip Technology Drawlng 004711“: Sheet 2 on

 2014 Microchip Technology Inc. DS20005318A-page 53

MCP6N16

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

S-Lead Plastic Micro Small Outline Package (MS) [MSOP] ><—»‘><_ iiﬂue—g="" ’*="" ”="" '="" \="" silk="" _—.="" screen="" i="" l="" —=""><—gx eiel="" recommended="" land="" pattern="" units="" millimeters="" dimension="" liinits="" mln="" l="" nom="" l="" max="" contact="" pitch="" e="" 0.65="" bsc="" contact="" pad="" spacing="" c="" a="" 40="" overall="" width="" 2="" 5.55="" contact="" pad="" width="" (xa)="" x1="" 0.45="" contact="" pad="" length="" (x8)="" y1="" 1.45="" distance="" between="" pads="" 61="" 2.95="" distance="" between="" pads="" gx="" 0.20="" notes="" 1="" dimensiuning="" and="" tolerancing="" perasme="" y14="" sm="" 550.="" basic="" dimensiun.="" theoretically="" exact="" value="" shown="" wilhuul="" tolerances.="" microchip="" technology="" drawing="" no="" (20472111a="">

MCP6N16

DS20005318A-page 54  2014 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2014 Microchip Technology Inc. DS20005318A-page 55

MCP6N16

APPENDIX A: REVISION HISTORY

Revision A (July 2014)

• Original Release of this Document.

PART No. v L)? -xxx T lxx

MCP6N16

DS20005318A-page 56  2014 Microchip Technology Inc.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP6N16 Single Instrumentation Amplifier

MCP6N16T Single Instrumentation Amplifier

(Tape and Reel)

Gain Option: 001 = Minimum gain of 1 V/V

010 = Minimum gain of 10 V/V

100 = Minimum gain of 100 V/V

Temperature Range: E = -40°C to +125°C

Package: MF = Plastic Dual Flat, no lead Package - 3×3x0.9 mm

Body, 8-lead (DFN)

MS = Plastic Micro Small Outline Package, 8-lead (MSOP)

Examples:

a) MCP6N16T-001E/MF: Tape and Reel,

Minimum gain =1,

Extended temperature,

8LD 3×3 DFN

b) MCP6N16-010E/MS: Minimum gain =10,

Extended temperature,

8LD MSOP

PART NO. X/XX-XXX

Gain PackageTemperature

Range

Device

Option

[X](1)

Tape and Reel

Option

Note 1: Tape and Reel identifier only appears in the

catalog part number description. This identi-

fier is used for ordering purposes and is not

printed on the device package. Check with

your Microchip Sales Office for package

availability with the Tape and Reel option.

YSTEM

 2014 Microchip Technology Inc. DS20005318A-page 57

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,

KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,

MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code

Generation, PICDEM, PICDEM.net, PICkit, PICtail,

RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-63276-377-8

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

6‘ MICRDCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE

DS20005318A-page 58  2014 Microchip Technology Inc.

AMERICAS

Corporate Office

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Technical Support:

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Web Address:

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Worldwide Sales and Service

03/25/14

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