TS68C000 Datasheet by Microchip Technology

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41m —®
Features
•16-/32-bit Data and Address Register
•16-Mbyte Direct Addressing Range
•56 Powerful Instruction Types
•Operations on Five Main Data Types
•Memory Mapped Input/Output
•14 Addressing Modes
•Three Available Versions: 8 MHz/10 MHz and 12.5 MHz
•Military Temperature Range: -55/+125°C
•Power Supply: 5VDC ± 10%
Description
The TS68C000 reduced power consumption device dissipates an order of magnitude
less power than the HMOS TS68000. The TS68C000 is an implementation of the
TS68000 16/32 microprocessor architecture. The TS68C000 has a 16-bit data bus
and 24-bit address bus while the full architecture provides for 32-bit address and data-
buses. It is completely code-compatible with the HMOS TS68000, TS68008 8-bit data
bus implementation of the TS68000 and the TS68020 32-bit implementation of the
architecture. Any user-mode programs written using the TS68C000 instruction set will
run unchanged on the TS68000, TS68008 and TS68020. This is possible because the
user programming model is identical for all processors and the instruction sets are
proper sub-sets of the complete architecture.
Screening/Quality
This product is manufactured in full compliance with:
•MIL-STD-883 class B
•DESC drawing 5962-89462
•Atmel standards
F Suffix
CQFP 68
Ceramic Quad Flat Pack (on request)
C Suffix
DIL 64
Ceramic Package
E Suffix
LCCC 68
Leadless Ceramic Chip Carrier
R Suffix
PGA 68
Pin Grid Array
Low Power
HCMOS
16-/32-bit
Hi-Rel
Microprocessor
TS68C000
Rev. 2170A–HIREL–09/05
TC68C000
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2170A–HIREL–09/05
TC68C000
1. General Description
1.1 Introduction
This detail specification contains both a summary of the TS68C000 as well as detailed set of
parametrics. The purpose is twofold to provide an instruction to the TS68C000 and support for
the sophisticated user. For detail information on the TS68C000, refer to "68000 16-bit micropro-
cessor user’s manual".
1.2 Detailed Block Diagram
The functional block diagram is given in Figure 1-1 below.
Figure 1-1. Block Diagram
Clock Gen.
and
Timing Control
Control
Store
M Store
N Store Alu Function
and Reg
Selection
Instruction
Decode
Internal
Control
bus
Instruction
Register
Interrupt
Control
Address High
Execution Unit
and Registers
16-bit
Alu
16-bit
Alu
16-bit
Alu
Address Low
Execution Unit
and Registers
Data Execution
Unit
and Registers
Addr.
Bus
Buffer
Data
Bus
Buffer
DATA BUS
ADDRESS BUS
16-bit
Data
Bus
System
Control
Signals
32-bit
Address
Bus
Bus
Control
Logic
Status
and
Control
Clock
VCC
VGND
:jjjjjjjjjjjjjjjjj3333333333333: \. D::::: T ,C 7|: C A lllEl
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2170A–HIREL–09/05
TS68C000
1.3 Pin Assignments
Figure 1-2. 64-lead Dual-in-Line Package
CLK
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
GND
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
AS
UDS
LDS
R/W
DTACK
BG
BGACK
BR
VCC
GND
HALT
RESET
VMA
E
VPA
BERR
IPL2
IPL0
IPL1
FC2
FC1
FC0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
46
47
45
44
43
42
41
40
39
38
37
36
35
34
33
TOP VIEW
Index
JJJJJJJJJJJJJJJJJ 6 3 ”a; mm 9 u :< mm="" 3="" no;="" «a="" av="">< mm="" mm="" um?="" mm="" mm="" u?="" e="" 8="" u?="" mm="" mm="">< _="" mm="" 52="" va="" u?="" mm="" u?="" 8="" u="" 2="" .m="" “.02="" em="" ”—00“.="" e="" u="" 5;="" ma="" uwom="" 1/="" \="" r="" u="" 3”:="" oooooooo="" oooooooo="" of="" o,="" o,="" o,="" of="" o="" omoiw,="" k="" 9="" o="" o="" o="" o="" o="" o="" o="" o="" o="" o="" 070307090="" mmemme="" \="" dtack="" i:="" 10="" bhus="" ei:22="" vcctm="" nona="" fixm="">
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2170A–HIREL–09/05
TC68C000
Figure 1-3. 68-terminal Pin Grid Array
Figure 1-4. 68-lead Quad Pack
NC
E
VMA
HALT
CLK
BR
BGACK
DTACK
NC
FC2
RESET
GND
V
CC
BG
AS
FC0
FC1
R/W
UDS
D1
A1
NC
D0
D2
A3
A2
A4
A5
A6
A8
A7
A10
A13
D3
D4
D6
D5
D9
D7
D11
D8
D13
A9
A11
A12
A15
A18
VCC
GND
A23
D14
D10
NC
A14
A16
A17
A19
A20
A21
A22
D15
D12
BERR IPL0
IPL2 IPL1
VPA
BOTTOM VIEW
1 2 34 56789 10
A
B
C
D
E
F
G
H
J
L
LDS
Index
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DTACK
BG
BGACK
BR
VCC
CLK
GND
GND
NC
HALT
RESET
VMA
E
VPA
BERR
IPL2
IPL1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
IPL0
FC2
FC1
FC0
NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
D13
D14
D15
GND
GND
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
R/W
LDS
UDS
AS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
TOP VIEW
Index
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TS68C000
Figure 1-5. 68-ceramic Quad Flat Pack
1.4 Terminal Designations
The function, category and relevant symbol of each terminal of the device are given in the follow-
ing table.
DTACK
BG
BGACK
BR
VCC
CLK
GND
GND
NC
HALT
RESET
VMA
E
VPA
BERR
IPL2
IPL1
IPL0
FC2
FC1
FC0
NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
D13
D14
D15
GND
GND
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
R/W
LDS
LDS
AS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
TOP VIEW
Index
1
17
18 34
35
51
68 52
Table 1-1. Terminal Designations
Symbol Function Category
VCC Power supply (2 terminals) Supply
VSS(1) Power supply (2 terminals) Terminals
FC0 to FC2 Processor status Outputs
IPL0 to IPL2 Interrupt control Inputs
A1 to A23 Address bus Outputs
AS
Asynchronous bus control Outputs
R/W
UDS
LDS
DTACK Input
BR
Bus arbitration control Inputs
BGACK
BG Output
4» S CLK 4,» T> 4* T» 4* DTACK <7><77 (t="" *9="" fl,="" 4*="" :=""> <7><:> <7 4—»="" h="">
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2170A–HIREL–09/05
TC68C000
Note: 1. VSS is the reference terminal for the voltages
1.5 Signal Description
The input and output signals are illustrated functionally in Figure 1-6 and are described in the fol-
lowing paragraphs.
Figure 1-6. Input and Output Signals
BERR
System control
Input
RESET Input/Output
HALT
VPA
6800 peripheral control
Input
VMA Output
E Output
CLK Clock Input
D0 to D15 Data bus Input/Output
Table 1-1. Terminal Designations (Continued)
Symbol Function Category
Table 1-2. Data Strobe Control of Data Bus
UDS LDS R/W D8-D15 D0-D7
High High No valid data No valid data
Low Low High Valid data bits 8-15 Valid data bits 0-7
High Low High No valid data Valid data bits 0-7
Low High High Valid data bits 8-15 No valid data
Low Low Low Valid data bits 8-15 Valid data bits 0-7
High Low Low Valid data bits 0-7 Valid data bits 0-7
Low High High Valid data bits 8-15 Valid data bits 8-15
GND
CLK
ADDRESS
BUS
DATA BUS
AS
R/W
UDS
LDS
DTACK
ASYNCHRONOUS
BUS
CONTROL
BR
BG
BGACK
IPL1
IPL2
INTERRUPT
CONTROL
BUS
ARBITRATION
CONTROL
FC1
FC2
E
VMA
VPA
BERR
RESET
HALT
PROCESSOR
STATUS
PERIPHERAL
CONTROL
SYSTEM
CONTROL
IPL0
FC0
A1 - A23
D0 - D15
VCC
MICROPROCESSOR
41m
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2170A–HIREL–09/05
TS68C000
1.5.0.1 Address Bus (A1 through A23)
This 24-bit, unidirectional, three-state bus is capable of addressing 16 megabytes of data. It pro-
vides the address for bus operation during all cycles except interrupt cycles. During interrupt
cycles, address lines A1, A2 and A3 provide information about what level interrupt is being ser-
viced while address lines A4 through A23 are set to a logic high.
1.5.0.2 Data Bus (D0 Through D15)
This 16-bit, bidirectional, three-state bus is the general-purpose data path. It can transfer and
accept data in either word or byte length. During an interrupt acknowledge cycle, the external
device supplies the vector number on data lines D0-07.
1.5.0.3 Asynchronous Bus Control
Asynchronous data transfers are handled using the following control signals: address strobe,
read/write, upper and lower data strobes, and data transfer acknowledge. These signals are
explained in the following paragraphs.
ADDRESS STROBE (AS)
This signal indicates that there is a valid address on the address bus.
READ/WRITE (R/W)
This signal defines the data bus transfer as a read or write cycle. The R/W signal also works in
conjunction with the data strobes as explained in the following paragraph.
UPPER AND LOWER DATA STROBE (UDS, LDS)
These signals control the flow of data on the data bus, as shown in Table 1-2. When the R/W
line is high, the processor will read from the data bus as indicated. When the R/W line is low, the
processor will write to the data bus as shown.
DATA TRANSFER ACKNOWLEDGE (DTACK)
This input indicates that the data transfer is completed. When the processor recognizes DTACK
during a read cycle, data is latched and the bus cycle terminated. When DTACK is recognized
during a write cycle, the bus cycle is terminated.
1.5.0.4 Bus Arbitration Control
The three signals, bus request, bus grant, and bus grant acknowledge, form a bus arbitration cir-
cuit to determine which device will be the bus master device.
BUS REQUEST (BR)
This input is wire ORed with all other devices that could be bus masters. This input indicates to
the processor that some other device desires to become the bus master.
BUS GRANT (BG)
This output indicates to all other potential bus master devices that the processor will release bus
control at the end of the current bus cycle.
BUS GRANT ACKNOWLEDGE (BGACK)
This input indicates that some other device has become the bus master.
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2170A–HIREL–09/05
TC68C000
This signal should not be asserted until the following four conditions are met:
1. a bus grant has been received,
2. address strobe is inactive which indicates that the microprocessor is not using the bus,
3. data transfer acknowledge is Inactive which indicates that neither memory nor peripher-
als are using the bus, and
4. bus grant acknowledge is inactive which indicates that no other device is still claiming
bus mastership.
1.5.0.5 Interrupt Control (IPL0, IPL1, IPL2)
These Input pins indicate the encoded priority level of the device requesting an interrupt. Level
seven is the highest priority white level zero indicates that no interrupts are requested. Level
seven cannot be masked. The least significant bit is given in IPLO and the most significant bit is
contained in IPL2. These lines must remain stable until the processor signals interrupt acknowl-
edge (FC0-FC2 are all high) to insure that the interrupt is recognized.
1.5.0.6 System Control
The system control inputs are used to either reset or halt the processor and to indicate to the
processor that bus errors have occurred. The three system control inputs are explained in the
following paragraphs.
BUS ERROR (BERR)
This input informs the processor that there is a problem with the cycle currently being executed.
Problems may be a result of:
1. nonresponding devices,
2. interrupt vector number acquisition failure,
3. illegal access request as determined by a memory management unit, or
4. other application dependent errors.
The bus error signal interacts with the halt signal to determine if the current bus cycle should be
re-executed or if exception processing should be performed.
RESET (RESET)
This bidirectional signal line acts to reset (start a system initialization sequence) to processor in
response to an external reset signal. An internally generated reset (result of a RESET instruc-
tion) causes all external devices to be reset and the internal of the processor is not affected. A
total system reset (processor and external devices) is the result of external HALT and RESET
signals applied at the same time.
HALT (HALT)
When this bldirectional line is driven by an external device, it will cause the processor to stop at
the completion of the current bus cycle. When the processor has been halted using this input, all
controI signals are inactive and all three-state lines are put in their high-impedance state.
When the processor has stopped executing Instructions, such as in a double bus fault condition,
the HALT line is driven by the processor to indicate to external devices that the processor has
stopped.
41m
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TS68C000
1.5.0.7 EF 6800 Peripheral Control
These control signals are used to allow the interfacing of synchronous EF 6800 peripheral
devices with the asynchronous TS68C000. These signals are explained in the following
paragraphs.
ENABLE (E)
This signal is the standard enable signal common to all EF 6800 type peripheral devices. The
period for this output is ten TS68C000 clock periods (six clocks low, four clocks high). Enable is
generated by an internal ring counter which may come up in any state (i.e., at power on, it Is
impossible to guarantee phase relationship of E to CLK). E is a free-running crack and runs
regardless of the state of the bus on the MPU.
VALID PERIPHERAL ADDRESS (VPA)
This input indicates that the device or region addressed is an TS68000 Family device and that
data transfer should be synchronized with the enable (E) signal. This Input also indicates that
the processor should use automatic vectoring for an interrupt during an IACK cycle.
VALID MEMORY ADDRESS (VMA)
This output is used to indicate to TS68000 peripheral devices that there is a valid address on the
address bus and the processor is synchronized to enable. This signal only responds to a valid
peripheral address (VPA) input which indicates that the peripheral is an TS68000 Family device.
1.5.0.8 Processor Status (FC0, FC1, FC2)
These function code outputs indicate the state (user or supervisor) and the cycle type currently
being executed, as shown in Table 1-3. The information indicated by the function code outputs is
valid whenever address strobe (AS) is active.
1.5.0.9 Clock (CLK)
The clock input is a TTL-compatible signal that is internally buffered for development of the inter-
nal clocks needed by the processor. The clock input should not be gated off at any time and the
clock signal must conform to minimum and maximum pulse width times. The clock is a constant
frequency square wave with no stretching or shaping techniques required.
Table 1-3. Processor Status Table
Function Code Output
Cycle TimeFC2 FC1 FC0
Low Low Low (Undefined, reserved)
Low Low High User data
Low High Low User program
Low High High (Undefined, reserved)
High Low Low (Undefined, reserved)
High Low High Supervisor data
High High Low Supervisor program
High High High Interrupt acknowledge
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2170A–HIREL–09/05
TC68C000
2. Detailed Specifications
2.1 Scope
This drawing describes the specific requirements for the microprocessor TS68C000, 8 MHz, 10
MHz and 12.5 MHz, in compliance with MIL-STD-883 class B.
2.2 Applicable Documents
2.2.1 MIL-STD-883
1. MIL-STD-883: Test Methods and Procedures For Electronics
2. MIL-PRF-38535 Appendix A: General Specifications for Microcircuits
2.3 Requirements
2.3.1 General
The microcircuits are in accordance with the applicable document and as specified herein.
2.4 Design and Construction
2.4.1 Terminal Connections
Depending on the package, the terminal connections shall be as shown in Figure 1-2, Figure 1-
3, Figure 1-4 and Figure 1-5.
2.4.2 Lead Material and Finish
Lead material and finish shall be any option of MIL-PRF-38535 Appendix A-3-5-6 "Package Ele-
ment Material and Finsh".
2.4.3 Package
The macrocircuits are packaged in hermetically sealed ceramic package which is conform to
case outlines of MIL-PRF-38535 Appendix A-3-5-1.
• PGA68 64 LEAD DIP
• 64 DILSQ. LCC 68 PINS
• 68 LCCC68 TERMINALS JCC
•68 CQFP
The precise case outlines are described on figures and into MIL-M-38510.
2.4.4 Electrical Characteristics
2.4.4.1 Absolute Maximum Ratings
Limiting conditions (ratings) defined below shall not be for inspection purposes. However some
limiting conditions (ratings) may be taken in other parts of this specification as detail conditions
for an applicable test.
Unless otherwise stated, all voltages are referenced to the reference terminal as defined in
Table 1-1, ”Terminal Designations” on page 5 of this specification.
41m
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2170A–HIREL–09/05
TS68C000
2.4.4.2 Recommended Condition of Use and Guaranteed Characteristics
• Guaranteed Characteristics (Table 2-5 and Table 2-8)
The characteristics associated to a specified measurement in the detail specification shall
only be for inspection purposes.
Such characteristic defined in this specification is guaranteed only under the conditions and
within the limits which are specified for the relevant measurement. Unless otherwise speci-
fied, this guarantee applies within all the recommended operating ranges specified below.
• Recommended conditions of use (Table 2-2)
To the correct operation of the device, the conditions of use shall be within the ranges speci-
fied below (see also above).
These conditions shall not be for inspection purposes.
Some recommended values may, however, be taken in other parts of this specification as
detail conditions for an applicable test (Table 2-9).
• Additional Electrical Characteristics (Table 2-9), see ”Additional Electrical Characteristics” on
page 30.
Figure 2-1. Clock Input Timing Diagram
Note: Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V,
unless otherwise noted. The voltage swing through this range should start outside, and pass
through, the range such that the rise of fall will be linear between 0.8V and 2.0V.
Unless otherwise stated, all voltages are referenced to the reference terminal (see Table 1-1).
Table 2-1. Absolute Maximum Ratings
Symbol Parameter Test Conditions Min Max Unit
VCC Supply voltage -0.3 +6.5 V
VIInput voltage -0.3 +6.5 V
VOOutput voltage NA NA V
VOZ Off state voltage -0.3 11.0 V
IOOutput currents NA NA mA
IiInput currents NA NA mA
PDMAX Max power dissipation TCASE = -55°C0.27W
TCASE = +125°C0.27W
TSTG Storage temperature -55 +150 °C
TJJunction temperature +150 °C
TLEADS Lead temperature Max 5 sec. Soldering +270 °C
0.8V
2.0V
tcyc
tCL tCH
tCf
tCr
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2170A–HIREL–09/05
TC68C000
Note: 1. Load networks number 1 to 4 as specified in ”Test Conditions Specific to the Device” on page 26 (Figure 2-2 and Figure 2-3)
gives the maximum loading for the relevant output.
2.4.4.3 Special Recommended Conditions for CMOS Devices
1. CMOS Latch-up
The CMOS cell is basically composed of two complementary transistors (a P-channel and an N-
channel), and, in the steady state, only one transistor is turned-on. The active P-channel transis-
tor sources current when the output is a logic high and presents a high impedance when the
output is a logic low. Thus the overall result is extremely low power consumption because there
is no power loss through the active P.channel transistor. Also since only once transistor is deter-
mined by leakage currents.
Because the basic CMOS cell is composed of two complementary transistors, a virtual semicon-
ductor controlled rectifier (SCR) may be formed when an input exceeds the supply voltage. The
SCR that is formed by this high input causes the device to become "Iatched" in a mode that may
result in excessive current drain and eventual destruction of the device. Although the device is
Implemented with input protection diodes, care should be exercised to ensure that the maximum
input voltages specification is not exceeded tram voltage transients; others may require no addi-
tional circuitry.
Table 2-2. Recommended Condition of Use
Symbol Parameter
Operating Range
Model Min Max Unit
VCC Supply voltage All 4.5 5.5 V
VIL Low level input voltage All 0 0.8 V
VIH High level input voltage (see also ”Package” on page 10)All 2.0V
CC V
TCASE Operating temperature All -55 +125 °C
RLValue of output load resistance All (1) Ω
CLOutput loading capacitance All (1) pF
tr(c) Clock rise time (see Figure 2-1)All10ns
tf(c) Clock fall time (see Figure 2-1)All10ns
fCClock frequency (see Figure 2-1)
TS68C000-8 4.0 8.0 MHz
TS68C000-10 4.0 10.0 MHz
TS68C000-12 4.0 12.5 MHz
tCYC Clock time (see Figure 2-1)
TS68C000-8 125 250 ns
TS68C000-10 100 250 ns
TS68C000-12 80 250 ns
tW(CL) Clock pulse width low (see Figure 2-1)
TS68C000-8 55 125 ns
TS68C000-10 45 125 ns
TS68C000-12 35 125 ns
tW(CH) Cycle pulse width high (see Figure 2-1)
TS68C000-8 55 125 ns
TS68C000-10 45 125 ns
TS68C000-12 35 125 ns
41m
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TS68C000
2. CMOS Applications
• The TS68C000 completely satisfies the input/output drive requirements of CMOS logic
devices.
• The HCMOS TS68C000 provides an order of magnitude power dissipation reduction when
compared to the HMOS TS68000. However, the TS68C000 does not offer a "power down" or
"halt" mode. The minimum operating frequency of the TS68C000 is 4 MHz.
2.4.5 Thermal Characteristics
2.4.5.1 Power Considerations
The average chip-junction temperature, TJ, in °C can be obtained from:
TJ = TA + (PD . θJA)(1)
TA = Ambient Temperature, °C
θJA = Package Thermal Resistance, Junction-to-Ambient, °C/W
PD = PINT + PI/O
PINT = ICC x VCC, Watts – Chip Internal Power
PI/O = Power Dissipation on Input and Output Pins – User Determined
For most applications PI/O < PINT and can be neglected.
An Approximate relationship between PD and TJ (if PI/O is neglected) is:
PD = K: (TJ + 273) (2)
Solving equations (1) and (2) for K gives:
K = PD. (TA + 273) + θJA · PD2(3)
where K is constant pertaining to the particular part K can be determined from the equation (3)
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ
can be obtained by solving equations (1) and (2) iteratively for any value of TA.
The total thermal resistance of a package (θJA) can be separated into two components, θJC and
θCA, representing the barrier to heat flow from the semiconductor junction to the package (case),
surface (θJC) and from the case to the outside ambient (θCA).
Table 2-3. Thermal Characteristics
Package Symbol Parameter Value Unit
DIL 64
θJA Thermal resistance junction to ambient 25 °C/W
θJC Thermal resistance junction to case 6 °C/W
PGA 68
θJA Thermal resistance junction to ambient 30 °C/W
θJC Thermal resistance junction to case 6 °C/W
LCCC 68 θJA Thermal resistance junction to ambient 40 °C/W
θJC Thermal resistance junction to case 8 °C/W
CQFP 68
θJA Thermal resistance junction to ambient 40 °C/W
θJC Thermal resistance junction to case 10 °C/W
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2170A–HIREL–09/05
TC68C000
These terms are related by the equation:
θJA = θJC + θCA (4)
θJA is device related and cannot be influenced by the user. However, θCA is user dependent and
can be minimized by such thermal management techniques as heat sinks, ambient air cooling
and thermal convection. Thus, good thermal management on the part of the user can signifi-
cantly reduce θCA so that θJA approximately equals θJC. Substitution of θJC for θJA in equation (1)
will result in a lower semiconductor junction temperature.
2.4.6 Mechanical and Environmental
The microcircuits shall meet all mechanical environmental requirements of MIL-STD-883 for
class B devices.
2.4.7 Marking
The document where are defined the marking are identified in the related reference documents.
Each microcircuit is legible and permanently marked with the following information as minimum:
• Atmel Logo
• Manufacturer’s Part Number
• Class B Identification
• Date-code of inspection lot
• ESD Identifier if Available
• Country of Manufacturing
2.5 Quality Conformance Inspection
2.5.1 DESC/MIL-STD-883
Is in accordance with MIL-PRF-38535 and method 5005 of MIL-STD-883. Group A and B
inspections are performed on each production lot. Group C and D inspection are performed on a
periodical basis.
2.6 Electrical Characteristics
2.6.1 General Requirements
All static and dynamic electrical characteristics specified for inspection purposes and the rele-
vant measurements conditions are given below:
•Table 2-4: Static Electrical Characteristics for all electrical variants.
•Table 2-5, Table 2-6, Table 2-7 and Table 2-8: Dynamic electrical characteristics for 8 MHz,
10 MHz and 12.5 MHz.
For static characteristics (Table 2-4), test methods refer to IEC 748-2 method number, where
existing.
For dynamic characteristics, test methods refer to clause ”Test Conditions Specific to the
Device” on page 26 of this specification (Table 2-5, Table 2-6, Table 2-7 and Table 2-8).
Indication of "min" or "max" in the column "test temperature" means minimum or maximum oper-
ating temperatures as defined in sub-clause ”Recommended Condition of Use and Guaranteed
Characteristics” on page 11 here above.
41m
15
2170A–HIREL–09/05
TS68C000
Table 2-4. Static Characteristics
VCC = 5.0V VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and -40°C/+85°C
Test
Number Symbol Parameter
Ref
Number
(**)
Test
Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
1I
CC Supply current 41
VCC = 5.5V
FC = 8 MHz
FC = 10 MHz
FC = 12 MHz
All 42
45
50
mA
2V
OL(1)
Low level output
voltage for: A1 to A23
FC0 to FC2; BG
37
VCC = 4.5V 25°C
0.5 Vmax
IOL = 3.2 mA min
3V
OL(2)
Low level output
voltage for:
HALT
37
VCC = 4.5V 25°C
0.5 Vmax
IOL = 1.6 mA min
4V
OL(3)
Low level output
voltage for:
AS; R/W:
D0 to D15 UDS;
LDS; VMA and E
37
VCC = 4.5V 25°C
0.5 V
max
IOL = 5.3 mA min
5V
OL(4)
Low level output
voltage for:
RESET
37
VCC = 4.5V 25°C
0.5 Vmax
IOL = 5.0 mA min
6V
OH
High level output
voltage for all outputs 37
VCC = 4.5V 25°C
2.4 VCC – 0.75 Vmax
IOH = -400 µA min
7I
IH(1)
High level input current
for all inputs excepted
HALT and RESET
38
VCC = 5.5V 25°C
2.5 µAmax
VI = 5.5V min
8I
IL(1)
Low level input current
for all inputs excepted
HALT and RESET
38
VCC = 5.5V 25°C
-2.5 µAmax
VI = 0V min
9I
IH(2)
High level input
current for:
HALT and RESET
38
VCC = 5.5V 25°C
20 µAmax
VI = 5.5V min
10 IIL(2)
Low level input
current for:
HALT and RESET
38
VCC = 5.5V 25°C
-20 µAmax
VI = 0V min
16
2170A–HIREL–09/05
TC68C000
Note: * Algebraic values
** Measurement method: see ”General Requirements” on page 14 and ”Test Conditions Specific to the Device” on page 26.
Referred notes are given on page 25.
11 IOHZ
High level output
3-state leakage current
VCC = 5.5V 25°C
20 µAmax
VOH = 2.4V min
12 IOLZ
Low level output
3-state leakage current
VCC = 5.5V 25°C
20 µAmax
VOL = 0.4V min
13 VIH
High level input
voltage for all inputs
VCC = 4.5V 25°C
2.0 Vmax
VCC = 5.5V min
14 VIL
Low level input
voltage for all inputs
VCC = 4.5V 25°C0.8V
max 0.8 V
VCC = 5.5V min 0.8 V
14A CIN
Input capacitance
(all inputs) 11
Reverse
voltage = 0V
f = 1.0 MHz
25°C25pF
max NA pF
min NA pF
14B COUT
Output capacitance
(all inputs) 11
Reverse
voltage = 0V
f = 1.0 MHz
25°C20pF
max NA pF
min NA pF
14C VTEST Internal protection
Transient energy rating
See note(9)
5 cycles 25°C -500 +500 V
Table 2-4. Static Characteristics (Continued)
VCC = 5.0V VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and -40°C/+85°C
Test
Number Symbol Parameter
Ref
Number
(**)
Test
Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
Table 2-5. Dynamic Characteristics – TS68C000-8
VCC = 5.0 VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and Tc = -40°C/+85°C
Test
Number Symbol Parameter
Figure
Number
(**)
Test
Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
27 tSU (DICL) Set-up time
Data-in to clock low(1) 10 – 11
See ”Input and
Output Signals
for Dynamic
Measurements”
on page 29
(a) to (c)
fC = 8 MHz
25°C
20(10) ns
max
min
41m
17
2170A–HIREL–09/05
TS68C000
47 tSU
(SDTCL)
Set-up time
DTACK low to clock
low(1)
10 – 11 Idem test 27
25°C
20(10) nsmax
min
47 tSU
(SBRCL)
Set-up time
BR low to clock low (1) 10 – 11 Idem test 27
25°C
20(10) nsmax
min
47 tSU
(SBGCL)
Set-up time
BGACK low to clock
low(1)
10 – 11 Idem test 27
25°C
20(10) nsmax
min
47 tSU
(SVPACL)
Set-up time
VPA low to clock low
(1)
10 – 11 Idem test 27
25°C
20(10) nsmax
min
47 tSU
(SBERCL)
Set-up time BERR
low to clock low(1) 10 – 11 Idem test 27
25°C
20(10) nsmax
min
2tw
(CL) Clock width low 10 – 11 Idem test 27
25°C
55(10) 125 nsmax
min
3tw
(CH) Clock width high 10 – 11 Idem test 27
25°C
55 125 nsmax
min
6A
tPLH
tPHL
(CHFCV)
Propagation time
clock high to FC valid 10 – 11
Idem
test 27
Load: 3
25°C
70 nsmax
min
9tPHL
(CHSLX)
Propagation time
clock high to AS low 10 – 11
Idem
test 27
Load: 4
25°C
60(3)
max
min
9tPHL
(CHSL)
Propagation time
CLK high to LDS,
UDS low
10 – 11
Idem
test 27
Load: 4
25°C
60(3) nsmax
min
12 tPLH
(CLSH)
Propagation time
CLK low to AS high 10 – 11
Idem
test 27
Load: 4
25°C
70(3) nsmax
min
Table 2-5. Dynamic Characteristics – TS68C000-8 (Continued)
VCC = 5.0 VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and Tc = -40°C/+85°C
Test
Number Symbol Parameter
Figure
Number
(**)
Test
Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
18
2170A–HIREL–09/05
TC68C000
12 tPLH
(CLSH)
Propagation time
CLK low to LDS, UDS
high
10 – 11
Idem
test 27
Load: 4
25°C
70(3) nsmax
min
18 tPLH
(CHRHX)
Propagation time
CLK high to R/W high 10 – 11
Idem
test 27
Load: 4
25°C
70(3) nsmax
min
20 tPHL
(CHRL)
Propagation time
CLK high to R/W low 10 – 11
Idem
test 27
Load: 4
25°C
70(3) nsmax
min
23
tPZL
tPZH
(CLDO)
Propagation time
CLK low to Data-out
valid
10 – 11
Idem
test 27
Load: 4
25°C
70(3) nsmax
min
6
tPZL
tPZH
(CLAV)
Propagation time
CLK low to Address
valid
10 – 11
Idem
test 27
Load: 3
25°C
70 nsmax
min
32 tHRRF RESET/HALT input
transition time 10 – 11 Idem
test 27
25°C
200 nsmax
min
33 tPHL
(CHGL)
Propagation time
CLK high to BG low 12
Idem
test 27
Load: 3
25°C
70 nsmax
min
34 tPLH
(CHGH)
Propagation time
CLK high to BG high 12
Idem
test 27
Load: 3
25°C
70 nsmax
min
40 tPHL
(CLVM)
Propagation time
CLK low to VMA low 13
Idem
test 27
Load: 4
25°C
70 nsmax
min
41 tPHL
(CLE)
Propagation time
CLK low to E low 13
Idem
test 27
Load: 4
25°C
70 nsmax
min
8th
(SHAZ)
Hold time CLK high
to Address 10 – 11
Idem
test 27
Load: 3
25°C
0nsmax
min
Table 2-5. Dynamic Characteristics – TS68C000-8 (Continued)
VCC = 5.0 VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and Tc = -40°C/+85°C
Test
Number Symbol Parameter
Figure
Number
(**)
Test
Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
41m
19
2170A–HIREL–09/05
TS68C000
Note: * Algebraic values
** Measurement method: see ”General Requirements” on page 14 and ”Test Conditions Specific to the Device” on page 26
Referred notes are given on page 25.
11 tSU
(AVSL)
Set-up time
Address valid to
AS, LDS, UDS low
10 – 11
Idem
test 27
Load: 4
25°C
30(4) nsmax
min
35 tPHL
(BRLGL)
Propagation time
BR low to
BG low
12
Idem
test 27
Load: 3
25°C
1.5
3.5 CLKS
(2)
ns
max
min +90
37 tPLH
(GALEH)
Propagation time
BGACK low to
BG high
12
Idem
test 27
Load: 3
25°C
1.5
3.5 CLKS
(2)
ns
max
min +90
48 tSU
(BELDAL)
Set-up time
BERR low to
DTACK low
11 Idem
test 27
25°C
20(5) –nsmax
min
48 tSU
(BELDAL)
Set-up time
BERR low to
DTACK low
10 – 11 Idem
test 27
25°C
20(5) –nsmax
min
26 th
(DOSL)
Hold time
Data-out valid to
LDS, UDS low
11
Idem
test 27
Load: 4
25°C
30(4) –nsmax
min
Table 2-5. Dynamic Characteristics – TS68C000-8 (Continued)
VCC = 5.0 VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and Tc = -40°C/+85°C
Test
Number Symbol Parameter
Figure
Number
(**)
Test
Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
Table 2-6. Dynamic Characteristics – TS68C000-10
Test
Number Symbol Parameter
Figure
Number
(**)
Test
Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
27 tSU (DICL) Set-up time
Data-in to clock low(1) 10 – 11
See ”Input and
Output Signals
for Dynamic
Measurements”
on page 29
(a) to (c)
fc = 10 MHz
25°C
20(10) ns
max
min
47 tSU
(SDTCL)
Set-up time
DTACK low to clock
low(1)
10 – 11 Idem test 27
25°C
20(10) nsmax
min
20
2170A–HIREL–09/05
TC68C000
47 tSU
(SBRCL)
Set-up time
BR low to clock low (1) 10 – 11 Idem test 27
25°C
20(10) nsmax
min
47 tSU
(SBGCL)
Set-up time
BGACK low to clock
low(1)
10 – 11 Idem test 27
25°C
20(10) nsmax
min
47 tSU
(SVPACL)
Set-up time
VPA low to clock low
(1)
10 – 11 Idem test 27
25°C
20(10) nsmax
min
47 tSU
(SBERCL)
Set-up time BERR
low to clock low(1) 10 – 11 Idem test 27
25°C
20(10) nsmax
min
2tw
(CL) Clock width low 10 – 11 Idem test 27
25°C
45 125 nsmax
min
3tw
(CH) Clock width high 10 – 11 Idem test 27
25°C
45 125 nsmax
min
6A
tPLH
tPHL
(CHFCV)
Propagation time
clock high to FC valid 10 – 11
Idem
test 27
Load: 3
25°C
60 nsmax
min
9tPHL
(CHSLX)
Propagation time
clock high to AS low 10 – 11
Idem
test 27
Load: 4
25°C
55(3) nsmax
min
9tPHL
(CHSL)
Propagation time
CLK high to LDS,
UDS low
10 – 11
Idem
test 27
Load: 4
25°C
55(3) nsmax
min
12 tPLH
(CLSH)
Propagation time
CLK low to AS high 10 – 11
Idem
test 27
Load: 4
25°C
55(3) nsmax
min
12 tPLH
(CLSH)
Propagation time
CLK low to LDS, UDS
high
10 – 11
Idem
test 27
Load: 4
25°C
55(3) nsmax
min
Table 2-6. Dynamic Characteristics – TS68C000-10 (Continued)
Test
Number Symbol Parameter
Figure
Number
(**)
Test
Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
41m
21
2170A–HIREL–09/05
TS68C000
18 tPLH
(CHRHX)
Propagation time
CLK high to R/W high 10 – 11
Idem
test 27
Load: 4
25°C
60(3) nsmax
min
20 tPHL
(CHRL)
Propagation time
CLK high to R/W low 10 – 11
Idem
test 27
Load: 4
25°C
60(3) nsmax
min
23
tPZL
tPZH
(CLDO)
Propagation time
CLK low to Data-out
valid
10 – 11
Idem
test 27
Load: 4
25°C
55(3) nsmax
min
6
tPZL
tPZH
(CLAV)
Propagation time
CLK low to Address
valid
10 – 11
Idem
test 27
Load: 4
25°C
60 nsmax
min
32 tHRRF
(CHGL)
RESET/HALT input
transition time 10 – 11 Idem
test 27
25°C
200 nsmax
min
33 tPHL
(CHGL)
Propagation time
CLK high to BG low 12
Idem
test 27
Load: 3
25°C
60 nsmax
min
34 tPLH
(CHGH)
Propagation time
CLK high to BG high 12
Idem
test 27
Load: 3
25°C
60 nsmax
min
40 tPHL
(CLVM)
Propagation time
CLK low to VMA low 13
Idem
test 27
Load: 4
25°C
70 nsmax
min
41 tPHL
(CLE)
Propagation time
CLK low to E low 13
Idem
test 27
Load: 4
25°C
55 nsmax
min
8tH
(SHAZ)
Hold time CLK high
to Address 10 – 11
Idem
test 27
Load: 3
25°C
0nsmax
min
11 tSU
(AVSL)
Set-up time
Address valid to
AS, LDS, UDS low
10 – 11
Idem
test 27
Load: 4
25°C
20(4) nsmax
min
Table 2-6. Dynamic Characteristics – TS68C000-10 (Continued)
Test
Number Symbol Parameter
Figure
Number
(**)
Test
Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
22
2170A–HIREL–09/05
TC68C000
Note: * Algebraic values
** Measurement method: see ”General Requirements” on page 14 and ”Test Conditions Specific to the Device” on page 26
Referred notes are given on page 25.
35 tPHL
(BRLGL)
Propagation time
BR low to
BG low
12
Idem
test 27
Load: 3
25°C
1.5
3.5 CLKS
(2)
ns
max
min +80
37 tPLH
(GALGH)
Propagation time
BGACK low to
BG high
12
Idem
test 27
Load: 3
25°C
1.5
3.5 CLKS
(2)
ns
max
min +80
48 tSU
(BELDAL)
Set-up time
BERR low to
DTACK low
11 Idem
test 27
25°C
20(5) nsmax
min
48 tSU
(BELDAL)
Set-up time
BERR low to
DTACK low
10 – 11 Idem
test 27
25°C
20(5) nsmax
min
26 tH
(DOSL)
Hold time
Data-out valid to
LDS, UDS low
11
Idem
test 27
Load: 4
25°C
20(4) nsmax
min
Table 2-6. Dynamic Characteristics – TS68C000-10 (Continued)
Test
Number Symbol Parameter
Figure
Number
(**)
Test
Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
Table 2-7. Dynamic Characteristics – TS68C000-12
Test
Number Symbol Parameter
Figure
Number
(**) Test Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
27 tSU (DICL)
Set-up time
Data-in to clock
low(1)
10 – 11
See ”Input and
Output Signals for
Dynamic
Measurements” on
page 29
(a) to (c)
fC = 12 MHz
25°C
10(10) ns
max
min
47 tSU
(SDTCL)
Set-up time
DTACK low to
clock low(1)
10 – 11 Idem test 27
25°C
20(10) nsmax
min
47 tSU
(SBRCL)
Set-up time
BR low to clock
low(1)
10 – 11 Idem test 27
25°C
20(10) nsmax
min
23
2170A–HIREL–09/05
TS68C000
47 tSU
(SBGCL)
Set-up time
BGACK low to
clock low(1)
10 – 11 Idem test 27
25°C
20(10) nsmax
min
47 tSU
(SVPACL)
Set-up time
VPA low to clock
low(1)
10 – 11 Idem test 27
25°C
20(10) nsmax
min
47 tSU
(SBERCL)
Set-up time BERR
low to clock low(1) 10 – 11 Idem test 27
25°C
20(10) nsmax
min
2tw
(CL) Clock width low 10 – 11 Idem test 27
25°C
35 125 nsmax
min
3tw
(CH) Clock width high 10 – 11 Idem test 27
25°C
35 125 nsmax
min
6A
tPLH
tPHL
(CHFCV)
Propagation time
clock high to FC
valid
10 – 11
Idem
test 27
Load: 3
25°C
55 nsmax
min
9tPHL
(CHSLX)
Propagation time
clock high to AS
low
10 – 11
Idem
test 27
Load: 4
25°C
55(3) nsmax
min
9tPHL
(CHSL)
Propagation time
CLK high to LDS,
UDS low
10 – 11
Idem
test 27
Load: 4
25°C
55(3) nsmax
min
12 tPLH
(CLSH)
Propagation time
CLK low to LDS,
UDS high
10 – 11
Idem
test 27
Load: 4
25°C
50(3) nsmax
min
12 tPLH
(CLSH)
Propagation time
CLK low to LDS,
UDS high
10 – 11
Idem
test 27
Load: 4
25°C
50(3) nsmax
min
18 tPLH
(CHRHX)
Propagation time
CLK high to R/W
high
10 – 11
Idem
test 27
Load: 4
25°C
60(3) nsmax
min
Table 2-7. Dynamic Characteristics – TS68C000-12 (Continued)
Test
Number Symbol Parameter
Figure
Number
(**) Test Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
24
2170A–HIREL–09/05
TC68C000
20 tPHL
(CHRL)
Propagation time
CLK high to R/W
low
11
Idem
test 27
Load: 4
25°C
60(3) nsmax
min
23
tPZL
tPZH
(CLDO)
Propagation time
CLK low to Data-
out valid
11
Idem
test 27
Load: 4
25°C
55(3) nsmax
min
6
tPZL
tPZH
(CLAV)
Propagation time
CLK low to
Address valid
10 – 11
Idem
test 27
Load: 4
25°C
55 nsmax
min
32 tHRRF RESET/HALT
transition time 10 – 11 Idem
test 27
25°C
150 nsmax
min
33 tPHL
(CHGL)
Propagation time
CLK high to BG
low
8 – 9
Idem
test 27
Load: 3
25°C
50 nsmax
min
34 tPLH
(CHGH)
Propagation time
CLK high to BG
high
12
Idem
test 27
Load: 3
25°C
50 nsmax
min
40 tPHL
(CLVM)
Propagation time
CLK low to VMA
low
13
Idem
test 27
Load: 4
25°C
70 nsmax
min
41 tPHL
(CLE)
Propagation time
CLK low to E low 13
Idem
test 27
Load: 4
25°C
45 nsmax
min
8tH
(SHAZ)
Hold time CLK
high to Address 10 – 11
Idem
test 27
Load: 3
25°C
0nsmax
min
11 tSU
(AVSL)
Set-up time
Address valid to
AS, LDS, UDS low
10 – 11
Idem
test 27
Load: 4
25°C
15(4) nsmax
min
35 tPHL
(BRLGL)
Propagation time
BR low to
BG low
12
Idem
test 27
Load: 3
25°C
1.5
3.5 CLKS
(2)
ns
max
min +70
Table 2-7. Dynamic Characteristics – TS68C000-12 (Continued)
Test
Number Symbol Parameter
Figure
Number
(**) Test Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
41m
25
2170A–HIREL–09/05
TS68C000
Note: * Algebraic values
** Measurement method: see ”General Requirements” on page 14 and ”Test Conditions Specific to the Device” on page 26
2.6.1.1 Referred notes to Table 2-4, Table 2-5, Table 2-6, Table 2-7
The following notes shall apply where referred into Table 2-4, Table 2-5, Table 2-6 and Table 2-
7.
Notes: 1. If the asynchronous setup tlme (47) requirements are satisfied, the DTACK low-to-data setup time (31) requirement Gan be
ignored. The data must only satisfy the data-in to clock-low setup time (27) for the following cycle.
2. Where "CLKS" is stated as unit time limit, the relevant time in nanoseconds shall be calculated as the actual cycle time of
clock signal input multiply by the given number of CLKS limits.
3. For a loading capacitance of less than or equal to 50 picofarads, substrate 5 nanoseconds from the value given in the maxi-
mum columns.
4. Actual value depends on period.
5. If 47 is satisfied for bath DTACK and BERR, 48 may be 0 nanoseconds.
6. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting
BGACK.
7. The falling edge of 56 triggers bath the negation of the strobes (AS, and X DS) and the falling edge of E. either of these
events can occur first depending upon the loading on each signal. Specification 49 indicates the absolute maximum skew
that will occur between the rising edge of the strobes and the falling edge of the E clock.
8. When AS and R/W are equally loaded (±20%), substrate 10 nanoseconds from the values in these columns.
9. Each terminal of the device under test shall be tested separately against all existing VCC and VSS terminals of the device
which shall be shorted together for the test. The other untested terminals shall be unconnected during the test. One cycle
consists of the application of the bath limits as given in Table 2-5, Table 2-6 and Table 2-7.
10. This value should be treated as a min for design purpose. For the conformance testing the value shall be regarded as the
maximum time.
37 tPLH
(GALGH)
Propagation time
BGACK low to
BG high
12
Idem
test 27
Load: 3
25°C
1.5
3.5 CLKS
(2)
ns
max
min +70
48 tSU
(BELDAL)
Set-up time
BERR low to
DTACK low
11 Idem
test 27
25°C
20(5) nsmax
min
48 tSU
(BELDAL)
Set-up time
BERR low to
DTACK low
10 – 11 Idem
test 27
25°C
20(5) nsmax
min
26 tH
(DOSL)
Hold time
Data-out valid to
LDS, UDS low
11
Idem
test 27
Load: 4
25°C
15(4) nsmax
min
Table 2-7. Dynamic Characteristics – TS68C000-12 (Continued)
Test
Number Symbol Parameter
Figure
Number
(**) Test Conditions
Test
Temperature
Limits
Unit
Min
(*)
Max
(*)
0—4”
26
2170A–HIREL–09/05
TC68C000
2.6.2 Test Conditions Specific to the Device
2.6.2.1 Loading Network
The applicable loading network shall be as defined in column "Test Conditions" of Table 2-5,
Table 2-6 and Table 2-7, referring to the loading network number as shown in Figure 2-2 and
Figure 2-3 below.
Figure 2-2. Passive Loads
Figure 2-3. Active Loads
Table 2-8. AC Electrical Specification – Clock Timing
Symbol Parameter
8 MHz 10 MHz 12.5 MHz
UnitMin Max Min Max Min Max
f Frequency of operation 4.0 8.0 4.0 10.0 4.0 12.5 MHz
tcyc Cycle time 125 250 100 250 80 250 ns
tCL
tCH
Clock pulse width 55
55
125
125
45
45
125
125
35
35
125
125 ns
tCr
tCf
Rise and fall times 10
10
10
10
10
10 ns
C1
Rn
+ VCC
OUTPUT
OUTPUT
C1
Rn
1N 914
+ VCC
R1
27
2170A–HIREL–09/05
TS68C000
Note: 1. C1 includes all parasitic capacitances of test machines
2.6.2.2 Time Definitions
The times specified in Table 2-5, Table 2-6 and Table 2-7 as dynamic characteristics are defined
in Figure 2-4 to Figure 2-7 below by a reference number given in the column "Method" of the
tables together with the relevant figure number.
Figure 2-4. Read Cycle Timing
Load NBR Figure R1 Rn C1(1) Output Application
15.1–910Ω130 pF RESET
2 5.1 – 2.9 kΩ70 pF HALT
3 5.2 6.0 k 1.22 kΩ130 pF A1 to A23, BG and FC0 to FC2
4 5.2 6.0 k 740Ω130 pF All other outputs
DATA IN
31
27
47
32
47
56 30
11
9
15
17
19
12
12
6
2
1
3
7
14
47
11A
6A
4
5
810
13
15
18
32
48
29
28
S0 S1 S2 S3 S4 S5 S6 S7
A1-A23
CLK
AS
R/W
FC0-FC2
ASYNCHRONOUS
INPUTS
HALT/RESET
BERR/BR
DTACK
LDS/UDS
_’ ‘ \R l O :RQ >—:a\ e4) 0% e a f4) a <—o %="" o="" x="" w="" e="" 2="" j="" c}="" o="" k="" a_="" _="" v="" :="" a="" 50="" o=""><—. g‘—*="" o=""><—> O 07% fl <—o a="" (—0="" (="" q="" ,="" oi‘—*="">
28
2170A–HIREL–09/05
TC68C000
Figure 2-5. Write Cycle Timing
A1-A23
CLK
AS
R/W
DATA OUT
32
FC0-FC2
ASYNCHRONOUS
INPUTS
HALT/RESET
BERR/BR
DTACK
LDS/UDS
56
32
47
47
47
48
30
28
6A
7
21A
55
10
26
23
22
20
14A
915
13
21
6
10
9
7
8
14 16
53
25
S0 S1 S2 S3 S5 S6 S7 S0
S4
Arman
29
2170A–HIREL–09/05
TS68C000
Figure 2-6. AC Electrical Waveforms – Bus Arbitration
Figure 2-7. Enable/Interface Timing
2.6.2.3 Input and Output Signals for Dynamic Measurements
1. Input pulse characteristics
Where input pulse generator is loaded by only a 50Ω resistor, the input pulse characteristics
shall be as shown in Figure 2-8.
STROBES
AND R/W
BR
BG
BGACK
CLK
16
35
33 38
34
36
39
46
37
A1-A23
CLK
AS
23
E
VPA
VMA
R/W
(READ)
DATA IN
UDS/LDS
READ
R/W
WRITE
DATA OUT
UDS/LDS
WRITE
41
43
40 24
27
44
49
42
45
54
42
50
41
51
52
S0 S1 S2 S3 S4 wwwwww ww wwwww wwwwwww wwwwwwww
S5 S6 S7 S0
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2170A–HIREL–09/05
TC68C000
Figure 2-8. Input Pulse Characteristics
2. Time measurement input voltage references
Input voltages which are taken as reference for time measurement shall be:
VIL = 0.8V
VIH = 2.0V
3. Time measurement input voltage references
Where output is (or becomes to) valid state, the output voltages which are taken as reference for
time measurements, shall be as shown in Figure 2-9.
Figure 2-9. Output Voltage References
2.6.3 Additional Information
Additional information shall not be for any inspection purposes.
2.6.3.1 Power Considerations
See ”Thermal Characteristics” on page 13.
2.6.3.2 Additional Electrical Characteristics
The following additional characteristics, which are obtained from circuit design, are given for
Information only.
Unless otherwise stated, for dynamic additional characteristics, the given reference numbers
refer to Figure 2-1 to Figure 2-7 and loading number refer to Figure 2-2 and Figure 2-3 (see
”Test Conditions Specific to the Device” on page 26 of this specification).
The given limits should be valid for all operating temperature ranges as defined in ”Recom-
mended Condition of Use and Guaranteed Characteristics” on page 11 of this specification.
2.4V
2.0V
0.8V
0.45V
tra = 0.5 ns tra = 0.5 ns
Voltage Reference
Voltage Reference
Low
High
tPLH tPHL tPZH tPZL
VOH = 2.4V
VOL = 0.5V
41m
31
2170A–HIREL–09/05
TS68C000
Table 2-9. Additional Electrical Characteristics
Item
NO. Symbol Parameter
Ref
Number
Load
Number
TS68C000-8 TS68C000-10 TS68C000-12
Unit
Limits Limits Limits
Min Max Min Max Min Max
6A VOH
High level output
voltage for E
with pull up
R = 1.1K to VCC
Min VCC-
0.75 Min VCC-
0.75 Min VCC-0.75 V
37
tPLZ
tPHZ
(CLAZX)
Propagation
time CLK low to
Address
3-state
Fig. 10
Ref. 7 3807060ns
39 tPHZ
(CHSZX)
Propagation
time CLK high to
AS, LDS, UDS
3-state
Fig. 11
Ref. 16 4807060ns
40
tPLZ
tPHZ
(CHRZ)
Propagation
time CLK high to
R/W 3-state
Fig. 12
Ref. 16 4807060ns
41
tPHZ
tPLZ
(CHAZX)
Propagation
time CLK high to
Data 3-state
Fig. 11
Ref. 7 4807060ns
43 tH
(SHAZ)
Hold time AS,
LDS, UDS high
to Address
Fig. 10
Ref. 13 330 20 10 ns
44 tw
(SL) AS/DS width low Fig. 10
Ref. 14
240
(4) 195
(4) 160
(4) ns
45 tw
(SL)
AS, LDS, UDS
width high
Fig. 10
Ref. 15
150
(4)
105
(4)
65
(4) ns
46 tSU
(SHRH)
Set-up time
LDS, UDS high
to R/W high
Fig. 10
Ref. 17 440
(4)
20
(4)
10
(4) ns
47 tSU
(AVRL)
Set-up time
Address valid to
R/W low
Fig. 10
Ref. 21 420
(4)
0
(4)
0
(4) ns
48 tPHL
(RLSL)
Propagation
time R/W low to
lds, uds low
Fig. 11
Ref. 22 480
(4) 50
(4) 30
(4) ns
49 tH
(SHDO)
Hold time LDS,
UDS high to
Data-out
Fig. 11
Ref. 25 430
(4) 20
(4) 15
(4) ns
50 tH (SHDI)
Hold time AS,
LDS, UDS high
to Data-in
Fig. 10
Ref. 29 00 0 ns
52 tH
(BRHGH)
Propagation
time BR high to
BG high(6)
Fig. 12
Ref. 36 3 1.5 3.5 + 90 1.5 3.5 + 80 1.5 3.5 + 70
CLKS
(2)
ns
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2170A–HIREL–09/05
TC68C000
54
tPHZ
tPLZ
(GLZ)
Propagation
time BG low
to Data and
Address
3-state
Fig. 12
Ref. 36
BG,
address
3
Data 4
80 70 60 ns
55 tw (GH) BG width high Fig. 12
Ref. 39 1.5 1.5 1.5 CLKS
ns
56 tPLH
(VMLEH)
Propagation
time VMA low to
E high
Fig. 13
Ref. 43 4 200 150 90 ns
57 tH
(SHVPH)
Hold time AS,
LDS, UDS high
to VPA high
Fig. 20 Ref. 44
(see ”Although
UDS and LDS
are asserted,
no data is read
from the bus
during the
autovector
cycle. The
vector number
is generated
internally).” on
page 45)
4 0 120 0 90 0 70 ns
58 tH (ELAI) Hold time E low
to address
Fig. 13
Ref. 45 330 10 10 ns
59 tw (BGL) BGACK width
low
Fig. 12
Ref. 46 1.5 1.5 1.5 CLKS
(2)
61 tw (EH) E width high Fig. 13
Ref. 50 450 350 280 ns
62 tw (EL) E width low Fig. 13
Ref. 51 700 550 440 ns
63 tPHL
(FCVSL)
Propagation
time FC valid to
AS, DS low
Fig. 10
Ref. 1A
or 11A
460
(4) 50
(4) 40
(4) ns
64 tPHL
(SHDAH)
Propagation
time AS, DS
high to DTACK
high
Fig. 10
Ref. 28 40245
(4) 0 190(4) 0150
(4) ns
65 tPLH
(SHBEH)
Propagation
time AS, DS
high to BERR
high
Fig. 12
Ref. 30 40 0 0 ns
66 tSU
(DALDI)
Set-up time
DTACK low
to Data-in(1)
Fig. 10
Ref. 31 90(4) 65(4) 50(4) ns
Table 2-9. Additional Electrical Characteristics (Continued)
Item
NO. Symbol Parameter
Ref
Number
Load
Number
TS68C000-8 TS68C000-10 TS68C000-12
Unit
Limits Limits Limits
Min Max Min Max Min Max
33
2170A–HIREL–09/05
TS68C000
Notes: 1. If the asynchronous setup tlme (47) requirements are satisfied, the DTACK low-to-data setup time (31) requirement Gan be
ignored. The data must only satisfy the data-in to clock-low setup time (27) for the following cycle.
2. Where "CLKS" is stated as unit time limit, the relevant time in nanoseconds shall be calculated as the actual cycle time of
clock signal input multiply by the given number of CLKS limits.
3. For a loading capacitance of less than or equal to 50 picofarads, substrate 5 nanoseconds from the value given in the maxi-
mum columns.
4. Actual value depends on period.
5. If 47 is satisfied for bath DTACK and BERR, 48 may be 0 nanoseconds.
6. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting
BGACK.
7. The falling edge of 56 triggers bath the negation of the strobes (AS, and X DS) and the falling edge of E. either of these
events can occur first depending upon the loading on each signal. Specification 49 indicates the absolute maximum skew
that will occur between the rising edge of the strobes and the falling edge of the E clock.
8. When AS and R/W are equally loaded (±20%), substrate 10 nanoseconds from the values in these columns.
9. Each terminal of the device under test shall be tested separately against all existing VCC and VSS terminals of the device
which shall be shorted together for the test. The other untested terminals shall be unconnected during the test. One cycle
consists of the application of the bath limits as given in Table 2-5, Table 2-6 and Table 2-7.
10. This value should be treated as a min for design purpose. For the conformance testing the value shall be regarded as the
maximum time.
67 tTHL tTLH
(RH)
Transition time
HALT, RESET
input
Fig. 10
Ref. 32 200 200 200 ns
69 tw
(HRPW)
HALT and
RESET pulse
width after
power up
Fig. 10
Ref. 56 10 10 10 CLKS
(2)
70 tPHL
(ASRV)
Propagation
time AS low
to R/W valid
Fig. 11
Ref. 20A 420
(8) 20(8) 20(8) ns
71 tPHL
(FCVRL)
Propagation
time FC valid to
R/W low
Fig. 11
Ref. 21A 460
(4) 50
(4) 30
(4) ns
73 tH
(CHDOI)
Hold time CLK
high to
Data-out
Fig. 11
Ref. 53 40 0 0 ns
74 tPLH tPHL
(RLDBO)
Propagation
time R/W low to
Data-bus
impedance
change
Fig. 11
Ref. 55 430 20 10 ns
75 tPHL
(SHEL)
Propagation
time AS, DS low
to E low
Fig. 13
Ref. 49 4(7) -70 +70 -55 +55 -45 +45 ns
76 tH
(ELDOI)
Hold time E low
to
Data-out
Fig. 13
Ref. 54 430 20 15 ns
Table 2-9. Additional Electrical Characteristics (Continued)
Item
NO. Symbol Parameter
Ref
Number
Load
Number
TS68C000-8 TS68C000-10 TS68C000-12
Unit
Limits Limits Limits
Min Max Min Max Min Max
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2170A–HIREL–09/05
TC68C000
2.7 Functional Description
2.7.1 Description of Registers
Figure 2-10. User Programming Model
As shown in the user programming model (Figure 2-10), the TS68C000 offers 16/32 bits regis-
ters and a 32 bits program counter. The first eight registers (D0 – D7) are used as data registers
for byte (8-bit), and long word (32-bit) operations. The second set of seven registers (A0-A6) and
the user stack pointer (USP) may be used as software stack pointers and base address regis-
ters. In addition, the registers may be used for word and long word operations. All of the 16
registers may be used as index registers.
In supervisor mode, the upper byte of the status register and the supervisor stack pointer (SSP)
are also available to the programmer. These registers are shown in Figure 2-11.
D0
D1
D2
D3
D4
D5
D6
D7
Eight Data Registers
31 16 15
16 15
87 0
A0
A1
A2
A3
A4
A5
A6
Seven Address Registers
31 0
16 15
A7 (USP) User Stack Pointer
CCR
PC
31
31
0
0
07
Status Register
Program Counter
41m
35
2170A–HIREL–09/05
TS68C000
Figure 2-11. Supervisor Programming Model Supplement
The status register (Figure 2-12) contains the interrupt mask (eight levels available) as well as
the conditions codes: extend (X), negative (N), zero (Z), overflow (V), and carry (C). Additional
status bits indicate that the processor is in a trace (T) mode and in a supervisor (S) or user state.
Figure 2-12. Status Register
2.7.2 Data Types and Addressing Modes
Five basic data types are supported. These data types are:
•Bits
• BCD Digits (4 bits)
• Bytes (8 bits)
• Words (16 bits)
• Long Words (32 bits)
In addition, operations on other data types such as memory addresses, status ward data, etc.
are provided in the instruction set.
The 14 addressing modes, shown in Table 2-10, include six basic types:
• Register Direct
• Register Indirect
• Absolute
• program Counter Relative
•Immediate
• Implied
16 15
A7 (SSP)
SR
31 0
0
Supervisor
Stack Pointer
Status Register
15
(CCR)
87
TSIII XNZVC
210
15 13 10 8 4 0
Trace Mode
Supervisor
State
Interrupt
Mask
Extend
Negative
Zero
Overflow
Carry
System Byte
User Byte
(Condition Code Regiter)
36
2170A–HIREL–09/05
TC68C000
Included in the register indirect addressing modes is the capability to do post incrementing, pre-
decrementing, offsetting, and indexing. The program counter relative mode can also be modified
via Indexing and offsetting.
2.7.3 Data Transfer Operations
Transfer of data between devices involves the following leads:
1. address bus A1 through A23,
2. data bus 00 through D15, and
3. control signals.
The address and data buses are separate parallel buses used to transfer data using an asyn-
chronous bus structure. In all cycles, the bus master assumes responsibility for deskewing all
signals it issues at bath the stan and end of a cycle. In addition, the bus master Is responsible for
deskewing the acknowledge and data signals tram the slave device.
The following paragraphs explain the read, write, and read-modify.write cycles. The indivisible
read-modify-write cycle is the method used by the TS68C000 for interlocked multiprocessor
communications.
2.7.3.1 Read Cycle
During a read cycle, the processor receives data tram the memory of a peripheral devlce. The
processor reads bytes of data in all cases. If the instruction specifies a ward (or double ward)
operation, the processor reads both upper and lower bytes simultaneously. by asserting both
upper and lower data strobes. When the instruction specifies byte operation, the processor uses
an internal AO bit to determine which byte to read and then Issues the data strobe required for
that byte. For byte operations, when the AO bit equals zero, the upper data strobes is issued.
When the AO bit equals one, the lower data strobe is issued. When the data is received, the pro-
cessor correctly positions is internally.
2.7.3.2 Write Cycle
During a write cycle, the processor sends data to either the memory of a peripheral device. The
processor writes bytes of data in all cases. If the instruction specifies a ward operation, the pro-
cessor writes bath bytes. When the instruction specifies a byte operation, the processor uses an
internal AO bit to determine which byte to write and then issues the data strobe required for that
byte. For byte operations, when the AO bit equals zero, the upper data strobe is issued. When
the AO bit equals one, the lower data strobe is issued.
Table 2-10. Addressing Modes
Addressing Modes Syntax
Register direct addressing
Data register direct
Address register direct
Dn
An
Absolute data addressing
Absolute short
Absolute long
xxx.W
xxx.L
Program counter relative addressing
Relative with offset
Relative with index offset
d16 (PC)
d8 (PC, Xn)
41m
37
2170A–HIREL–09/05
TS68C000
Notes:
Dn = Data Register
An = Address Register
Xn = Address of Data Register used as Index Register
SR = Status Register
PC = Program Counter
SP = Stack Pointer
USP = User Stack Pointer
( ) = Effective Address
d8 = 8-bit Offset (Displacement)
d16 = 16-bit Offset (Displacement)
= xxx = Immediate Data
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
(An)
(An) +
- (An)
d16 (An)
d8 (An, Xn)
Immediate Data Addressing
Immediate
Quick Immediate
= XXX
= 1- = 8
Implied Addressing
Implied Register SR/USP/SP/PC
Table 2-10. Addressing Modes (Continued)
Addressing Modes Syntax
38
2170A–HIREL–09/05
TC68C000
Table 2-11. Instruction Set Summary
Mnemonic Description
ABCD
ADD
AND
ASL
ASR
Add Decimal with Extend
Add
Logical AND
Arithmetic Shift Left
Arithmetic Shift Right
Bcc
BCHG
BCLR
BRA
BSET
BSR
BTST
Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test
CHK
CLR
CMP
Check Register Against Bounds
Clear Operand
Compare
DBcc
DIVS
DIVU
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
EOR
EXG
EXT
Exclusive OR
Exchange Registers
Sign Extend
JMP
JSR
Jump
Jump to Subroutine
LEA
LINK
LSL
LSR
Lead Effective Address
Link Stack
Logical Shift Left
Logical Shift Right
MOVE
MULS
MULU
Move
Signed Multiply
Unsigned Multiply
NBCD
NEG
NOP
NOT
Negate Decimal with Extend
Negate
No Operation
One’s Complement
OR Logical OR
PEA Push Effective Address
41m
39
2170A–HIREL–09/05
TS68C000
2.7.3.3 Read Modify Write Cycle
The read-modify-write cycle performs a read, modifies the data in the arithmetic-logic unit, and
writes the data back to the same address. In the TS68C000, this cycle is indivisible in that the
address strobe is asserted throughout the entire cycle. The test and set (TAS) instruction uses
this cycle to provide meaningful communication between processors in a multiple processor
environment. This Instruction is the only instruction that uses the read-modify-write cycles and
since the test and set instruction only operates on bytes, all read-modify-write are byte
operations.
2.7.4 Instruction Set Overview
The TS68C000 instruction set is shown in Table 2-11. Some additional instructions are varia-
tions, or sub-sets, of these and they appear in Table 2-12. Special emphasis has been given to
the instruction set's support of structured high-level languages to facilitate ease of programming.
Each instruction, with few exceptions, operates on bytes, words, and long words and most
instructions can use any of the 14 addressing modes. Combining instruction types, data types,
and addressing modes, over 1000 useful instructions are provided. These instructions include
signed and unsigned, multiply and divide, "quick" arithmetic operations, BCD arithmetic, and
expanded operations (through traps).
RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS
Rest External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return form Subroutine
SBCD
Scc
STOP
SUB
SWAP
Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves
TAS
TRAP
TRAPV
TST
Test and Set Operand
Trap
Trap on Overflow
Test
UNLK Unlink
Table 2-11. Instruction Set Summary (Continued)
Mnemonic Description
40
2170A–HIREL–09/05
TC68C000
Table 2-12. Variations of Instruction Types
Instruction Type Variation Description
ADD
ADD
ADDA
ADDQ
ADDI
ADDX
Add
Add Address
Add Quick
Add Immediate
Add with Extend
AND
AND
ANDI
ANDI to CCR
ANDI to SR
Logical AND
And Immediate
And Immediate to Condition codes
And Immediate to Status Register
CMP
CMP
CMPA
CMPM
CMPI
Compare
Compare Address
Compare Memory
Compare Immediate
EOR
EOR
EORI
EORI to CCR
EORI to SR
Exclusive OR
Exclusive OR Immediate
Exclusive OR Immediate to condition Codes
Exclusive OR Immediate to Status Register
MOVE
MOVE
MOVEA
MOVEM
MOVEP
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP
Move
Move Address
Move Multiple Registers
Move Peripheral Data
Move Quick
Move from Status Register
Move to Status Register
Move to Condition Codes
Move User Stack Pointer
NEG NEG
NEGX
Negate
Negate with Extend
OR
OR
ORI
ORI to CCR
ORI to SR
Logical OR
OR Immediate
OR Immediate to Condition Codes
OR Immediate to Status Register
SUB
SUB
SUBA
SUBI
SUBQ
SUBX
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract Extend
41m
41
2170A–HIREL–09/05
TS68C000
2.7.5 Processing States
The TS68C000 is always in one of three processing states: normal, exception, or halted.
2.7.5.1 Normal Processing
The normal processing state is that associated with instruction execution; the memory refer-
ences are to fetch instructions and operands, and to store results. A special case of normal state
is the stopped state which the processor enters when a stop instruction is executed. In this state,
no further references are made.
2.7.5.2 Exception Processing
The exception processing state is associated with interrupts, trap instructions, tracing, and other
exception conditions. The exception may be internally generated by an instruction or by an
unusual condition arising during the execution of an instruction. Externally, exception processing
can be forced by an interrupt, by a bus error, or by a reset. Exception processing is designed to
provide an efficient context switch so that the processor may handle unusual conditions.
2.7.5.3 Halted Processing
The halted processing state is an Indication of catastrophic hardware failure. For example, if dur-
ing the exception processing of a bus error another bus errors occurs, the processor assumes
that the system is unusable and halts. Only an external reset can restart a halted processor.
Note that a processor in the stopped state is not in the halted state, nor vice versa.
Asserting the reset and halt line for ten cycles will cause a processor reset, except when VCC is
initially applied to the processor. In this case, an external reset must be applied for least 100
milliseconds.
2.7.6 Interface with EF 6800 Peripherals
Extensive line of EF6800 peripherals are directly compatible with the TS68C000.
Note: It is the own user's responsibility to verify the actual EF 6800 peripheral performances to
be compatible to the actual used TS68C000 microprocessor performances.
Soma of the EF 6800 peripheral that are particularly useful are:
EF6821: Peripheral lnterface Adapter
EF6840: Programmable Timer Module
EF6850: Asynchronous Communications Interface Adapter
EF6852: Synchronous Serial Data Adapter
EF6854: Advanced Data Link Controller
To interface the synchronous EF 6800 peripherals with the asynchronous TS68C000, the pro-
cessor modifies its bus cycle to meet the EF 6800 cycle requirements whenever an EF 6800
device address is detected. This is possible since both processors use memory mapped 1/0.
Figure 2-13 is a flowchart of the interface operation between the processor and EF 6800
devices.
42
2170A–HIREL–09/05
TC68C000
Figure 2-13. EF6800 Interfacing Flowchart
2.7.6.1 Data Transfer Operation
Three signals on processor provide the EF 6800 interface. They are: enable (E), valid memory
address (VMA), and valid peripheral address (VPA). Enable corresponds to the E or phase 2 sig-
nal i n existing EF 6800 systems. The bus frequency is one tenth of the incoming TS68C000
clock frequency. The timing of E allows 1 MHz peripherals to be used 8 MHz TS68C000. Enable
has a 60/40 duty cycle, that is, it is low for six input clocks and high for four input clocks. This
duty cycle allows the processor to do successive VPA accesses on successive E pulses.
EF6800 cycle timing is given in Figure 2-17 and Figure 2-18. At state zero (50) in the cycle, the
address bus is in the high-impedance state. A function code is asserted on the function code
output fines. One-half clock later, in state 1, the address bus is released from the high-imped-
ance state.
During state 2, the address strobe (AS) is asserted to indicate that there Is a valid address on
the address bus. If the bus cycle is a read cycle, the upper and/or lower data strobes are also
asserted in state 2. If the bus cycle is a write cycle, the read/write (R/W) signal is switched to low
(write) during state 2. One-half clock later, in state 3, the write data Is placed on the data bus,
and in state 4 the data strobes are issued to indicate valid data on the data bus. The processor
now inserts wait states until it recognizes the assertion of VPA.
The VPA input signals the processor that the address on the bus is the address of an EF 6800
device (or an area reserved for EF6800 devices) and that the bus should conform to the phase 2
transfer characteristics of the EF 6800 bus. Valid peripheral address is derived by decoding the
address bus, conditioned by the address strobe. Chip select for the EF 6800 peripherals should
be derived by decoding the address bus conditioned by VMA.
PROCESSOR SLAVE
Initiate the cycle
1) The Processor Starts a Normal Read or Write Cycle
Synchronize with Enable
1) The Processor Monitors Enable (E) until it is low
(Phase 1)
2) The Processor Asserts Valid Memory Address (VMA)
Terminate the Cycle
1) The Processor waits until E goes low (on a read
cycle the data is latched as E goes low (internally)
2) The Processor negates VMA
3) The Processor negates AS, UDS and LDS
Start Next Cycle
Define EF 6800 Cycle
1) External Hardware Asserts Valid Peripheral
Address (VPA)
Transfer the Data
1) The Peripheral waits until E is active and then
transfers the Data
43
2170A–HIREL–09/05
TS68C000
After recognition of VPA, the processor assures that the enable (E) is low, by waiting if neces-
sary, and subsequently asserts VMA. Valid memory address is then used as part of the chip
select equation of the peripheral. This ensures that the EF6800 peripherals are selected and
deselected at the correct time. The peripheral now runs its cycle during the high portion of the
signal. Figure 2-17 and Figure 2-18 depict the best and worst case EF6800 cycle timing. This
cycle length is dependent strictly upon when VPA Is asserted in relationship to the E clock.
If it is assumed that external circuitry asserts VPA as soon as possible after the assertion of AS,
then VPA will be recognized as being asserted on the falling edge of 54. In this case, no "extra"
wait cycles will be inserted prior to the recognition of VPA asserted and only the wait cycles
inserted to synchronize with the E clock will determine the total length of the cycle. In any case,
the synchronization delay will be some integral number of clock cycles within the following two
extremes:
1. Best Case – VPA is recognized as being asserted on the falling edge three crack cycles
before E rizes (or three clock cycles after E falls).
2. Worst Case – VPA is recognized as being asserted on the falling edge two clock cycles
before E rises (or four clock cycles after E falls).
During a read cycle, the processor latches the peripheral data in state 6. For all cycles, the pro-
cessor negates the address and data strobes one-half clack cycle rater in state 7 and the enable
signal goes low at this time. Another half clock later, the address bus is put in the high-imped-
ance state. During a write cycle the data bus is put in the high-impedance state and the
read/write signal is switched high. The peripheral logic must remove VPA within one clock after
the address strobe is negated.
DTACK should not be asserted while VPA Is asserted. Notice that the TS68C000 VMA is active
low, constrasted with the active high EF 6800 VMA. This allows the processor to put its buses in
the high-impedance state on DMA requests without inadvertently selecting the peripherals.
Figure 2-14. TS68C000 to EF6800 Peripheral Timing – Best Case
S0 S2 S4 w wwwwS6S0S2
CLK
A1-A23
AS
DTACK
Data Out
Data In
FC0-FC2
E
VPA
VMA
44
2170A–HIREL–09/05
TC68C000
Figure 2-15. TS68C000 to EF6800 Peripheral Timing – Worst Case
2.7.6.2 Interrupt Interface Operation
During an interrupt acknowledge cycle while the processor is fetching the vector, the VPA is
asserted, the TS68C000 will assert VMA and complete a normal EF 6800 read cycle as shown
in Figure 2-16. The processor will then use an internally generated vector that is a function of the
interrupt being serviced. This process is know as autovectorlng. The seven autovectors are vec-
tor number 25 through 31 (decimal).
Autovectoring operates in the same fashion (but is not restricted to) the EF 6800 interrupt
sequence. The basic difference is that there are six normal interrupt vectors and one NMI type
vector. As with bath the EF 6800 and the TS68C(XX)'s normal vectored interrupt, the Interrupt
service routine can be located any-where in the address space. This is due to the tact that while
the vector numbers are fixed the contents of the vector table entries are assigned by the user.
Since VMA is asserted during autovectoring. The EF 6800 peripheral address decoding should
prevent unintended accesses.
S0 S2S4wwwwwwwww wwww
ww S6 S0
CLK
A1-A23
AS
DTACK
Data Out
Data In
FC0-FC2
E
VPA
VMA
S4SGSOSZS4wwwww 3032 W H X rC U C ATE;
45
2170A–HIREL–09/05
TS68C000
Figure 2-16. Autovector Operation Timing Diagram
Although UDS and LDS are asserted, no data is read from the bus during the autovector cycle.
The vector number is generated internally).
S0 S2 S4 S6 S0 S2 S4 w w w w wwww
ww S6 S0 S2
CLK
A1-A3
A4-A23
AS
LDS
UDS*
DTACK
FC0-FC2
D0-D7
D8-D15
E
VPA
VMA
IPL0-IPL2
R/W
Autovector Operation
Normal
Cycle
Table 2-13. Dynamic Electrical Characteristics TS68C000 to EF 6800 Peripheral
Number Symbol Parameter
8 MHz 10 MHz 12.5 MHz
Unit
Limits Limits Limits
Min Max Min Max Min Max
12 CLSH Clock low to AS, DS high(1) 70 55 50 ns
18 CHRH Clock high to R/W high(1) 070060060ns
20 CHRL Clock high to R/W low (write)(1) 70 60 60 ns
23 CLDO Clock low to data out valid (write) 70 55 55 ns
27 CLDO Data in to clock low (set up time on read)(2) 15 10 10 ns
29 SHDII AS, DS high to Data in invalid (hold time on
read) 000ns
40 CLVML AS, DS high to VPA high 70 70 70 ns
41 CLET Clock low to E transition 70 55 45 ns
42 Erf E output rise and fall time 25 25 25 ns
43 VMLEH VMA low to E high 200 150 90 ns
44 SHVPH AS, DS high to VPA high 0 120 0 90 0 70 ns
TjwfififiMJ—LflfL/TVJ’L/ ,, fl 7 0% e 0% <7 a="" eo="" a:="" «o="" %="" [a="" lo="" 2="" :3)="" l0="" ,="" ‘0="" lg="" *0="" 9="" «o="" ”’="" i="" 09f="" 0—»="" -z:="" if.="" g="">
46
2170A–HIREL–09/05
TC68C000
Notes: 1. For a loading capacitance of less than or equal to 50 picofarads, subtract 5 nanoseconds from the value given in the maxi-
mum columns.
2. If the asynchronous setup time (47) requirements are satisfied, the DTACK low-to-data setup time (31) required can be
ignored. The data must only satisfy the date in clock-low setup time (27) for the following cycle.
3. The falling edge of S6 triggers both the negation of the strobes (AS and X DS) and the falling edge of E. Either of these
events can occur first, depending upon the loading on each signal specification 49 indicates the absolute maximum skew
that will occur between the rising edge of the strobes and the falling edge of the E clock.
Figure 2-17. TS68C000 to EF6800 Peripheral Timing Diagram – Best Case
Note: This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the worst case possibly
attainable.
45 ELCAI E low to control, address bus invalid
(address hold time) 30 10 10 ns
47 ASI Asynchronous input setup time(2) 20 20 20 ns
49 SHEL AS, DS high to E low(3) -7070-5555-80 ns
50 EH E width high 450 350 280 ns
51 EL E width low 700 550 440 ns
54 ELDOI E low to data out invalid 30 20 15 ns
Table 2-13. Dynamic Electrical Characteristics TS68C000 to EF 6800 Peripheral (Continued)
Number Symbol Parameter
8 MHz 10 MHz 12.5 MHz
Unit
Limits Limits Limits
Min Max Min Max Min Max
S0 S1 S2 S3 S4
A1-A23
CLK
AS
R/W
E
VPA
VMA
DATA OUT
DATA IN
23
18
41
20
42
51
41
40
43
50
42
41 12
49
18
44
45
41
54
29
27
45
S5 S6 S7 S0
wwwwwwwwwwww
41m
47
2170A–HIREL–09/05
TS68C000
Figure 2-18. TS68C000 to EF6800 Peripheral Timing Diagram – Worse Case
Note: This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the worst case possibly
attainable.
2.8 Preparation For Delivery
2.8.1 Packaging
Microcircuit are prepared for delivery in accordance with MIL-PRF-38535.
2.8.2 Certificate of Compliance
Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in
compliance with MIL-STD-883 and guarantying the parameters not tested at extreme tempera-
tures for the entire temperature range.
2.9 Handling
MOS devices must be handled with certain precautions to avoid damage due to accumulation of
static charge. Input protection devices have been designed in the chip to minimize the effect of
this static buildup. However, the following handling practices are recommended:
a) Device should be handled on benches with conductive and grounded surface.
b) Ground test equipment, tools and operator.
c) Do not handle devices by the leads.
d) Store devices in conductive foam or carriers.
e) Avoid use of plastic, rubber, or silk in MOS areas.
f) Maintain relative humidity above 50%, if practical.
S0 S1 S2 S3 S4
A1-A23
CLK
AS
R/W
E
VPA
VMA
DATA OUT
DATA IN
18
S5 S6S7S0
wwwwwww wwwww wwwwwwwwww wwwwww
20
47
23
41
42
51
43
40
27
45
54
29
49
45
12
50
41
42
18
44
®®® Ge. ®®®®@@®®®© 933933b33® W"
48
2170A–HIREL–09/05
TC68C000
2.10 Package Mechanical Data
Figure 2-19. 68-lead – Pin Grid Array
Figure 2-20. 64-lead – Ceramic Side Brazed Package
Index corner
.180 ± 010
4.57 ± 0.25
.050 ± 010
1.27 ± 0.254
.900 Typ
22.86 Typ
BOTTOM VIEWTOP VIEW
.097 ± 008
2.46 ± 0.20
.080 ± 008
2.03 ± 0.20
.065 ± 005
1.65 ± 0.13
1.060 ± .010
26.92 ± 0.25
A
B
C
D
E
F
G
H
J
K
10 98765432 1
1.060 ± 010
26.92 ± 0.25
.100 Typ
2.54 Typ
.050 ± 005
1.27 ± 0.13
.018 ± 001
0.46 ± 0.13
.018 ± 002
0.46 ± 0.05
.900 ± .010
22.86 ± 0.25
.010 ± 002
0.25 ± 0.05
.100 ± .002
2.54 ± 0.05
64 33
132
.895 ± .010
22.73 ± 0.25
.050 ± .010
1.27 ± 0.25
1.90 Max
4.83 Max
.150 Min
3.81 Min
.080 ± 009
2.03 ± 0.23
3.200 ± 030
81.28 ± 0.76
Pin N° 1 Index
r ~"IEET‘13TJj‘JL’YW‘TTT; {TV 'mttt 027 037 'o o a“ 3 o 41m 2170A7H|REL419105 —«n
49
2170A–HIREL–09/05
TS68C000
Figure 2-21. 68-lead – Leadless Ceramic Chip Carrier
Figure 2-22. 68-lead – Ceramic Quad Flat Pack
BOTTOM VIEW TOP VIEW
.050 ± 005
1.27 ± 0.13
.800 ± 008
20.32 ± 0.2
.085 ± .009
2.16 ± 0.23
.950 +.012
-.010
24.13 +0.30
-0.25
.950 +.012
-.010
24.13 +0.30
-0.25
1
2
CQFP 68
1.133-1.147
28.78-29.13
.940-.960
23.88-24.38
.021-.025
0.53-0.64
.800 BSC
20.32 BSC
.050 BSC
1.27 BSC
.940-.960
23.88-24.38
1.133-1.147
28.78-29.13
68
1
17
18 34
35
51
52
.008 M Z X Y
Pin N° 1 index
.004
.135
3.43
.018-.035
.046-0.88
.005-.010
0.13-0.25
.027-.037
0.69-0.94
0°-8°
ALP _77 HL 00000000
50
2170A–HIREL–09/05
TC68C000
2.11 Ordering Information
2.11.1 MIL-STD-883
2.11.2 DESC
Device Type Revision level
Operating frequency (MHz)
MIL-STD-883 Class B
Package:
C: Ceramic DIL
R: PGA
E: LCCC
C1: Ceramic DIL, tin dipped leads
E1: LCCC, tin dipped leads
F: CQFP
M = -55/+125°C
TS68C000 M C1 B/C 8 A
Device Type
Part number for DESC Drawing 82021
Device Type:
01: 8 MHz
02: 10 MHz
03: 12.5 MHz
Revision level
Lead finish per
MIL-M-38510
A = tin dipped
C = gold plated
Case outlines:
U: PGA 68
Y: CDIL 64
X: LCCC 68 (on request)
Z: CQFP 68 (on request)
TS68C000DESC 02 T A A
Note: Temperature range is -55°C ≤ TC ≤ +125C for DESC product
4L5
51
2170A–HIREL–09/05
TS68C000
2.11.3 Standard Product
Note: 1. For availability of the different versions, contact your Atmel sale office.
Device Type
M = -55°C/+125°C
V = -40°C/+85°C
Revision level
Operating frequency (MHz)
Package:
C: Ceramic DIL
R: PGA
E: LCCC
F: CQFP (on request)
TS68C000 M C 8 A
41m —@
Printed on recycled paper.
2170A–HIREL–09/05
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