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© 2004 Fairchild Semiconductor Corporation DS009493 www.fairchildsemi.com
April 1988
Revised January 2004
74F189 64-Bit Random Access Memory with 3-STATE Outputs
74F189
64-Bit Random Access Memory with 3-STATE Outputs
General Description
The F189 is a high-speed 64-bit RAM organized as a 16-
word by 4-bit array. Address inputs are buffered to mini-
mize loading and are fully decoded on-chip. The outputs
are 3-STATE and are in the high impedance state when-
ever the Chip Select (CS) input is HIGH. The outputs are
active only in the Read mode and the output data is the
complement of the stored data.
Features
■3-STATE outputs for data bus applications
■Buffered inputs minimize loading
■Address decoding on-chip
■Diode clamped inputs minimize ringing
Ordering Code:
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F189PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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74F189
Unit Loading/Fan Out
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Block Diagram
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
A0–A3Address Inputs 1.0/1.0 20 µA/−0.6 mA
CS Chip Select Input (Active LOW) 1.0/1.0 20 µA/−1.2 mA
WE Write Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
D0–D3Data Inputs 1.0/1.0 20 µA/−0.6 mA
O 0–O 3Inverted Data Outputs 150/40 (33.3) −3.0 mA/24 mA (20 mA)
Inputs Operation Condition of Outputs
CS WE
L L Write High Impedance
L H Read Complement of Stored Data
H X Inhibit High Impedance
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74F189
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +175°C
VCC Pin Potential to
Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output −0.5V to VCC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units VCC Conditions
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
VOH Output HIGH 10% VCC 2.5
VMin
IOH = −1 mA
Voltage 10% VCC 2.4 IOH = −3 mA
5% VCC 2.7 IOH = −1 mA
5% VCC 2.7 IOH = −3 mA
VOL Output LOW Voltage 10% VCC 0.5 V Min IOL = 24 mA
IIH Input HIGH 5.0 µAMaxV
IN = 2.7V
Current
IBVI Input HIGH Current 7.0 µAMaxV
IN = 7.0V
Breakdown Test
ICEX Output HIGH 50 µAMaxV
OUT = VCC
Leakage Current
VID Input Leakage 4.75 V 0.0 IID = 1.9 µA
Test All Other Pins Grounded
IOD Output Leakage 3.75 µA0.0
VIOD = 150 mV
Circuit Current All Other Pins Grounded
IIL Input LOW Current −0.6 mA Max VIN = 0.5V (except CS)
−1.2 VIN = 0.5V (CS)
IOZH Output Leakage Current 50 µAMaxV
OUT = 2.7V
IOZL Output Leakage Current −50 µAMaxV
OUT = 0.5V
IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V
IZZ Bus Drainage Test 500 µA0.0VV
OUT = 5.25V
ICCZ Power Supply Current 37 55 mA Max VO = HIGH Z
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74F189
AC Electrical Characteristics
AC Operating Requirements
Symbol Parameter
TA = +25°CT
A = −55°C to +125°CT
A = 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF CL = 50 pF
Min Typ Max Min Max Min Max
tPLH Access Time, HIGH or LOW 10.0 18.5 26.0 9.0 32.0 10.0 27.0 ns
tPHL An to On8.0 13.5 19.0 8.0 23.0 8.0 20.0
tPZH Access Time, HIGH or LOW 3.5 6.0 8.5 3.5 10.5 3.5 9.5 ns
tPZL CS to On5.0 9.0 13.0 5.0 15.0 5.0 14.0
tPHZ Disable Time, HIGH or LOW 2.0 4.0 6.0 2.0 8.0 2.0 7.0 ns
tPLZ CS to On3.0 5.5 8.0 2.5 10.0 3.0 9.0
tPZH Write Recovery Time, 6.5 15.0 28.0 6.5 37.5 6.5 29.0 ns
tPZL HIGH or LOW WE to On 6.5 11.0 15.5 6.5 17.5 6.5 16.5
tPHZ Disable Time, HIGH or LOW 4.0 7.0 10.0 3.5 12.0 4.0 11.0 ns
tPLZ WE to On 5.0 9.0 13.0 5.0 15.0 5.0 14.0
Symbol Parameter
TA = +25°CT
A = −55°C to +125°CT
A = 0°C to +70°C
UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V
Min Max Min Max Min Max
tS(H) Setup Time, HIGH or LOW 0 0 0
ns
tS(L) An to WE 000
tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0
tH(L) An to WE 2.0 2.0 2.0
tS(H) Setup Time, HIGH or LOW 10.0 11.0 10.0
ns
tS(L) Dn to WE 10.0 11.0 10.0
tH(H) Hold Time, HIGH or LOW 0 2.0 0
tH(L) Dn to WE 02.00
tS(L) Setup Time, LOW 0 0 0
ns
CS to WE
tH(L) Hold Time, LOW 6.0 7.5 6.0
CS to WE
tW(L) WE Pulse Width, LOW 6.0 15.0 6.0 ns
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74F189 64-Bit Random Access Memory with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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