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© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 7 1Publication Order Number:
MC3479/D
MC3479
Stepper Motor Driver
The MC3479 is designed to drive a two−phase stepper motor in the
bipolar mode. The circuit consists of four input sections, a logic
decoding/sequencing section, two driver−stages for the motor coils,
and an output to indicate the Phase A drive state.
Features
•Single Supply Operation: 7.2 to 16.5 V
•350 mA/Coil Drive Capability
•Clamp Diodes Provided for Back−EMF Suppression
•Selectable CW/CCW and Full/Half Step Operation
•Selectable High/Low Output Impedance (Half Step Mode)
•TTL/CMOS Compatible Inputs
•Input Hysteresis: 400 mV Minimum
•Phase Logic Can Be Initialized to Phase A
•Phase A Output Drive State Indication (Open−Collector)
•Pb−Free Package is Available*
CW/CCW
VM
GNDBias/SetPhase A
Logic
Driver
OIC
Driver
F/H Step
Clk Clock
Figure 1. Representative Block Diagram
L4
L3
VD
L2
L1
OIC
Full/Half
Step
CW/CCW
ORDERING INFORMATION
Device
Operating
Temperature Range Package Shipping
MC3479P
TA = 0° to +70°C
PDIP−16
25 Units / Rai
l
MC3479PG PDIP−16
(Pb−Free)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
PDIP−16
P SUFFIX
CASE 648C
(Top View)
1
OIC
GND
Clk
Bias/Set
16 VM
GND
PIN CONNECTIONS
9
8
4
7
6
5
3
2
L1
L2
Full/Half
Step
VD
CW/CCW
Phase A
L4
L3
15
14
13
12
11
10
INPUT TRUTH TABLE
Input Low Input High
CW CCW
Full Step Half Step
Hi Z Low Z
CW/CCW
Full/Half Step
OIC
Positive Edge TriggeredClk
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MARKING DIAGRAM
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
MC3479P
AWLYYWWG
1
16
MC3479
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2
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VM+ 18 Vdc
Clamp Diode Cathode Voltage (Pin 1) VDVM + 5.0 Vdc
Driver Output Voltage VOD VM + 6.0 Vdc
Drive Output Current/Coil IOD ±500 mA
Input Voltage (Logic Controls) Vin − 0.5 to + 7.0 Vdc
Bias/Set Current IBS − 10 mA
Phase A Output Voltage VOA + 18 Vdc
Phase A Sink Current IOA 20 mA
Junction Temperature TJ+ 150 °C
Storage Temperature Range Tstg − 65 to + 150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Min Max Unit
Supply Voltage VM+ 7.2 + 16.5 Vdc
Clamp Diode Cathode Voltage VDVMVM + 4.5 Vdc
Driver Output Current (Per Coil) (Note 1) IOD − 350 mA
Input Voltage (Logic Controls) Vin 0+ 5.5 Vdc
Bias/Set Current (Outputs Active) IBS −300 − 75 mA
Phase A Output Voltage VOA − VMVdc
Phase A Sink Current IOA 0 8.0 mA
Operating Ambient Temperature TA0+ 70 °C
1. See section on Power Dissipation in Application Information.
DC ELECTRICAL CHARACTERISTICS (Specifications apply over the recommended supply voltage and temperature range,
(Notes 2, 3) unless otherwise noted.)
Characteristic Pins Symbol Min Typ Max Unit
INPUT LOGIC LEVELS
Threshold Voltage (Low−to−High) 7, 8,
9, 10 VTLH − − 2.0 Vdc
Threshold Voltage (High−to−Low) VTHL 0.8 − − Vdc
Hysteresis VHYS 0.4 − − Vdc
Current: (VI = 0.4 V)
(VI = 5.5 V)
(VI = 2.7 V)
IIL −100
−
−
−
−
−
−
+100
+20
mA
DRIVER OUTPUT LEVELS
Output High Voltage (IBS = − 300 mA) IOD = − 350 mA
IOD = − 0.1 mA 2, 3,
14, 15 VOHD VM −2.0
VM −1.2 −
−−
−Vdc
Output Low Voltage (IBS = − 300 mA, IOD = 350 mA) VOLD − − 0.8 Vdc
Differential Mode Output Voltage Difference (Note 4)
(IBS = − 300 mA, IOD = 350 mA) 14, 15 DVOD
CVOD
−
−−
−0.15
0.15 Vdc
Output Leakage, Hi Z State (0 v VOD v VM, IBS = − 5.0 mA)
(0 v VOD v VM, IBS = − 300 mA, F/H = 2.0 V, OIC = 0.8 V) 14, 15 IOZ1
IOZ2
−100
−100
−
−
+100
+100
mA
CLAMP DIODES
Forward Voltage (ID = 350 mA) 1, 2,
3, 14
,
15
VDF − 2.5 3.0 Vdc
Leakage Current (Per Diode) (Pin 1 = 21 V; Outputs = 0 V; IBS = 0 mA) IDR − − 100 mA
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DC ELECTRICAL CHARACTERISTICS (Specifications apply over the recommended supply voltage and temperature range,
(Notes 2, 3) unless otherwise noted.)
Characteristic UnitMaxTypMinSymbolPins
PHASE A OUTPUT
Output Low Voltage (IOA = 8.0 mA) 11 VOLA − − 0.4 Vdc
Off State Leakage Current (VOHA = 16.5 V) IOHA − − 100 mA
POWER SUPPLY
Power Supply Current (IOD = 0 mA, IBS = − 300 mA)
(L1 = VOHD, L2 = VOLD, L3 = VOHD, L4 = VOLD)
(L1 = VOHD, L2 = VOLD, L3 = Hi Z, L4 = Hi Z)
(L1 = VOHD, L2 = VOLD, L3 = VOHD, L4 = VOHD)
16
IMW
IMZ
IMN
−
−
−
−
−
−
70
40
75
mA
BIAS/SET CURRENT
To Set Phase A 6 IBS − 5.0 − − mA
2. Algebraic convention rather than absolute values is used to designate limit values.
3. Current into a pin is designated as positive. Current out of a pin is designated as negative.
4. DVOD = ⎥VOD1,2 − VOD3,4⎥ where:VOD1,2 = (VOHD1 − VOLD2) or (VOHD2 − VOLD1), and VOD3,4 = (VOHD3 − VOLD4) or (VOHD4 − VOLD3).
PACKAGE THERMAL CHARACTERISTICS
Characteristic Symbol Min Typ Max Unit
Thermal Resistance, Junction−to−Ambient (No Heatsink) RqJA − 45 − °C/W
AC SWITCHING CHARACTERISTICS (TA = + 25°C, VM = 12 V) (See Figures 2, 3, 4) (Notes 5, 6)
Characteristic Pins Symbol Min Typ Max Unit
Clock Frequency 7 fCK 0 − 50 kHz
Clock Pulse Width (High) 7 PWCKH 10 − − ms
Clock Pulse Width (Low) 7 PWCKL 10 − − ms
Bias/Set Pulse Width 6 PWBS 10 − − ms
Setup Time (CW/CCW and F/HS) 10−7
9−7 tsu 5.0 − − ms
Hold Time (CW/CCW and F/HS) 10−7
9−7 th10 − − ms
Propagation Delay (Clk−to−Driver Output) tPCD − 8.0 − ms
Propagation Delay (Bias/Set−to−Driver Output) tPBSD − 1.0 − ms
Propagation Delay (Clk−to−Phase A Low) 7−11 tPHLA − 12 − ms
Propagation Delay (Clk−to−Phase A High) 7−11 tPLHA − 5.0 − ms
5. Algebraic convention rather than absolute values is used to designate limit values.
6. Current into a pin is designated as positive. Current out of a pin is designated as negative.
MC3479
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4
5
Phase A
+ 12 V
MC3479P
CW / CCW
F / HS
OIC
Clk
Bias/Set
56 k
6
7
8
9
10
41213
15
14
3
2
16
VM1.0 k
1.0 k
1.0 k
1.0 k
1.0 k
1.0 k
4.0 k
11
L3
L4
L1
L2
0.1 mF
+ 12 V
Figure 2. AC Test Circuit
Note: tr, tf (10% to 90%) for
input signals are p 25 ns.
Figure 3. Bias/Set Timing (Refer to Figure 2)
Bias/Set
Input
VM
PWBS
VM − 1.0 VM − 1.0
tPBSD tPBSD
(High Impedance)
0
L1 − L4
Outputs
PIN FUNCTION DESCRIPTION
Pin # Function Symbol Description
16 Power Supply VMPower supply pin for both the logic circuit and the motor coil current. Voltage range is
+ 7.2 to + 16.5 V.
4, 5,
12, 13 Ground GND Ground pins for the logic circuit and the motor coil current. The physical configuration of
the pins aids in dissipating heat from within the IC package.
1Clamp Diode Voltage VDThis pin is used to protect the outputs where large voltage spikes may occur as the
motor coils are switched. Typically a diode is connected between this pin and Pin 16.
See Figure 12.
2, 3,
14, 15 Driver Outputs L1, L2 L3,
L4 High current outputs for the motor coils. L1 and L2 are connected to one coil, and L3 and
L4 to the other coil.
6 Bias/Set B/S This pin is typically 0.7 volts below VM. The current out of this pin (through a resistor to
ground) determines the maximum output sink current. If the pin is opened (IBS < 5.0 mA)
the outputs assume a high impedance condition, while the internal logic presets to a
Phase A condition.
7 Clock Clk The positive edge of the clock input switches the outputs to the next position. This input
has no effect if Pin 6 is open.
9 Full/Half Step F/HS When low (Logic “0”), each clock input pulse will cause the motor to rotate one full step.
When high, each clock pulse will cause the motor to rotate one−half step. See Figure 7
for sequence.
10 Clockwise/
Counterclockwise CW/CCW This input allows reversing the rotation of the motor. See Figure 7 for sequence.
8Output Impedance
Control OIC This input is relevant only in the half step mode (Pin 9 > 2.0 V). When low (Logic “0”),
the two driver outputs of the non−energized coil will be in a high impedance condition.
When high the same driver outputs will be at a low impedance referenced to VM. See
Figure 7.
11 Phase A Ph A This open−collector output indicates (when low) that the driver outputs are in the Phase
A condition (L1 = L3 = VOHD, L2 = L4 = VOLD).
M
MC3479
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5
APPLICATION INFORMATION
General
The MC3479 integrated circuit is designed to drive a
stepper positioning motor in applications such as disk drives
and robotics. The outputs can provide up to 350 mA to each
of two coils of a two−phase motor. The outputs change state
with each low−to−high transition of the clock input, with the
new output state depending on the previous state, as well as
the input conditions at the logic controls.
Outputs
The outputs (L1−L4) are high current outputs (see
Figure 5), which when connected to a two−phase motor,
provide two full−bridge configurations (L3 and L4 are not
shown in Figure 5). The polarities applied to the motor coils
depend on which transistor (QH or QL) of each output is on,
which in turn depends on the inputs and the decoding
circuitry.
Note: tr, tf (10% to 90%) for
input signals are p 10 ns.
tPLHA
tPHLA
th
tsu
PWCLKL
PWCLKH
1.5 V
1.5 V
Phase A
Output
F/HS,
CW/CCW
Inputs 0
L1 − L4
Outputs
tPCD
3.0 V
0
Clk
3.0 V
Figure 4. Clock Timing (Refer to Figure 2)
6.0 V
1.5 V
Current
Drivers
and
Logic
VD
QH
QL
L2
Parasitic
Diodes
L1
Motor Coil
QL
VM
B/S
I′BS
IBS
RB
To L3, L4
Transistors
CW / CCW OIC
ClkF/HS
Inputs
Logic Decoding
Circuit
Figure 5. Output Stages
QH
The maximum sink current available at the outputs is a
function of the resistor connected between Pin 6 and ground
(see section on Bias/Set operation). Whenever the outputs
are to be in a high impedance state, both transistors (QH and
QL of Figure 5) of each output are off.
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6
VD
This pin allows for provision of a current path for the
motor coil current during switching, in order to suppress
back−EMF voltage spikes. VD is normally connected to VM
(Pin 16) through a diode (zener or regular), a resistor, or
directly. The peaks instantaneous voltage at the outputs must
not exceed VM by more than 6.0 V. The voltage drop across
the internal clamping diodes must be included in this portion
of the design (see Figure 6). Note the parasitic diodes
(Figure 5) across each QL of each output provide for a
complete circuit path for the switched current.
Figure 6. Clamp Diode Characteristics
ID (mA)
300100 2000
0
1.0
2.0
3.0
V (V)
F
Full/Half Step
When this input is at a Logic “0” (< 0.8 V), the outputs
change a full step with each clock cycle, with the sequence
direction depending on the CW/CCW input. There are four
steps (Phase A, B, C, D) for each complete cycle of the
sequencing logic. Current flows through both motor coils
during each step, as shown in Figure 7.
When taken to a Logic “1” (>2.0 V), the outputs change
a half step with each clock cycle, with the sequence direction
depending on the CW/CCW input. Eight steps (Phase A to
H) result for each complete cycle of the sequencing logic.
Phase A, C, E and G correspond (in polarity) to Phase A, B,
C, and D, respectively, of the full step sequence. Phase B, D,
F and H provide current to one motor coil, while
de−energizing the other coil. The condition of the outputs of
the de−energized coil depends on the OIC input, see Figure 7
timing diagram.
OIC
The output impedance control input determines the output
impedance to the de−energized coil when operating in the
half−step mode. When the outputs are in Phase B, D, F or H
(Figure 7) and this input is at a Logic “0” (<0.8 V), the two
outputs to the de−energized coil are in a high impedance
condition − QL and QH of both outputs (Figure 5) are off.
When this input is at a Logic “1” (>2.0 V), a low impedance
output is provided to the de−energized coil as both outputs
have QH on (QL off). To complete the low impedance path
requires connecting VD to VM as described elsewhere in this
data sheet.
Bias/Set
This pin can be used for three functions: a) determining
the maximum output sink current; b) setting the internal
logic to a known state; and c) reducing power consumption.
a) The maximum output sink current is determined by the
base drive current supplied to the lower transistors (QLs of
Figure 5) of each output, which in turn, is a function of IBS.
The appropriate value of IBS can be approximated using
Figure 11.
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Ilus pin ix opened (raised [0 VM
155
MC3479
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Figure 7. Output Sequence
Phase A
Output
(a) Full Step Mode
A
CW/CCW
A
A
AA
Bias/Set
Clk
Phase A
Output
Phase A A
(c) Half Step Mode
CD
L3
L4
F
L1
EC
L1
L2
L2
L3
L4
BD
L1
CDBHGDBC EF
(b) Half Step Mode
L2
L3
L4
GH B
BCDBCB
= Logic 0"
= Logic 1"
= Logic 1"
= High Impedance
CW/CCW = Logic 0"
F/HS = Logic 1", OIC = Logic 0"
DBC
= High Impedance
= Logic 0"
= Don′t Care
F/HS
OIC
CW/CCW
F/HS
OIC
The value of RB (between this pin and ground) is then
determined by:
RB+
VM*0.7 V
IBS
b) When this pin is opened (raised to VM) such that IBS is
< 5.0 mA, the internal logic is set to the Phase A condition, and
the four driver outputs are put into a high impedance state.
The Phase A output (Pin 11) goes active (low), and input
signals at the controls are ignored during this time. Upon
re−establishing IBS, the driver outputs become active, and
will be in the Phase A position (L1 = L3 = VOHD, L2 = L4
= VOLD). The circuit will then respond to the inputs at the
controls.
The Set function (opening this pin) can be used as a
powerup reset while supply voltages are settling. A CMOS
logic gate (powered by VM) can be used to control this pin as
shown in Figure 12.
c) Whenever the motor is not being stepped, power
dissipation in the IC and in the motor may be lowered by
reducing IBS, so as to reduce the output (motor) current.
Setting IBS to 75 mA will reduce the motor current, but will
not reset the internal logic as described above. See Figure 13
for a suggested circuit.
Power Dissipation
The power dissipated by the MC3479 must be such that
the junction temperature (TJ) does not exceed 150°C. The
power dissipated can be expressed as:
P = (VM IM) + (2 IOD) [(VM − VOHD) + VOLD]
where VM = Supply voltage;
IM = Supply current other than IOD;
IOD = Output current to each motor coil;
VOHD = Driver output high voltage;
VOLD = Driver output low voltage.
The power supply current (IM) is obtained from Figure 8.
After the power dissipation is calculated, the junction
temperature can be calculated using:
TJ = (P RqJA) + TA
where RqJA = Junction−to−ambient thermal resistance
(52°C/W for the DIP, 72°C/W for the FN Package);
TA = Ambient Temperature.
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Figure 8. Power Supply Current
50
IBS (mA)
IOD = 0
10
20
0
60
50
40
30
70
150 200 250 300 350100
IM(mA)
Figure 9. Maximum Saturation Voltage −
Driver Output Low
IOD (mA)
0 100 200 300
0.8
0.6
0.4
0.2
0
VOLD (VOLTS)
For example, assume an application where VM = 12 V, the
motor requires 200 mA/coil, operating at room temperature
with no heatsink on the IC. From Figure 11, IBS is
determined to be 95 mA.
RB is calculated:
RB = (12 − 0.7) V/95 mA
RB = 118.9 kW
From Figure 8, IM (max) is determined to be 22 mA. From
Figure 9, VOLD is 0.46 V, and from Figure 10, (VM − VOHD)
is 1.4 volts.
P = (12 0.022) + (2 0.2) (1.4 + 0.46)
P = 1.01 W
TJ = (1.01 W 52°C/W) + 25°C
TJ = 77.5°C
This temperature is well below the maximum limit. If the
calculated TJ had been higher than 150°C, a heatsink such
as the Staver Co. V−7 Series, Aavid #5802, or Thermalloy
#6012 could be used to reduce RqJA. In extreme cases,
forced air cooling should be considered.
The above calculation, and RqJA, assumes that a ground
plane is provided under the MC3479 (either or both sides of
the PC board) to aid in the heat dissipation. Single nominal
width traces leading from the four ground pins should be
avoided as this will increase TJ, as well as provide
potentially disruptive ground noise and IR drops when
switching the motor current.
Figure 10. Maximum Saturation Voltage −
Driver Output High
1.5
2.0
IOD (mA)
1.0
0.5
0
0 100 200 300
[V
M− V ] (VOLTS)
OHD
Figure 11. Bias/Set Current − Output Drive Current
140.00
120.00
100.00
80.00
60.00
40.00
20.00
0.00
0.00 50.00 100.00 150.00 200.00 250.00 300.00
IOD (mA)
IBS (mA)
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Figure 12. Typical Applications Circuit
− Suggested value for RB1 (VM = 12 V) is 150 kW.
− RB calculation (see text) must take into account
the current through RB1.
Figure 13. Power Reduction
RB
Normal
Operation
Set
OIC
Full/Half Step
CW/CCW
Clock
Phase A
Typ
2.0 kW
+V
GND
MC3479
1N5221A (3.0 V)
+V
VM
1
16
11
7
10
9
8614
15
2
3
Bias/Set
L4
L3
L2
L1
VD
Motor
MC14049UB
or equivalent
Digital Inputs
131245
Reduced
Power
Normal
Operation
Bias/Set
RB1
RB
6
MC3479
MC14049UB
or equivalent
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MC3479
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10
PACKAGE DIMENSIONS
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.744 0.783 18.90 19.90
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
E0.050 BSC 1.27 BSC
F0.040 0.70 1.02 1.78
G0.100 BSC 2.54 BSC
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L0.300 BSC 7.62 BSC
M0 10 0 10
N0.015 0.040 0.39 1.01
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
16 9
18
D
G
E
N
KC
16X
A
M
0.005 (0.13) T
SEATING
PLANE
B
M
0.005 (0.13) T
J16X
M
L
AA
B
F
T
B
PDIP−16
CASE 648C−04
ISSUE D
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