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© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 8
1Publication Order Number:
MC14067B/D
MC14067B
Analog Multiplexers /
Demultiplexers
The MC14067 multiplexer/demultiplexer is a digitally controlled
analog switch featuring low ON resistance and very low leakage
current. This device can be used in either digital or analog
applications.
The MC14067 is a 16−channel multiplexer/demultiplexer with an
inhibit and four binary control inputs A, B, C, and D. These control
inputs select 1−of−16 channels by turning ON the appropriate analog
switch (see MC14067 truth table.)
Features
•Low OFF Leakage Current
•Matched Channel Resistance
•Low Quiescent Power Consumption
•Low Crosstalk Between Channels
•Wide Operating Voltage Range: 3 to 18 V
•Low Noise
•Pin for Pin Replacement for CD4067B
•These Devices are Pb−Free and are RoHS Compliant
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage Range
(DC or Transient)
– 0.5 to VDD + 0.5 V
Iin Input Current (DC or Transient),
per Control Pin
±10 mA
Isw Switch Through Current ±25 mA
PDPower Dissipation, per Package
(Note 1)
500 mW
TAAmbient Temperature Range – 55 to + 125 _C
Tstg Storage Temperature Range – 65 to + 150 _C
TLLead Temperature
(8–Second Soldering)
260 _C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: − 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
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MARKING DIAGRAM
SOIC−24
DW SUFFIX
CASE 751E
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
14067B
AWLYYWWG
_____________________
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2
TRUTH TABLE
Control Inputs Selected
Channel
A B C D Inh
X X X X 1 None
0 0 0 0 0 X0
1 0 0 0 0 X1
0 1 0 0 0 X2
1 1 0 0 0 X3
0 0 1 0 0 X4
1 0 1 0 0 X5
0 1 1 0 0 X6
1 1 1 0 0 X7
0 0 0 1 0 X8
1 0 0 1 0 X9
0 1 0 1 0 X10
1 1 0 1 0 X11
0 0 1 1 0 X12
1 0 1 1 0 X13
0 1 1 1 0 X14
1 1 1 1 0 X15
X3
X5
X6
X7
X
X1
X2
X4 X11
X10
X9
X8
VDD
INHIBIT
X15
X14
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
13
11
12
21
22
23
24
D
C
X13
X12
B
VSS
A
X0
PIN ASSIGNMENT 16−Channel Analog
Multiplexer/Demultiplexer
CONTROLS
SWITCHES
IN/OUT
COMMON
OUT/IN
16
17
18
19
21
22
23
2
3
4
5
6
7
9
13
8
14
11
10
15
20
1
INHIBIT
A
B
C
D
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
X
VDD = PIN 24
VSS = PIN 12
FUNCTIONAL DIAGRAM
1-OF-16 DECODER
INHIBIT
A
B
C
D
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
CONTROL
INPUTS
X
IN/OUT X
OUT/IN
MC14067B
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3
ELECTRICAL CHARACTERISTICS
Characteristic Symbol VDD Test Conditions
− 55°C25_C 125_C
Unit
Min Max Min Typ (2) Max Min Max
SUPPLY REQUIREMENTS (Voltages Referenced to VSS)
Power Supply Voltage
Range
VDD −3.0 18 3.0 −18 3.0 18 V
Quiescent Current Per
Package
IDD 5.0
10
15
Control Inputs: Vin =
VSS or VDD,
Switch I/O: VSS v VI/O v
VDD, and
DVswitch v500 mV (3)
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mA
Total Supply Current
(Dynamic Plus
Quiescent,
Per Package
ID(AV) 5.0
10
15
TA = 25_C only (The
channel component,
(Vin – Vout)/Ron, is
not included.)
(0.07 mA/kHz) f + IDD
Typical (0.20 mA/kHz) f + IDD
(0.36 mA/kHz) f + IDD
mA
CONTROL INPUTS — INHIBIT, A, B, C, D (Voltages Referenced to VSS)
Low−Level Input Voltage VIL 5.0
10
15
Ron = per spec,
Ioff = per spec
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
V
High−Level Input Voltage VIH 5.0
10
15
Ron = per spec,
Ioff = per spec
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
V
Input Leakage Current Iin 15 Vin = 0 or VDD −± 0.1 −±0.00001 ± 0.1 −1.0 mA
Input Capacitance Cin —− − − 5.0 7.5 − − pF
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y (Voltages Referenced to VSS)
Recommended Peak−to−
Peak Voltage Into or
Out of the Switch
VI/O −Channel On or Off 0 VDD 0−VDD 0 VDD Vp−p
Recommended Static or
Dynamic Voltage
Across the Switch (3)
(Figure 1)
DVswitch −Channel On 0 600 0 −600 0 300 mV
Output Offset Voltage VOO −Vin = 0 V, No Load − − − 10 − − − mV
ON Resistance Ron 5.0
10
15
DVswitch v 500 mV (3),
Vin = VIL or VIH
(Control), and Vin
0 to VDD (Switch)
−
−
−
800
400
220
−
−
−
250
120
80
1050
500
280
−
−
−
1300
550
320
W
DON Resistance
Between
Any Two Channels
in the Same Package
DRon 5.0
10
15
−
−
−
70
50
45
−
−
−
25
10
10
70
50
45
−
−
−
135
95
65
W
Off−Channel Leakage
Current (Figure 2)
Ioff 15 Vin = VIL or VIH
(Control) Channel to
Channel or Any One
Channel
−± 100 −± 0.05 ±100 −±1000 nA
Capacitance, Switch I/O CI/O −Inhibit = VDD −— — 10 − − − pF
Capacitance, Common O/I CO/I −Inhibit = VDD
(MC14067B)
(MC14097B)
−
−
−
−
−
−
100
60
−
−
−
−
−
−
pF
Capacitance, Feedthrough
(Channel Off)
CI/O −
−
Pins Not Adjacent
Pins Adjacent
− − − 0.47 − − − pF
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DVswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e.
the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
MC14067B
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4
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic Symbol
VDD – VSS
Vdc Typ (4) Max Unit
Propagation Delay Times
Channel Input−to−Channel Output (RL = 200 kW)
MC14067B
tPLH,t
PHL
(Figure 3) 5.0
10
15
35
15
12
90
40
30
ns
Propagation Delay Times
Channel Input−to−Channel Output (RL = 1.0 kW)
MC14067B
tPLH,t
PHL
(Figure 3) 5.0
10
15
50
30
20
ns
Control Input−to−Channel Output
Channel Turn−On Time (RL = 10 kW)
MC14067B
tPZH, tPZL
(Figure 4)
tPHZ,t
PLZ
(Figure 4)
5.0
10
15
240
115
75
600
290
190
ns
Channel Turn−Off Time (RL = 300 kW)
MC14067B
5.0
10
15
250
120
75
625
300
190
ns
Channel Turn−Off Time (RL = 10 kW)
MC14067B
5.0
10
15
625
450
350
ns
Any Pair of Address Inputs to Output
MC14067B
tPLH, tPHL
5.0
10
15
280
115
85
700
290
215
ns
Second Harmonic Distortion
(RL = 10 kW, f = 1 kHz, Vin = 5 Vp−p)
−10 0.3 −%
ON Channel Bandwidth
[RL = 50 W, Vin = 1/2 (VDD – VSS) p−p(sine−wave)]
20 Log10 (Vout/Vin) = − 3 dB MC14067B
BW
(Figure 5) 10 15 −
MHz
Off Channel Feedthrough Attenuation
[RL = 50 W, Vin = 1/2 (VDD−VSS) p−p(sine−wave)]
fin = 20 MHz – MC14067B
−
(Figure 5)
10 – 40 −dB
Channel Separation
[RL = 1 kW, Vin = 1/2 (VDD−VSS) p−p (sine−wave)]
fin = 20 MHz
−
(Figure 6)
10 – 40 −dB
Crosstalk, Control Inputs−to−Common O/I
(R1 = 1 kW, RL = 10 kW,
Control tr = tf = 20 ns, Inhibit = VSS)
−
(Figure 7)
10 30 −mV
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14067B
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5
ORDERING INFORMATION
Device Package Shipping†
MC14067BDWG SOIC−24
(Pb−Free)
30 Units / Rail
NLV14067BDWG*
MC14067BDWR2G SOIC−24
(Pb−Free)
1000 Units / Tape & Reel
NLV14067BDWR2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
Figure 1. DV Across Switch Figure 2. Off Channel Leakage
CONTROL
SECTION
OF IC
SOURCE
V
LOAD
ON SWITCH
CONTROL
SECTION
OF IC
OFF CHANNEL UNDER TEST
OTHER
CHANNEL(S)
VDD
VSS
VSS
VDD
VSS
VDD
A
Figure 3. Propagation Delay Test Circuit
and Waveforms Vin to Vout
Figure 4. Turn−On and Delay Turn−Off
Test Circuit and Waveforms
VDD
Vout
CL = 50 pF
RL
Vin
A
B
C
D
INH
Vin
Vout
20 ns 20 ns
VDD
VSS
50%
10%
tPLH tPHL
90%
50%
PULSE
GENERATOR
VCA
B
C
D
INH RLCL = 50 pF
Vout
Vin
VDD VSS VSS VDD
VX
20 ns 20 ns
90%
50%
10%
90%
10%
Vout
Vout
VC
50%
50%
tPZH, tPZL tPHZ, tPLZ
Vin = VDD
VX = VSS
Vin = VSS
VX = VDD
MC14067B
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6
Figure 5. Bandwidth and Off−Channel
Feedthrough Attenuation
Figure 6. Channel Separation
(Adjacent Channels Used for Setup)
A, B, and C inputs used to turn ON or OFF
the switch under test.
A
B
C
D
INH
Vin
RLCL = 50 pF
Vout
VDD RL
Vout
CL = 50 pF
RL
Vin
A
B
C
D
INH OFF
ON
Figure 7. Crosstalk, Control to Common O/I
VC
A
B
C
D
INH RLCL = 50 pF
Vout
R1
Figure 8. Channel Resistance (RON) Test Circuit
VDD
VSS
10 k
KEITHLEY 160
DIGITAL
MULTIMETER
X-Y
PLOTTER
1 kW
RANGE
VDD
VA
VB
A
B
C
D
INH
CL
VDD
Vout
Vout
VB
VA50%
50%
tPHL tPLH
50%
Figure 9. Propagation Delay, Any Pair of
Address Inputs to Output
MC14067B
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7
TYPICAL RESISTANCE CHARACTERISTICS
Figure 10. VDD = 7.5 V, VSS = − 7.5 V Figure 11. VDD = 5.0 V, VSS = − 5.0 V
RON, “ON” RESISTANCE (OHMS)
350
300
250
200
150
100
0
50
-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 125°C
25°C
-55°C
RON, “ON” RESISTANCE (OHMS)
350
300
250
200
150
100
0
50
-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 125°C
25°C
-55°C
Figure 12. VDD = 2.5 V, VSS = − 2.5 V
RON, “ON” RESISTANCE (OHMS)
700
600
500
400
300
200
0
100
-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 125°C
25°C
-55°C
Figure 13. Comparison at 25°C, VDD = −VSS
RON, “ON” RESISTANCE (OHMS)
350
300
250
200
150
100
0
50
-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 25°C
VDD = 2.5 V
5.0 V
7.5 V
it?
MC14067B
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8
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Multiplexer /
Demultiplexer. The 0−to−5 V Digital Control signal is used
to directly control a 5 Vp−p analog signal.
The digital control logic levels are determined by VDD
and VSS. The VDD voltage is the logic high voltage; the VSS
voltage is logic low. For the example. VDD = + 5 V = logic
high at the control inputs; VSS = GND = 0 V = logic low.
The maximum analog signal level is determined by VDD
and VSS. The analog voltage must swing neither higher than
VDD nor lower than VSS. The example shows a 5 Vp−p
signal which allows no margin at either peak. If voltage
transients above VDD and/or below VSS are anticipated on
the analog channels, external diodes (Dx) are recommended
as shown in Figure B. These diodes should be small signal
types able to absorb the maximum anticipated current surges
during clipping.
The absolute maximum potential difference between VDD
and VSS is 18.0 volts. Most parameters are specified up to
15 V which is the recommended maximum difference
between VDD and VSS.
Figure A. Application Example
+5 V
VDD VSS
5 Vp-p
ANALOG SIGNAL
0-TO-5 V DIGITAL
CONTROL SIGNALS
SWITCH
I/O
MC14067B
COMMON
O/I
5 Vp-p
ANALOG SIGNAL
+5.0 V
+2.5 V
GND
+5 V
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
Figure B. External Germanium or Schottky Clipping Diodes
VDD VDD
VSS VSS
DXDX
DXDX
SWITCH
I/O
COMMON
O/I
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9
PACKAGE DIMENSIONS
SOIC−24 WB
CASE 751E−04
ISSUE F
b
M
0.25 C
SEATING
PLANE
A1
M
L
DETAIL A
END VIEW
h_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b AND c APPLY TO THE FLAT SEC-
TION OF THE LEAD AND ARE MEASURED
BETWEEN 0.10 AND 0.25 FROM THE LEAD TIP.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 mm PER SIDE. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED
0.25 PER SIDE. DIMENSIONS D AND E1 ARE
DETERMINED AT DATUM H.
5. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
NOTE 3
PIN 1
12
1
24 13
TOP VIEW DIM MIN MAX
MILLIMETERS
A2.35 2.65
b0.35 0.49
e1.27 BSC
h0.25 0.75
c0.23 0.32
A1 0.13 0.29
L0.41 0.90
M0 8
__
D
E1
SIDE VIEW
11.00
24X
0.52
24X
1.62
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
E10.30 BSC
RECOMMENDED
INDICATOR A B
0.25 C
24X
B
A
C
A
NOTE 5
x 45
c
NOTE 3 DETAIL A
C
H
D15.25 15.54
E1 7.40 7.60
E
S S
e
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reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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Phone: 81−3−5817−1050
MC14067B/D
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