DDR4 High-Speed Dynamic Random-Access Memory

High-speed dynamic random-access memory internally configured as sixteen banks from ISSI

Image of ISSI DDR4 High-Speed Dynamic Random-Access MemoryThe DDR4 SDRAM, from ISSI, Integrated Silicon Solution Inc., is a high-speed, dynamic, random-access memory internally configured as sixteen banks, four bank groups with four banks for each bank group (for x4/x8), and eight banks, 2 bank groups with 4 banks for each bank group (for x16 DRAM). The DDR4 SDRAM uses an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit-wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half clock cycle data transfers at the I/O pins.

Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ”chopped” burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE command which is then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be activated (BG0-BG1 in x4/8 and BG0 in x16 select the bank group, BA0-BA1 select the bank, and A0-A14 select the row) . The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto-precharge command is to be issued (via A10), and select BC4 or BL8 mode ”on the fly” (via A12) if enabled in the mode register.

Features Applications
  • Standard voltage: VDD = VDDQ = 1.2 V, VPP = 2.5 V
  • Data integrity (auto self-refresh with temp sensor)
  • DRAM access bandwidth (separated I/O gating structures by bank group and fine granularity refresh)
  • Signal synchronization (read/write leveling)
  • Reliability and error handling (write CRC and boundary scan)
  • Signal integrity (read preamble training and Per DRAM addressability)
  • Power saving (maximum power saving)
  • Telecom/networking
    • SDN, NFV
    • Access and aggregation nodes
    • Switches and routers
    • Packet optical transport
    • Network storage [PON OLT, DSLAM, CMTS, wireless]
  • Automotive
    • Infotainment
    • Telematics
    • Driver information systems
  • Industrial
    • Human machine interface
    • Embedded computing

DDR4 High-Speed Dynamic Random-Access Memory

ImageManufacturer Part NumberVoltage - SupplyAvailable QuantityView Details
IS43QR16256A-083RBLIS43QR16256A-083RBL1.14 V ~ 1.26 V0View Details
IS43QR16256A-093PBLIIS43QR16256A-093PBLI1.14 V ~ 1.26 V0View Details
IS43QR16256A-083RBLIIS43QR16256A-083RBLI1.14 V ~ 1.26 V0View Details
Published: 2016-09-26