While random signals like noise are often considered a problem, there are applications such as communications and device tests which depend on random bit sequences and noise due to their unique characteristics. However, for one-off tests or designers on a tight budget, it may not be feasible to purchase a purpose-built pseudo-random binary sequence (PRBS) or arbitrary waveform generator. In such cases it is more cost effective to build one using readily available CMOS devices.
This article will describe the useful roles of PRBS and noise in electronics. It will then introduce readily available CMOS ICs and show how they can be used to generate the required pseudo-random noise and binary sequences.
The role of “good” noise
White, random noise has a flat spectrum in the frequency domain. The averaged output amplitude spectrum of an amplifier or filter excited by a white noise source, will give the amplitude frequency response of that device.
In communications, a data stream for a CDMA transmitter is multiplied by a pseudo-random binary sequence (PRBS). It can then be transmitted over the same RF channel as multiple other signals. Correlating the composite signal with the same PRBS at the receiver end will extract the original data stream with little or no interference. Given that these random signals are so useful, it is important to be able to generate them as needed.
Generating a PRBS
A PRBS is a periodic, deterministic signal consisting of a series of digital ones and zeros. The duration of the one or zero levels are a multiple of the PRBS generator’s clock period. The pattern of ones and zeros is random within the pattern repetition period of the generator (Figure 1).
Figure 1: A PRBS7 signal is a PRBS test signal with a 7-bit length which has a period of 27 – 1, or 127 bits. This signal is clocked at 1 MHz and shows a periodicity of 127 ms, as marked by the oscilloscope cursors. (Image source: Digi-Key Electronics)
The signal in Figure 1 is a PRBS7 test signal produced by a generator with 7 stages which contain 127 bits within each pattern period. Within each period the bit pattern is random, but the whole sequence repeats identically every 127 clock periods.
These test signals can be generated in software or hardware. The advantage of a hardware implementation for testing is that the signals are available externally to drive the device being tested.
Linear feedback shift register
The hardware implementation of a PRBS is done using linear feedback shift registers (LFSR). Some shift registers are arranged in series with feedback from the later stages back to the input using EXCLUSIVE-OR/NOR gates. The number of shift registers used determines the length or duration of the pattern (Figure 2).
Figure 2: Examples of a four-bit LFSR implemented with both exclusive OR and exclusive NOR feedback logic. The feedback taps determine the sequence of data states. (Image source: Digi-Key Electronics)
While many feedback configurations are possible, almost all designs use taps that produce maximal length sequences so that the total number of states is equal to (2N-1), where N is the number of shift register stages. Table 1 summarizes the taps for maximal length sequences for LFSR lengths from 2 to 32. These taps are not exclusive. Note that more than one maximal length polynomial may exist for any given shift register length.
Table 1: Summary of the taps for maximal length sequences for LFSR lengths from 2 to 32. (Image source: Digi-Key Electronics)
Our example uses a 15 stage LFSR which produces a random sequence with a length of 32,767 bits, known as a PRBS15 test sequence. Longer sequences can be achieved by using a LFSR with a greater number of stages. The limitation of using a PRBS test sequence is the duration of the test. A 15-bit sequence clocked at 500 kHz takes 65 milliseconds (ms). A 31-bit sequence would take 4295 seconds, or about 72 minutes.
The example in Figure 2 uses four shift registers to produce data patterns with 15 distinct states. Note that both configurations have a single forbidden state. In the case of the exclusive OR feedback model, the all zeros state is not used because once loaded the shift register stays locked in that state. Likewise, the all ones state is forbidden in the exclusive NOR implementation. Tables 2 and 3 show the data patterns of both configurations for the four-bit LFSR, using feedback taps from stages three and four.
Table 2 and 3: Data patterns for OR and NOR configurations shown in Figure 1. (Image source: Digi-Key Electronics)
Both implementations start out from a known state, all ones in the OR case and all zeros in the NOR case. These four-bit maximal length LFSRs provide 15 possible states (2N-1) as shown in the tables.
The output data pattern is periodic as it repeats after 15 clocks. The pattern is also deterministic, in that for a given configuration and a known starting state the output can be predicted. The output pattern is however random within the 15 count period.
Designing a pseudo-random binary sequence generator
A practical, low-cost PRBS generator design based upon the LFSR implementation using the Texas Instruments CD4015BM96 dual quad static shift register and the CD4030BM96 quad XOR gate is shown in Figure 3.
Figure 3: A simplified schematic for a PRBS15 generator using the Texas Instruments CD4015BM96 dual quad static shift register and the CD4030BM96 quad XOR gate. (Image source Digi-Key Electronics)
This generator uses 16 D type flip-flops (eight per IC) with feedback taps at the 14th and 15th producing a PRBS15 data pattern. The feedback connection is via an XOR gate, which is then inverted to form an XNOR configured LFSR. This data pattern has a length of 32767 bits which is a duration of about 65 ms at a 500 kHz clock rate. Longer patterns can be achieved by using longer shift registers with an appropriate change in the feedback taps. Extending the design to a 31-bit pattern increases the pattern duration to over 2 billion states (about 72 minutes at a 500 kHz clock frequency).
The generator is initialized to the all-zeros state at power up using a CD4093BM96 Schmitt trigger NAND gate (IC5) and a simple RC network. The clock is provided by a simple CMOS oscillator running near 500 kHz. The digital output can be taken from any of the shift register Q outputs. In this case Q14 was used.
The output of the generator along with the fast Fourier transform (FFT) of the output is displayed on an oscilloscope in Figure 4.
Figure 4: The output of the generator (top trace) is expanded horizontally in the middle trace to see the detailed structure. The FFT of the generator output (bottom trace) shows that the spectrum is flat below 1/10th of the clock rate. (Image source: Digi-Key)
The FFT of the digital noise shows the expected sin(x)/x response of a pulsed waveform with zeros at multiples of the clock frequency. The spectrum is quite flat out to about 10% of the clock frequency. This is the key to extracting white noise from the digital output using low-pass filtering.
White noise generator
White noise is noise that is spectrally flat over its frequency range. The power spectral density and power per unit bandwidth is constant over the noise bandwidth. Filtering the digital noise output, the PRBS generator will produce white noise.
While an analog filter could be used, it would be restricted to a specific clock frequency. By using a finite impulse response (FIR) low-pass digital filter, the filter cutoff will track any changes in the clock frequency. Additionally, the FIR filter can provide very low cutoff frequencies that would require very large capacitors in an analog filter. The FIR filter combines the weighted sum of the shift register outputs. The weighting required to produce a rectangular low pass filter response in the frequency domain is sin(x)/x in the time domain (Figure 5).
Figure 5: The output stage of the generator employs sin(x)/x weighted samples from the shift register outputs to implement an FIR low pass filter. Since the sin(x)/x weighting requires negative terms, a differential amplifier is used to sum both positive and negative weighted components. (Image Source Digi-Key)
The weighted shift register outputs are summed in the differential amplifier, which is built using three sections of an LM324KDR quad operational amplifier. The upper resistor bank represents the negative components of the sin(x)/x weighting. The lower resistor bank represents the positive values. The outputs Q3 and Q12 are not connected because they represent the zero crossing points of the sin(x)/x function. The resultant white noise output exhibits the classic Gaussian probability density function (PDF) (Figure 6).
Figure 6: The PRBS digital noise (top two traces) along with the analog white noise output (third trace from the top). The histogram of the white noise, bottom trace, exhibits the classic bell-shaped normal or Gaussian PDF. (Image source: Digi-Key)
The white noise signal is the third down from the top. Below that is the histogram of the noise which exhibits the expected normal or Gaussian probability distribution. The white noise is bandlimited to 5% of the clock frequency, or 25 kHz, which is suitable for audio frequency test purposes.
As shown, readily available CMOS ICs can be used to produce both a pseudo-random binary sequence, as well as analog white noise for communications and test purposes. The BOM for the parts used is inexpensive, making it ideal for academic research, hobbyists, and economy conscious engineers and technicians.